X-Git-Url: https://git.sesse.net/?a=blobdiff_plain;f=m68kfpu.c;h=e836933f8401f459f1f968574a708fd945868f4d;hb=HEAD;hp=b103541c78a926965800aaa9f535f50feb5bdb83;hpb=3494518e3baa4c2d937c6b12f3969e845d83c8b7;p=pistorm diff --git a/m68kfpu.c b/m68kfpu.c index b103541..e836933 100644 --- a/m68kfpu.c +++ b/m68kfpu.c @@ -4,6 +4,8 @@ #include #include "softfloat/softfloat.h" +#include "m68kcpu.h" + float_status status; extern void exit(int); @@ -78,15 +80,15 @@ static inline floatx80 double_to_fx80(double in) return float64_to_floatx80(*d, &status); } -static inline floatx80 load_extended_float80(uint32 ea) +static inline floatx80 load_extended_float80(m68ki_cpu_core *state, uint32 ea) { uint32 d1,d2; uint16 d3; floatx80 fp; - d3 = m68ki_read_16(ea); - d1 = m68ki_read_32(ea+4); - d2 = m68ki_read_32(ea+8); + d3 = m68ki_read_16(state, ea); + d1 = m68ki_read_32(state, ea + 4); + d2 = m68ki_read_32(state, ea + 8); fp.high = d3; fp.low = ((uint64)d1<<32) | (d2 & 0xffffffff); @@ -94,24 +96,24 @@ static inline floatx80 load_extended_float80(uint32 ea) return fp; } -static inline void store_extended_float80(uint32 ea, floatx80 fpr) +static inline void store_extended_float80(m68ki_cpu_core *state, uint32 ea, floatx80 fpr) { - m68ki_write_16(ea+0, fpr.high); - m68ki_write_16(ea+2, 0); - m68ki_write_32(ea+4, (fpr.low>>32)&0xffffffff); - m68ki_write_32(ea+8, fpr.low&0xffffffff); + m68ki_write_16(state, ea + 0, fpr.high); + m68ki_write_16(state, ea + 2, 0); + m68ki_write_32(state, ea + 4, (fpr.low >> 32) & 0xffffffff); + m68ki_write_32(state, ea + 8, fpr.low & 0xffffffff); } -static inline floatx80 load_pack_float80(uint32 ea) +static inline floatx80 load_pack_float80(m68ki_cpu_core *state, uint32 ea) { uint32 dw1, dw2, dw3; floatx80 result; double tmp; char str[128], *ch; - dw1 = m68ki_read_32(ea); - dw2 = m68ki_read_32(ea+4); - dw3 = m68ki_read_32(ea+8); + dw1 = m68ki_read_32(state, ea); + dw2 = m68ki_read_32(state, ea + 4); + dw3 = m68ki_read_32(state, ea + 8); ch = &str[0]; if (dw1 & 0x80000000) // mantissa sign @@ -153,7 +155,7 @@ static inline floatx80 load_pack_float80(uint32 ea) return result; } -static inline void store_pack_float80(uint32 ea, int k, floatx80 fpr) +static inline void store_pack_float80(m68ki_cpu_core *state, uint32 ea, int k, floatx80 fpr) { uint32 dw1, dw2, dw3; char str[128], *ch; @@ -249,7 +251,7 @@ static inline void store_pack_float80(uint32 ea, int k, floatx80 fpr) { dw2 &= pkmask2[17]; dw3 &= pkmask3[17]; -// m68ki_cpu.fpcr |= (need to set OPERR bit) +// state->fpcr |= (need to set OPERR bit) } } @@ -280,12 +282,12 @@ static inline void store_pack_float80(uint32 ea, int k, floatx80 fpr) dw1 |= (j << 16); } - m68ki_write_32(ea, dw1); - m68ki_write_32(ea+4, dw2); - m68ki_write_32(ea+8, dw3); + m68ki_write_32(state, ea, dw1); + m68ki_write_32(state, ea + 4, dw2); + m68ki_write_32(state, ea + 8, dw3); } -static inline void SET_CONDITION_CODES(floatx80 reg) +static inline void SET_CONDITION_CODES(m68ki_cpu_core *state, floatx80 reg) { // u64 *regi; @@ -318,7 +320,7 @@ static inline void SET_CONDITION_CODES(floatx80 reg) } } -static inline int TEST_CONDITION(int condition) +static inline int TEST_CONDITION(m68ki_cpu_core *state, int condition) { int n = (REG_FPSR & FPCC_N) != 0; int z = (REG_FPSR & FPCC_Z) != 0; @@ -380,7 +382,7 @@ static inline int TEST_CONDITION(int condition) return r; } -static uint8 READ_EA_8(int ea) +static uint8 READ_EA_8(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -394,27 +396,27 @@ static uint8 READ_EA_8(int ea) case 2: // (An) { uint32 ea = REG_A[reg]; - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 3: // (An)+ { uint32 ea = EA_AY_PI_8(); - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 4: // -(An) { uint32 ea = EA_AY_PD_8(); - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 5: // (d16, An) { uint32 ea = EA_AY_DI_8(); - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_8(); - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 7: { @@ -422,29 +424,29 @@ static uint8 READ_EA_8(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); - return m68ki_read_8(ea); + uint32 ea = (uint32) OPER_I_16(state); + return m68ki_read_8(state, ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 2: // (d16, PC) { uint32 ea = EA_PCDI_8(); - return m68ki_read_8(ea); + return m68ki_read_8(state, ea); } case 3: // (PC) + (Xn) + d8 { - uint32 ea = EA_PCIX_8(); - return m68ki_read_8(ea); + uint32 ea = EA_PCIX_8(); + return m68ki_read_8(state, ea); } case 4: // # { - return OPER_I_8(); + return OPER_I_8(state); } default: fatalerror("M68kFPU: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -456,7 +458,7 @@ static uint8 READ_EA_8(int ea) return 0; } -static uint16 READ_EA_16(int ea) +static uint16 READ_EA_16(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -470,27 +472,27 @@ static uint16 READ_EA_16(int ea) case 2: // (An) { uint32 ea = REG_A[reg]; - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 3: // (An)+ { uint32 ea = EA_AY_PI_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 4: // -(An) { uint32 ea = EA_AY_PD_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 5: // (d16, An) { uint32 ea = EA_AY_DI_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 7: { @@ -498,29 +500,29 @@ static uint16 READ_EA_16(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); - return m68ki_read_16(ea); + uint32 ea = (uint32) OPER_I_16(state); + return m68ki_read_16(state, ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 2: // (d16, PC) { uint32 ea = EA_PCDI_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 3: // (PC) + (Xn) + d8 { uint32 ea = EA_PCIX_16(); - return m68ki_read_16(ea); + return m68ki_read_16(state, ea); } case 4: // # { - return OPER_I_16(); + return OPER_I_16(state); } default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -533,7 +535,7 @@ static uint16 READ_EA_16(int ea) return 0; } -static uint32 READ_EA_32(int ea) +static uint32 READ_EA_32(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -547,27 +549,27 @@ static uint32 READ_EA_32(int ea) case 2: // (An) { uint32 ea = REG_A[reg]; - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 3: // (An)+ { uint32 ea = EA_AY_PI_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 4: // -(An) { uint32 ea = EA_AY_PD_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 5: // (d16, An) { uint32 ea = EA_AY_DI_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 7: { @@ -575,29 +577,29 @@ static uint32 READ_EA_32(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); - return m68ki_read_32(ea); + uint32 ea = (uint32) OPER_I_16(state); + return m68ki_read_32(state, ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 2: // (d16, PC) { uint32 ea = EA_PCDI_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 3: // (PC) + (Xn) + d8 { uint32 ea = EA_PCIX_32(); - return m68ki_read_32(ea); + return m68ki_read_32(state, ea); } case 4: // # { - return OPER_I_32(); + return OPER_I_32(state); } default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -608,7 +610,7 @@ static uint32 READ_EA_32(int ea) return 0; } -static uint64 READ_EA_64(int ea) +static uint64 READ_EA_64(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -619,38 +621,38 @@ static uint64 READ_EA_64(int ea) case 2: // (An) { uint32 ea = REG_A[reg]; - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 3: // (An)+ { uint32 ea = REG_A[reg]; REG_A[reg] += 8; - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 4: // -(An) { uint32 ea = REG_A[reg]-8; REG_A[reg] -= 8; - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 5: // (d16, An) { uint32 ea = EA_AY_DI_32(); - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_32(); - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 7: @@ -659,29 +661,29 @@ static uint64 READ_EA_64(int ea) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - return (uint64)(m68ki_read_32(ea)) << 32 | (uint64)(m68ki_read_32(ea+4)); + return (uint64)(m68ki_read_32(state, ea)) << 32 | (uint64)(m68ki_read_32(state, ea + 4)); } case 3: // (PC) + (Xn) + d8 { uint32 ea = EA_PCIX_32(); - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } case 4: // # { - h1 = OPER_I_32(); - h2 = OPER_I_32(); + h1 = OPER_I_32(state); + h2 = OPER_I_32(state); return (uint64)(h1) << 32 | (uint64)(h2); } case 2: // (d16, PC) { uint32 ea = EA_PCDI_32(); - h1 = m68ki_read_32(ea+0); - h2 = m68ki_read_32(ea+4); + h1 = m68ki_read_32(state, ea + 0); + h2 = m68ki_read_32(state, ea + 4); return (uint64)(h1) << 32 | (uint64)(h2); } default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -695,7 +697,7 @@ static uint64 READ_EA_64(int ea) } -static floatx80 READ_EA_FPE(uint32 ea) +static floatx80 READ_EA_FPE(m68ki_cpu_core *state, uint32 ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -706,7 +708,7 @@ static floatx80 READ_EA_FPE(uint32 ea) case 2: // (An) { uint32 ea = REG_A[reg]; - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); break; } @@ -714,28 +716,28 @@ static floatx80 READ_EA_FPE(uint32 ea) { uint32 ea = REG_A[reg]; REG_A[reg] += 12; - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); break; } case 4: // -(An) { uint32 ea = REG_A[reg]-12; REG_A[reg] -= 12; - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); break; } case 5: // (d16, An) { // FIXME: will fail for fmovem uint32 ea = EA_AY_DI_32(); - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); break; } case 6: // (An) + (Xn) + d8 { // FIXME: will fail for fmovem uint32 ea = EA_AY_IX_32(); - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); break; } @@ -745,31 +747,31 @@ static floatx80 READ_EA_FPE(uint32 ea) { case 1: // (xxx) { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); } break; case 2: // (d16, PC) { uint32 ea = EA_PCDI_32(); - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); } break; case 3: // (d16,PC,Dx.w) { uint32 ea = EA_PCIX_32(); - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); } break; case 4: // immediate (JFF) { uint32 ea = REG_PC; - fpr = load_extended_float80(ea); + fpr = load_extended_float80(state, ea); REG_PC += 12; } break; @@ -787,7 +789,7 @@ static floatx80 READ_EA_FPE(uint32 ea) return fpr; } -static floatx80 READ_EA_PACK(int ea) +static floatx80 READ_EA_PACK(m68ki_cpu_core *state, int ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -798,7 +800,7 @@ static floatx80 READ_EA_PACK(int ea) case 2: // (An) { uint32 ea = REG_A[reg]; - fpr = load_pack_float80(ea); + fpr = load_pack_float80(state, ea); break; } @@ -806,7 +808,7 @@ static floatx80 READ_EA_PACK(int ea) { uint32 ea = REG_A[reg]; REG_A[reg] += 12; - fpr = load_pack_float80(ea); + fpr = load_pack_float80(state, ea); break; } @@ -817,7 +819,7 @@ static floatx80 READ_EA_PACK(int ea) case 3: // (d16,PC,Dx.w) { uint32 ea = EA_PCIX_32(); - fpr = load_pack_float80(ea); + fpr = load_pack_float80(state, ea); } break; @@ -834,7 +836,7 @@ static floatx80 READ_EA_PACK(int ea) return fpr; } -static void WRITE_EA_8(int ea, uint8 data) +static void WRITE_EA_8(m68ki_cpu_core *state, int ea, uint8 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -849,31 +851,31 @@ static void WRITE_EA_8(int ea, uint8 data) case 2: // (An) { uint32 ea = REG_A[reg]; - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 3: // (An)+ { uint32 ea = EA_AY_PI_8(); - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 4: // -(An) { uint32 ea = EA_AY_PD_8(); - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 5: // (d16, An) { uint32 ea = EA_AY_DI_8(); - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_8(); - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 7: @@ -882,16 +884,16 @@ static void WRITE_EA_8(int ea, uint8 data) { case 1: // (xxx).B { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } case 2: // (d16, PC) { uint32 ea = EA_PCDI_16(); - m68ki_write_8(ea, data); + m68ki_write_8(state, ea, data); break; } default: fatalerror("M68kFPU: WRITE_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -902,7 +904,7 @@ static void WRITE_EA_8(int ea, uint8 data) } } -static void WRITE_EA_16(int ea, uint16 data) +static void WRITE_EA_16(m68ki_cpu_core *state, int ea, uint16 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -917,31 +919,31 @@ static void WRITE_EA_16(int ea, uint16 data) case 2: // (An) { uint32 ea = REG_A[reg]; - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 3: // (An)+ { uint32 ea = EA_AY_PI_16(); - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 4: // -(An) { uint32 ea = EA_AY_PD_16(); - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 5: // (d16, An) { uint32 ea = EA_AY_DI_16(); - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_16(); - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 7: @@ -950,16 +952,16 @@ static void WRITE_EA_16(int ea, uint16 data) { case 1: // (xxx).W { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } case 2: // (d16, PC) { uint32 ea = EA_PCDI_16(); - m68ki_write_16(ea, data); + m68ki_write_16(state, ea, data); break; } default: fatalerror("M68kFPU: WRITE_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -970,7 +972,7 @@ static void WRITE_EA_16(int ea, uint16 data) } } -static void WRITE_EA_32(int ea, uint32 data) +static void WRITE_EA_32(m68ki_cpu_core *state, int ea, uint32 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -990,31 +992,31 @@ static void WRITE_EA_32(int ea, uint32 data) case 2: // (An) { uint32 ea = REG_A[reg]; - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 3: // (An)+ { uint32 ea = EA_AY_PI_32(); - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 4: // -(An) { uint32 ea = EA_AY_PD_32(); - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 5: // (d16, An) { uint32 ea = EA_AY_DI_32(); - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_32(); - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 7: @@ -1023,22 +1025,22 @@ static void WRITE_EA_32(int ea, uint32 data) { case 0: // (xxx).W { - uint32 ea = OPER_I_16(); - m68ki_write_32(ea, data); + uint32 ea = OPER_I_16(state); + m68ki_write_32(state, ea, data); break; } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } case 2: // (d16, PC) { uint32 ea = EA_PCDI_32(); - m68ki_write_32(ea, data); + m68ki_write_32(state, ea, data); break; } default: fatalerror("M68kFPU: WRITE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -1049,7 +1051,7 @@ static void WRITE_EA_32(int ea, uint32 data) } } -static void WRITE_EA_64(int ea, uint64 data) +static void WRITE_EA_64(m68ki_cpu_core *state, int ea, uint64 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1059,16 +1061,16 @@ static void WRITE_EA_64(int ea, uint64 data) case 2: // (An) { uint32 ea = REG_A[reg]; - m68ki_write_32(ea, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 3: // (An)+ { uint32 ea = REG_A[reg]; REG_A[reg] += 8; - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 4: // -(An) @@ -1076,22 +1078,22 @@ static void WRITE_EA_64(int ea, uint64 data) uint32 ea; REG_A[reg] -= 8; ea = REG_A[reg]; - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 5: // (d16, An) { uint32 ea = EA_AY_DI_32(); - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 6: // (An) + (Xn) + d8 { uint32 ea = EA_AY_IX_32(); - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 7: @@ -1100,18 +1102,18 @@ static void WRITE_EA_64(int ea, uint64 data) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } case 2: // (d16, PC) { uint32 ea = EA_PCDI_32(); - m68ki_write_32(ea+0, (uint32)(data >> 32)); - m68ki_write_32(ea+4, (uint32)(data)); + m68ki_write_32(state, ea + 0, (uint32) (data >> 32)); + m68ki_write_32(state, ea + 4, (uint32) (data)); break; } default: fatalerror("M68kFPU: WRITE_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -1122,7 +1124,7 @@ static void WRITE_EA_64(int ea, uint64 data) } } -static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) +static void WRITE_EA_FPE(m68ki_cpu_core *state, uint32 ea, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1133,7 +1135,7 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) { uint32 ea; ea = REG_A[reg]; - store_extended_float80(ea, fpr); + store_extended_float80(state, ea, fpr); break; } @@ -1141,7 +1143,7 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) { uint32 ea; ea = REG_A[reg]; - store_extended_float80(ea, fpr); + store_extended_float80(state, ea, fpr); REG_A[reg] += 12; break; } @@ -1151,13 +1153,13 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) uint32 ea; REG_A[reg] -= 12; ea = REG_A[reg]; - store_extended_float80(ea, fpr); + store_extended_float80(state, ea, fpr); break; } case 5: // (d16, An) { uint32 ea = EA_AY_DI_32(); - store_extended_float80(ea, fpr); + store_extended_float80(state, ea, fpr); break; } @@ -1173,7 +1175,7 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) } } -static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) +static void WRITE_EA_PACK(m68ki_cpu_core *state, int ea, int k, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1184,7 +1186,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) { uint32 ea; ea = REG_A[reg]; - store_pack_float80(ea, k, fpr); + store_pack_float80(state, ea, k, fpr); break; } @@ -1192,7 +1194,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) { uint32 ea; ea = REG_A[reg]; - store_pack_float80(ea, k, fpr); + store_pack_float80(state, ea, k, fpr); REG_A[reg] += 12; break; } @@ -1202,7 +1204,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) uint32 ea; REG_A[reg] -= 12; ea = REG_A[reg]; - store_pack_float80(ea, k, fpr); + store_pack_float80(state, ea, k, fpr); break; } @@ -1219,7 +1221,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) } -static void fpgen_rm_reg(uint16 w2) +static void fpgen_rm_reg(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int rm = (w2 >> 14) & 0x1; @@ -1236,42 +1238,42 @@ static void fpgen_rm_reg(uint16 w2) { case 0: // Long-Word Integer { - sint32 d = READ_EA_32(ea); + sint32 d = READ_EA_32(state, ea); source = int32_to_floatx80(d); break; } case 1: // Single-precision Real { - uint32 d = READ_EA_32(ea); + uint32 d = READ_EA_32(state, ea); source = float32_to_floatx80(d, &status); break; } case 2: // Extended-precision Real { - source = READ_EA_FPE(ea); + source = READ_EA_FPE(state, ea); break; } case 3: // Packed-decimal Real { - source = READ_EA_PACK(ea); + source = READ_EA_PACK(state, ea); break; } case 4: // Word Integer { - sint16 d = READ_EA_16(ea); + sint16 d = READ_EA_16(state, ea); source = int32_to_floatx80((sint32)d); break; } case 5: // Double-precision Real { - uint64 d = READ_EA_64(ea); + uint64 d = READ_EA_64(state, ea); source = float64_to_floatx80(d, &status); break; } case 6: // Byte Integer { - sint8 d = READ_EA_8(ea); + sint8 d = READ_EA_8(state, ea); source = int32_to_floatx80((sint32)d); break; } @@ -1391,7 +1393,7 @@ static void fpgen_rm_reg(uint16 w2) // handle it right here, the usual opmode bits aren't valid in the FMOVECR case REG_FP[dst] = source; //FIXME mame doesn't use SET_CONDITION_CODES here - SET_CONDITION_CODES(REG_FP[dst]); // JFF when destination is a register, we HAVE to update FPCR + SET_CONDITION_CODES(state, REG_FP[dst]); // JFF when destination is a register, we HAVE to update FPCR USE_CYCLES(4); return; } @@ -1413,7 +1415,7 @@ static void fpgen_rm_reg(uint16 w2) case 0x00: // FMOVE { REG_FP[dst] = source; - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(4); break; } @@ -1423,14 +1425,14 @@ static void fpgen_rm_reg(uint16 w2) temp = floatx80_to_int32(source, &status); REG_FP[dst] = int32_to_floatx80(temp); //FIXME mame doesn't use SET_CONDITION_CODES here - SET_CONDITION_CODES(REG_FP[dst]); // JFF needs update condition codes + SET_CONDITION_CODES(state, REG_FP[dst]); // JFF needs update condition codes USE_CYCLES(4); break; } case 0x02: // FSINH { REG_FP[dst] = floatx80_sinh(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } @@ -1440,113 +1442,118 @@ static void fpgen_rm_reg(uint16 w2) temp = floatx80_to_int32_round_to_zero(source, &status); REG_FP[dst] = int32_to_floatx80(temp); //FIXME mame doesn't use SET_CONDITION_CODES here - SET_CONDITION_CODES(REG_FP[dst]); // JFF needs update condition codes + SET_CONDITION_CODES(state, REG_FP[dst]); // JFF needs update condition codes break; } case 0x45: // FDSQRT case 0x41: // FSSQRT case 0x04: // FSQRT + case 0x05: // FSQRT { REG_FP[dst] = floatx80_sqrt(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(109); break; } case 0x06: // FLOGNP1 + case 0x07: // FLOGNP1 { REG_FP[dst] = floatx80_lognp1 (source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(594); // for MC68881 break; } case 0x08: // FETOXM1 { REG_FP[dst] = floatx80_etoxm1(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(6); break; } case 0x09: // FTANH { REG_FP[dst] = floatx80_tanh(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x0a: // FATAN + case 0x0b: // FATAN { REG_FP[dst] = floatx80_atan(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x0c: // FASIN { REG_FP[dst] = floatx80_asin(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x0d: // FATANH { REG_FP[dst] = floatx80_atanh(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x0e: // FSIN { REG_FP[dst] = floatx80_sin(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x0f: // FTAN { REG_FP[dst] = floatx80_tan(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x10: // FETOX { REG_FP[dst] = floatx80_etox(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x11: // FTWOTOX { REG_FP[dst] = floatx80_twotox(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x12: // FTENTOX + case 0x13: // FTENTOX { REG_FP[dst] = floatx80_tentox(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x14: // FLOGN { REG_FP[dst] = floatx80_logn(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(548); // for MC68881 break; } case 0x15: // FLOG10 { REG_FP[dst] = floatx80_log10(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(604); // for MC68881 break; } case 0x16: // FLOG2 + case 0x17: // FLOG2 { REG_FP[dst] = floatx80_log2(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(604); // for MC68881 break; } @@ -1556,31 +1563,32 @@ static void fpgen_rm_reg(uint16 w2) { REG_FP[dst] = source; REG_FP[dst].high &= 0x7fff; - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(3); break; } case 0x19: // FCOSH { REG_FP[dst] = floatx80_cosh(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(64); break; } case 0x5e: // FDNEG case 0x5a: // FSNEG case 0x1a: // FNEG + case 0x1b: // FNEG { REG_FP[dst] = source; REG_FP[dst].high ^= 0x8000; - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(3); break; } case 0x1c: // FACOS { REG_FP[dst] = floatx80_acos(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(604); // for MC68881 break; break; @@ -1588,21 +1596,21 @@ static void fpgen_rm_reg(uint16 w2) case 0x1d: // FCOS { REG_FP[dst] = floatx80_cos(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x1e: // FGETEXP { REG_FP[dst] = floatx80_getexp(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(6); break; } case 0x1f: // FGETMAN { REG_FP[dst] = floatx80_getman(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(6); break; } @@ -1612,7 +1620,7 @@ static void fpgen_rm_reg(uint16 w2) { REG_FP[dst] = floatx80_div(REG_FP[dst], source, &status); //FIXME mame doesn't use SET_CONDITION_CODES here - SET_CONDITION_CODES(REG_FP[dst]); // JFF + SET_CONDITION_CODES(state, REG_FP[dst]); // JFF USE_CYCLES(43); break; } @@ -1623,7 +1631,7 @@ static void fpgen_rm_reg(uint16 w2) uint64_t q; flag s; REG_FP[dst] = floatx80_rem(REG_FP[dst], source, &q, &s, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); status.float_rounding_mode = mode; USE_CYCLES(43); // guess break; @@ -1633,7 +1641,7 @@ static void fpgen_rm_reg(uint16 w2) case 0x22: // FADD { REG_FP[dst] = floatx80_add(REG_FP[dst], source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(9); break; } @@ -1642,7 +1650,7 @@ static void fpgen_rm_reg(uint16 w2) case 0x23: // FMUL { REG_FP[dst] = floatx80_mul(REG_FP[dst], source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(11); break; } @@ -1659,7 +1667,7 @@ static void fpgen_rm_reg(uint16 w2) uint64_t q; flag s; REG_FP[dst] = floatx80_rem(REG_FP[dst], source, &q, &s, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); status.float_rounding_mode = mode; USE_CYCLES(43); // guess break; @@ -1667,23 +1675,30 @@ static void fpgen_rm_reg(uint16 w2) case 0x26: // FSCALE { REG_FP[dst] = floatx80_scale(REG_FP[dst], source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(46); // (better?) guess break; } case 0x27: // FSGLMUL { REG_FP[dst] = floatx80_sglmul(REG_FP[dst], source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(11); // ? (value is from FMUL) break; } - case 0x6a: // FDSUB + case 0x6c: // FDSUB case 0x68: // FSSUB case 0x28: // FSUB + case 0x29: // FSUB + case 0x2a: // FSUB + case 0x2b: // FSUB + case 0x2c: // FSUB + case 0x2d: // FSUB + case 0x2e: // FSUB + case 0x2f: // FSUB { REG_FP[dst] = floatx80_sub(REG_FP[dst], source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(9); break; } @@ -1698,24 +1713,30 @@ static void fpgen_rm_reg(uint16 w2) { REG_FP[dst] = floatx80_cos(source, &status); REG_FP[w2&7] = floatx80_sin(source, &status); - SET_CONDITION_CODES(REG_FP[dst]); + SET_CONDITION_CODES(state, REG_FP[dst]); USE_CYCLES(75); break; } case 0x38: // FCMP + case 0x39: // FCMP + case 0x3c: // FCMP + case 0x3d: // FCMP { floatx80 res; res = floatx80_sub(REG_FP[dst], source, &status); - SET_CONDITION_CODES(res); + SET_CONDITION_CODES(state, res); USE_CYCLES(7); break; } case 0x3a: // FTST + case 0x3b: // FTST + case 0x3e: // FTST + case 0x3f: // FTST { floatx80 res; res = source; - SET_CONDITION_CODES(res); + SET_CONDITION_CODES(state, res); USE_CYCLES(7); break; } @@ -1724,7 +1745,7 @@ static void fpgen_rm_reg(uint16 w2) } } -static void fmove_reg_mem(uint16 w2) +static void fmove_reg_mem(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int src = (w2 >> 7) & 0x7; @@ -1736,25 +1757,25 @@ static void fmove_reg_mem(uint16 w2) case 0: // Long-Word Integer { sint32 d = (sint32)floatx80_to_int32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 1: // Single-precision Real { uint32 d = floatx80_to_float32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 2: // Extended-precision Real { - WRITE_EA_FPE(ea, REG_FP[src]); + WRITE_EA_FPE(state, ea, REG_FP[src]); break; } case 3: // Packed-decimal Real with Static K-factor { // sign-extend k k = (k & 0x40) ? (k | 0xffffff80) : (k & 0x7f); - WRITE_EA_PACK(ea, k, REG_FP[src]); + WRITE_EA_PACK(state, ea, k, REG_FP[src]); break; } case 4: // Word Integer @@ -1764,7 +1785,7 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_16(ea, (sint16)value); + WRITE_EA_16(state, ea, (sint16) value); break; } case 5: // Double-precision Real @@ -1773,7 +1794,7 @@ static void fmove_reg_mem(uint16 w2) d = floatx80_to_float64(REG_FP[src], &status); - WRITE_EA_64(ea, d); + WRITE_EA_64(state, ea, d); break; } case 6: // Byte Integer @@ -1783,12 +1804,12 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_8(ea, (sint8)value); + WRITE_EA_8(state, ea, (sint8) value); break; } case 7: // Packed-decimal Real with Dynamic K-factor { - WRITE_EA_PACK(ea, REG_D[k>>4], REG_FP[src]); + WRITE_EA_PACK(state, ea, REG_D[k >> 4], REG_FP[src]); break; } } @@ -1796,7 +1817,7 @@ static void fmove_reg_mem(uint16 w2) USE_CYCLES(12); } -static void fmove_fpcr(uint16 w2) +static void fmove_fpcr(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int dir = (w2 >> 13) & 0x1; @@ -1818,30 +1839,30 @@ static void fmove_fpcr(uint16 w2) if (dir) // From system control reg to { - if (regsel & 4) { m68ki_write_32(address, REG_FPCR); address += 4; } - if (regsel & 2) { m68ki_write_32(address, REG_FPSR); address += 4; } - if (regsel & 1) { m68ki_write_32(address, REG_FPIAR); address += 4; } + if (regsel & 4) { m68ki_write_32(state, address, REG_FPCR); address += 4; } + if (regsel & 2) { m68ki_write_32(state, address, REG_FPSR); address += 4; } + if (regsel & 1) { m68ki_write_32(state, address, REG_FPIAR); address += 4; } } else // From to system control reg { - if (regsel & 4) { REG_FPCR = m68ki_read_32(address); address += 4; } - if (regsel & 2) { REG_FPSR = m68ki_read_32(address); address += 4; } - if (regsel & 1) { REG_FPIAR = m68ki_read_32(address); address += 4; } + if (regsel & 4) { REG_FPCR = m68ki_read_32(state, address); address += 4; } + if (regsel & 2) { REG_FPSR = m68ki_read_32(state, address); address += 4; } + if (regsel & 1) { REG_FPIAR = m68ki_read_32(state, address); address += 4; } } } else { if (dir) // From system control reg to { - if (regsel & 4) WRITE_EA_32(ea, REG_FPCR); - if (regsel & 2) WRITE_EA_32(ea, REG_FPSR); - if (regsel & 1) WRITE_EA_32(ea, REG_FPIAR); + if (regsel & 4) WRITE_EA_32(state, ea, REG_FPCR); + if (regsel & 2) WRITE_EA_32(state, ea, REG_FPSR); + if (regsel & 1) WRITE_EA_32(state, ea, REG_FPIAR); } else // From to system control reg { - if (regsel & 4) REG_FPCR = READ_EA_32(ea); - if (regsel & 2) REG_FPSR = READ_EA_32(ea); - if (regsel & 1) REG_FPIAR = READ_EA_32(ea); + if (regsel & 4) REG_FPCR = READ_EA_32(state, ea); + if (regsel & 2) REG_FPSR = READ_EA_32(state, ea); + if (regsel & 1) REG_FPIAR = READ_EA_32(state, ea); } } @@ -1896,7 +1917,7 @@ static void fmove_fpcr(uint16 w2) USE_CYCLES(10); } -static void fmovem(uint16 w2) +static void fmovem(m68ki_cpu_core *state, uint16 w2) { int i; int ea = REG_IR & 0x3f; @@ -1934,11 +1955,11 @@ static void fmovem(uint16 w2) { case 5: // (d16, An) case 6: // (An) + (Xn) + d8 - store_extended_float80(mem_addr, REG_FP[i]); + store_extended_float80(state, mem_addr, REG_FP[i]); mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[i]); + WRITE_EA_FPE(state, ea, REG_FP[i]); break; } @@ -1958,11 +1979,11 @@ static void fmovem(uint16 w2) { case 5: // (d16, An) case 6: // (An) + (Xn) + d8 - store_extended_float80(mem_addr, REG_FP[7-i]); + store_extended_float80(state, mem_addr, REG_FP[7 - i]); mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[7-i]); + WRITE_EA_FPE(state, ea, REG_FP[7 - i]); break; } @@ -1994,11 +2015,11 @@ static void fmovem(uint16 w2) { case 5: // (d16, An) case 6: // (An) + (Xn) + d8 - REG_FP[7-i] = load_extended_float80(mem_addr); + REG_FP[7-i] = load_extended_float80(state, mem_addr); mem_addr += 12; break; default: - REG_FP[7-i] = READ_EA_FPE(ea); + REG_FP[7-i] = READ_EA_FPE(state, ea); break; } USE_CYCLES(2); @@ -2012,84 +2033,84 @@ static void fmovem(uint16 w2) } } -static void fscc() +static void fscc(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; - int condition = (sint16)(OPER_I_16()); + int condition = (sint16)(OPER_I_16(state)); - WRITE_EA_8(ea, TEST_CONDITION(condition) ? 0xff : 0); + WRITE_EA_8(state, ea, TEST_CONDITION(state, condition) ? 0xff : 0); USE_CYCLES(7); // ??? } -static void fbcc16(void) +static void fbcc16(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = (sint16)(OPER_I_16()); + offset = (sint16)(OPER_I_16(state)); // TODO: condition and jump!!! - if (TEST_CONDITION(condition)) + if (TEST_CONDITION(state, condition)) { m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset-2); + m68ki_branch_16(state, offset - 2); } USE_CYCLES(7); } -static void fbcc32(void) +static void fbcc32(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = OPER_I_32(); + offset = OPER_I_32(state); // TODO: condition and jump!!! - if (TEST_CONDITION(condition)) + if (TEST_CONDITION(state, condition)) { m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset-4); + m68ki_branch_32(state, offset - 4); } USE_CYCLES(7); } -void m68040_fpu_op0() +void m68040_fpu_op0(m68ki_cpu_core *state) { - m68ki_cpu.fpu_just_reset = 0; + state->fpu_just_reset = 0; switch ((REG_IR >> 6) & 0x3) { case 0: { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); switch ((w2 >> 13) & 0x7) { case 0x0: // FPU ALU FP, FP case 0x2: // FPU ALU ea, FP { - fpgen_rm_reg(w2); + fpgen_rm_reg(state, w2); break; } case 0x3: // FMOVE FP, ea { - fmove_reg_mem(w2); + fmove_reg_mem(state, w2); break; } case 0x4: // FMOVEM ea, FPCR case 0x5: // FMOVEM FPCR, ea { - fmove_fpcr(w2); + fmove_fpcr(state, w2); break; } case 0x6: // FMOVEM ea, list case 0x7: // FMOVEM list, ea { - fmovem(w2); + fmovem(state, w2); break; } @@ -2106,7 +2127,7 @@ void m68040_fpu_op0() printf("M68kFPU: unimplemented FDBcc main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); break; default: // FScc (?) - fscc(); + fscc(state); return; } fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); @@ -2114,12 +2135,12 @@ void m68040_fpu_op0() } case 2: // FBcc disp16 { - fbcc16(); + fbcc16(state); break; } case 3: // FBcc disp32 { - fbcc32(); + fbcc32(state); break; } @@ -2127,18 +2148,18 @@ void m68040_fpu_op0() } } -static int perform_fsave(uint32 addr, int inc) +static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc) { - if(m68ki_cpu.cpu_type & CPU_TYPE_040) + if(state->cpu_type & CPU_TYPE_040) { if(inc) { - m68ki_write_32(addr, 0x41000000); + m68ki_write_32(state, addr, 0x41000000); return 4 -4; } else { - m68ki_write_32(addr, 0x41000000); + m68ki_write_32(state, addr, 0x41000000); return -4 +4; } } @@ -2146,30 +2167,30 @@ static int perform_fsave(uint32 addr, int inc) if (inc) { // 68881 IDLE, version 0x1f - m68ki_write_32(addr, 0x1f180000); - m68ki_write_32(addr+4, 0); - m68ki_write_32(addr+8, 0); - m68ki_write_32(addr+12, 0); - m68ki_write_32(addr+16, 0); - m68ki_write_32(addr+20, 0); - m68ki_write_32(addr+24, 0x70000000); + m68ki_write_32(state, addr, 0x1f180000); + m68ki_write_32(state, addr + 4, 0); + m68ki_write_32(state, addr + 8, 0); + m68ki_write_32(state, addr + 12, 0); + m68ki_write_32(state, addr + 16, 0); + m68ki_write_32(state, addr + 20, 0); + m68ki_write_32(state, addr + 24, 0x70000000); return 7*4 -4; } else { - m68ki_write_32(addr+4-4, 0x70000000); - m68ki_write_32(addr+4-8, 0); - m68ki_write_32(addr+4-12, 0); - m68ki_write_32(addr+4-16, 0); - m68ki_write_32(addr+4-20, 0); - m68ki_write_32(addr+4-24, 0); - m68ki_write_32(addr+4-28, 0x1f180000); + m68ki_write_32(state, addr + 4 - 4, 0x70000000); + m68ki_write_32(state, addr + 4 - 8, 0); + m68ki_write_32(state, addr + 4 - 12, 0); + m68ki_write_32(state, addr + 4 - 16, 0); + m68ki_write_32(state, addr + 4 - 20, 0); + m68ki_write_32(state, addr + 4 - 24, 0); + m68ki_write_32(state, addr + 4 - 28, 0x1f180000); return -7*4 +4; } } // FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0 -static void do_frestore_null(void) +static void do_frestore_null(m68ki_cpu_core *state) { int i; @@ -2184,36 +2205,36 @@ static void do_frestore_null(void) // Mac IIci at 408458e6 wants an FSAVE of a just-restored NULL frame to also be NULL // The PRM says it's possible to generate a NULL frame, but not how/when/why. (need the 68881/68882 manual!) - m68ki_cpu.fpu_just_reset = 1; + state->fpu_just_reset = 1; } -void m68040_do_fsave(uint32 addr, int reg, int inc) +void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc) { - if (m68ki_cpu.fpu_just_reset) + if (state->fpu_just_reset) { - m68ki_write_32(addr, 0); + m68ki_write_32(state, addr, 0); } else { // we normally generate an IDLE frame - int delta = perform_fsave(addr, inc); + int delta = perform_fsave(state, addr, inc); if(reg != -1) REG_A[reg] += delta; } } -void m68040_do_frestore(uint32 addr, int reg) +void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg) { - uint32 temp = m68ki_read_32(addr); + uint32 temp = m68ki_read_32(state, addr); // check for nullptr frame if (temp & 0xff000000) { // we don't handle non-nullptr frames - m68ki_cpu.fpu_just_reset = 0; + state->fpu_just_reset = 0; if (reg != -1) { - uint8 m40 = !!(m68ki_cpu.cpu_type & CPU_TYPE_040); + uint8 m40 = !!(state->cpu_type & CPU_TYPE_040); // how about an IDLE frame? if (!m40 && ((temp & 0x00ff0000) == 0x00180000)) { @@ -2235,11 +2256,11 @@ void m68040_do_frestore(uint32 addr, int reg) } else { - do_frestore_null(); + do_frestore_null(state); } } -void m68040_fpu_op1() +void m68040_fpu_op1(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; int mode = (ea >> 3) & 0x7; @@ -2254,27 +2275,27 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 3: // (An)+ addr = EA_AY_PI_32(); printf("FSAVE mode %d, reg A%d=0x%08x\n",mode,reg,REG_A[reg]); - m68040_do_fsave(addr, -1, 1); // FIXME: -1 was reg + m68040_do_fsave(state, addr, -1, 1); // FIXME: -1 was reg break; case 4: // -(An) addr = EA_AY_PD_32(); - m68040_do_fsave(addr, reg, 0); // FIXME: -1 was reg + m68040_do_fsave(state, addr, reg, 0); // FIXME: -1 was reg break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 7: // @@ -2284,13 +2305,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } default: @@ -2311,22 +2332,22 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 3: // (An)+ addr = EA_AY_PI_32(); - m68040_do_frestore(addr, reg); + m68040_do_frestore(state, addr, reg); break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 7: // @@ -2336,13 +2357,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } default: @@ -2361,26 +2382,26 @@ void m68040_fpu_op1() } } -void m68881_ftrap() +void m68881_ftrap(m68ki_cpu_core *state) { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); // now check the condition - if (TEST_CONDITION(w2 & 0x3f)) + if (TEST_CONDITION(state, w2 & 0x3f)) { // trap here - m68ki_exception_trap(EXCEPTION_TRAPV); + m68ki_exception_trap(state, EXCEPTION_TRAPV); } else // fall through, requires eating the operand { switch (REG_IR & 0x7) { case 2: // word operand - OPER_I_16(); + OPER_I_16(state); break; case 3: // long word operand - OPER_I_32(); + OPER_I_32(state); break; case 4: // no operand