From: Marco Costalba <mcostalba@gmail.com>
Date: Fri, 26 Apr 2013 16:45:54 +0000 (+0200)
Subject: Cache line aligned TT
X-Git-Url: https://git.sesse.net/?p=stockfish;a=commitdiff_plain;h=083fe5812485597e13943b690cc24a8f25c0d140;hp=083fe5812485597e13943b690cc24a8f25c0d140

Cache line aligned TT

Let TT clusters (16*4=64 bytes) to hold on a singe cache line.
This avoids the need for the double prefetch.

Original patches by Lucas and Jean-Francois that has also tested
on his AMD FX:

BIG HASHTABLE

./stockfish bench 1024 1 18 > /dev/null

Before:
1437642 nps
1426519 nps
1438493 nps

After:
1474482 nps
1476375 nps
1475877 nps

SMALL HASHTABLE

./stockfish bench 128 1 18 > /dev/null

Before:
1435207 nps
1435586 nps
1433741 nps

After:
1479143 nps
1471042 nps
1472286 nps

No functional change.
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