2 Copyright 2005-2011 Intel Corporation. All Rights Reserved.
4 This file is part of Threading Building Blocks.
6 Threading Building Blocks is free software; you can redistribute it
7 and/or modify it under the terms of the GNU General Public License
8 version 2 as published by the Free Software Foundation.
10 Threading Building Blocks is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
12 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with Threading Building Blocks; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 As a special exception, you may use this file as part of a free software
20 library without restriction. Specifically, if other files instantiate
21 templates or use macros or inline functions from this file, or you compile
22 this file and link it with other files to produce an executable, this
23 file does not by itself cause the resulting executable to be covered by
24 the GNU General Public License. This exception does not however
25 invalidate any other reasons why the executable file might be covered by
26 the GNU General Public License.
29 #ifndef __TBB_machine_H
30 #error Do not include this file directly; include tbb_machine.h instead
33 #if defined(__INTEL_COMPILER)
34 #define __TBB_release_consistency_helper() __asm { __asm nop }
35 #elif _MSC_VER >= 1300
36 extern "C" void _ReadWriteBarrier();
37 #pragma intrinsic(_ReadWriteBarrier)
38 #define __TBB_release_consistency_helper() _ReadWriteBarrier()
40 #error Unsupported compiler - need to define __TBB_release_consistency_helper to support it
43 #define __TBB_full_memory_fence() __asm { __asm mfence }
45 #define __TBB_WORDSIZE 4
46 #define __TBB_BIG_ENDIAN 0
48 #if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
49 // Workaround for overzealous compiler warnings in /Wp64 mode
50 #pragma warning (push)
51 #pragma warning (disable: 4244 4267)
55 __int64 __TBB_EXPORTED_FUNC __TBB_machine_cmpswp8 (volatile void *ptr, __int64 value, __int64 comparand );
56 __int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchadd8 (volatile void *ptr, __int64 addend );
57 __int64 __TBB_EXPORTED_FUNC __TBB_machine_fetchstore8 (volatile void *ptr, __int64 value );
58 void __TBB_EXPORTED_FUNC __TBB_machine_store8 (volatile void *ptr, __int64 value );
59 __int64 __TBB_EXPORTED_FUNC __TBB_machine_load8 (const volatile void *ptr);
62 #define __TBB_DEFINE_ATOMICS(S,T,U,A,C) \
63 static inline T __TBB_machine_cmpswp##S ( volatile void * ptr, U value, U comparand ) { \
65 volatile T *p = (T *)ptr; \
66 __TBB_release_consistency_helper(); \
71 __asm mov A , comparand \
72 __asm lock cmpxchg [edx], C \
75 __TBB_release_consistency_helper(); \
79 static inline T __TBB_machine_fetchadd##S ( volatile void * ptr, U addend ) { \
81 volatile T *p = (T *)ptr; \
82 __TBB_release_consistency_helper(); \
87 __asm lock xadd [edx], A \
90 __TBB_release_consistency_helper(); \
94 static inline T __TBB_machine_fetchstore##S ( volatile void * ptr, U value ) { \
96 volatile T *p = (T *)ptr; \
97 __TBB_release_consistency_helper(); \
102 __asm lock xchg [edx], A \
103 __asm mov result, A \
105 __TBB_release_consistency_helper(); \
109 __TBB_DEFINE_ATOMICS(1, __int8, __int8, al, cl)
110 __TBB_DEFINE_ATOMICS(2, __int16, __int16, ax, cx)
111 __TBB_DEFINE_ATOMICS(4, __int32, __int32, eax, ecx)
112 __TBB_DEFINE_ATOMICS(W, ptrdiff_t, ptrdiff_t, eax, ecx)
114 static inline __int32 __TBB_machine_lg( unsigned __int64 i ) {
124 static inline void __TBB_machine_OR( volatile void *operand, __int32 addend ) {
133 static inline void __TBB_machine_AND( volatile void *operand, __int32 addend ) {
142 static inline void __TBB_machine_pause (__int32 delay ) {
154 #define __TBB_CompareAndSwap1(P,V,C) __TBB_machine_cmpswp1(P,V,C)
155 #define __TBB_CompareAndSwap2(P,V,C) __TBB_machine_cmpswp2(P,V,C)
156 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
157 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
158 #define __TBB_CompareAndSwapW(P,V,C) __TBB_machine_cmpswpW(P,V,C)
160 #define __TBB_FetchAndAdd1(P,V) __TBB_machine_fetchadd1(P,V)
161 #define __TBB_FetchAndAdd2(P,V) __TBB_machine_fetchadd2(P,V)
162 #define __TBB_FetchAndAdd4(P,V) __TBB_machine_fetchadd4(P,V)
163 #define __TBB_FetchAndAdd8(P,V) __TBB_machine_fetchadd8(P,V)
164 #define __TBB_FetchAndAddW(P,V) __TBB_machine_fetchaddW(P,V)
166 #define __TBB_FetchAndStore1(P,V) __TBB_machine_fetchstore1(P,V)
167 #define __TBB_FetchAndStore2(P,V) __TBB_machine_fetchstore2(P,V)
168 #define __TBB_FetchAndStore4(P,V) __TBB_machine_fetchstore4(P,V)
169 #define __TBB_FetchAndStore8(P,V) __TBB_machine_fetchstore8(P,V)
170 #define __TBB_FetchAndStoreW(P,V) __TBB_machine_fetchstoreW(P,V)
172 // Should define this:
173 #define __TBB_Store8(P,V) __TBB_machine_store8(P,V)
174 #define __TBB_Load8(P) __TBB_machine_load8(P)
175 #define __TBB_AtomicOR(P,V) __TBB_machine_OR(P,V)
176 #define __TBB_AtomicAND(P,V) __TBB_machine_AND(P,V)
178 // Definition of other functions
179 extern "C" __declspec(dllimport) int __stdcall SwitchToThread( void );
180 #define __TBB_Yield() SwitchToThread()
181 #define __TBB_Pause(V) __TBB_machine_pause(V)
182 #define __TBB_Log2(V) __TBB_machine_lg(V)
184 // Use generic definitions from tbb_machine.h
185 #undef __TBB_TryLockByte
186 #undef __TBB_LockByte
188 #if defined(_MSC_VER)&&_MSC_VER<1400
189 static inline void* __TBB_machine_get_current_teb () {
191 __asm mov eax, fs:[0x18]
197 #if defined(_MSC_VER) && !defined(__INTEL_COMPILER)
198 #pragma warning (pop)
199 #endif // warnings 4244, 4267 are back
201 // API to retrieve/update FPU control setting
202 #define __TBB_CPU_CTL_ENV_PRESENT 1
204 struct __TBB_cpu_ctl_env_t {
208 inline void __TBB_get_cpu_ctl_env ( __TBB_cpu_ctl_env_t* ctl ) {
215 inline void __TBB_set_cpu_ctl_env ( const __TBB_cpu_ctl_env_t* ctl ) {