#if defined (MODULE_NAME_IS_i420_yuy2_mmx)
/* re-enable FPU registers */
- __asm__ __volatile__ ( "emms" );
+ MMX_END;
#endif
#if defined (MODULE_NAME_IS_i420_yuy2_altivec)
p_line1 += i_dest_margin;
p_line2 += i_dest_margin;
}
- /* make sure all SSE2 stores are visible thereafter */
- __asm__ __volatile__ ( "sfence" );
}
else
{
p_line2 += i_dest_margin;
}
}
+ /* make sure all SSE2 stores are visible thereafter */
+ SSE2_END;
#endif // defined(MODULE_NAME_IS_i420_yuy2_sse2)
}
#if defined (MODULE_NAME_IS_i420_yuy2_mmx)
/* re-enable FPU registers */
- __asm__ __volatile__ ( "emms" );
+ MMX_END;
#endif
#if defined (MODULE_NAME_IS_i420_yuy2_altivec)
p_line1 += i_dest_margin;
p_line2 += i_dest_margin;
}
- /* make sure all SSE2 stores are visible thereafter */
- __asm__ __volatile__ ( "sfence" );
}
else
{
p_line2 += i_dest_margin;
}
}
+ /* make sure all SSE2 stores are visible thereafter */
+ SSE2_END;
#endif // defined(MODULE_NAME_IS_i420_yuy2_sse2)
}
#if defined (MODULE_NAME_IS_i420_yuy2_mmx)
/* re-enable FPU registers */
- __asm__ __volatile__ ( "emms" );
+ MMX_END;
#endif
#if defined (MODULE_NAME_IS_i420_yuy2_altivec)
p_line1 += i_dest_margin;
p_line2 += i_dest_margin;
}
- /* make sure all SSE2 stores are visible thereafter */
- __asm__ __volatile__ ( "sfence" );
}
else
{
p_line2 += i_dest_margin;
}
}
+ /* make sure all SSE2 stores are visible thereafter */
+ SSE2_END;
#endif // defined(MODULE_NAME_IS_i420_yuy2_sse2)
}
#if defined (MODULE_NAME_IS_i420_yuy2_mmx)
/* re-enable FPU registers */
- __asm__ __volatile__ ( "emms" );
+ MMX_END;
#endif
#else // defined(MODULE_NAME_IS_i420_yuy2_sse2)
p_line1 += i_dest_margin;
p_line2 += i_dest_margin;
}
- /* make sure all SSE2 stores are visible thereafter */
- __asm__ __volatile__ ( "sfence" );
}
else
{
p_line2 += i_dest_margin;
}
}
+ /* make sure all SSE2 stores are visible thereafter */
+ SSE2_END;
#endif // defined(MODULE_NAME_IS_i420_yuy2_sse2)
}
#endif // !defined (MODULE_NAME_IS_i420_yuy2_altivec)