X-Git-Url: https://git.sesse.net/?a=blobdiff_plain;f=m68kfpu.c;fp=m68kfpu.c;h=43210fedce8ae1c586052bd62671aa7bb051a85d;hb=6d74804193233a5fe5c57a2eb776219e6e1a31c1;hp=68c3f6f1614702554c5ea3ba240faa20d6517581;hpb=14636790c638a4c24fd31054b35228a9138e98a9;p=pistorm diff --git a/m68kfpu.c b/m68kfpu.c index 68c3f6f..43210fe 100644 --- a/m68kfpu.c +++ b/m68kfpu.c @@ -4,6 +4,7 @@ #include #include "softfloat/softfloat.h" + float_status status; extern void exit(int); @@ -380,7 +381,7 @@ static inline int TEST_CONDITION(int condition) return r; } -static uint8 READ_EA_8(int ea) +static uint8 READ_EA_8(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -422,13 +423,13 @@ static uint8 READ_EA_8(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_8(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_8(ea); } @@ -439,12 +440,12 @@ static uint8 READ_EA_8(int ea) } case 3: // (PC) + (Xn) + d8 { - uint32 ea = EA_PCIX_8(); + uint32 ea = EA_PCIX_8(); return m68ki_read_8(ea); } case 4: // # { - return OPER_I_8(); + return OPER_I_8(state); } default: fatalerror("M68kFPU: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -456,7 +457,7 @@ static uint8 READ_EA_8(int ea) return 0; } -static uint16 READ_EA_16(int ea) +static uint16 READ_EA_16(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -498,13 +499,13 @@ static uint16 READ_EA_16(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_16(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_16(ea); } @@ -520,7 +521,7 @@ static uint16 READ_EA_16(int ea) } case 4: // # { - return OPER_I_16(); + return OPER_I_16(state); } default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -533,7 +534,7 @@ static uint16 READ_EA_16(int ea) return 0; } -static uint32 READ_EA_32(int ea) +static uint32 READ_EA_32(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -575,13 +576,13 @@ static uint32 READ_EA_32(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_32(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_32(ea); } @@ -597,7 +598,7 @@ static uint32 READ_EA_32(int ea) } case 4: // # { - return OPER_I_32(); + return OPER_I_32(state); } default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -608,7 +609,7 @@ static uint32 READ_EA_32(int ea) return 0; } -static uint64 READ_EA_64(int ea) +static uint64 READ_EA_64(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -659,8 +660,8 @@ static uint64 READ_EA_64(int ea) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return (uint64)(m68ki_read_32(ea)) << 32 | (uint64)(m68ki_read_32(ea+4)); } @@ -673,8 +674,8 @@ static uint64 READ_EA_64(int ea) } case 4: // # { - h1 = OPER_I_32(); - h2 = OPER_I_32(); + h1 = OPER_I_32(state); + h2 = OPER_I_32(state); return (uint64)(h1) << 32 | (uint64)(h2); } case 2: // (d16, PC) @@ -695,7 +696,7 @@ static uint64 READ_EA_64(int ea) } -static floatx80 READ_EA_FPE(uint32 ea) +static floatx80 READ_EA_FPE(m68ki_cpu_core *state, uint32 ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -745,8 +746,8 @@ static floatx80 READ_EA_FPE(uint32 ea) { case 1: // (xxx) { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; fpr = load_extended_float80(ea); } @@ -787,7 +788,7 @@ static floatx80 READ_EA_FPE(uint32 ea) return fpr; } -static floatx80 READ_EA_PACK(int ea) +static floatx80 READ_EA_PACK(m68ki_cpu_core *state, int ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -834,7 +835,7 @@ static floatx80 READ_EA_PACK(int ea) return fpr; } -static void WRITE_EA_8(int ea, uint8 data) +static void WRITE_EA_8(m68ki_cpu_core *state, int ea, uint8 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -882,8 +883,8 @@ static void WRITE_EA_8(int ea, uint8 data) { case 1: // (xxx).B { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_8(ea, data); break; @@ -902,7 +903,7 @@ static void WRITE_EA_8(int ea, uint8 data) } } -static void WRITE_EA_16(int ea, uint16 data) +static void WRITE_EA_16(m68ki_cpu_core *state, int ea, uint16 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -950,8 +951,8 @@ static void WRITE_EA_16(int ea, uint16 data) { case 1: // (xxx).W { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_16(ea, data); break; @@ -970,7 +971,7 @@ static void WRITE_EA_16(int ea, uint16 data) } } -static void WRITE_EA_32(int ea, uint32 data) +static void WRITE_EA_32(m68ki_cpu_core *state, int ea, uint32 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1023,14 +1024,14 @@ static void WRITE_EA_32(int ea, uint32 data) { case 0: // (xxx).W { - uint32 ea = OPER_I_16(); + uint32 ea = OPER_I_16(state); m68ki_write_32(ea, data); break; } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_32(ea, data); break; @@ -1049,7 +1050,7 @@ static void WRITE_EA_32(int ea, uint32 data) } } -static void WRITE_EA_64(int ea, uint64 data) +static void WRITE_EA_64(m68ki_cpu_core *state, int ea, uint64 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1100,8 +1101,8 @@ static void WRITE_EA_64(int ea, uint64 data) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_32(ea+0, (uint32)(data >> 32)); m68ki_write_32(ea+4, (uint32)(data)); @@ -1122,7 +1123,7 @@ static void WRITE_EA_64(int ea, uint64 data) } } -static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) +static void WRITE_EA_FPE(m68ki_cpu_core *state, uint32 ea, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1173,7 +1174,7 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) } } -static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) +static void WRITE_EA_PACK(m68ki_cpu_core *state, int ea, int k, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1219,7 +1220,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) } -static void fpgen_rm_reg(uint16 w2) +static void fpgen_rm_reg(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int rm = (w2 >> 14) & 0x1; @@ -1236,42 +1237,42 @@ static void fpgen_rm_reg(uint16 w2) { case 0: // Long-Word Integer { - sint32 d = READ_EA_32(ea); + sint32 d = READ_EA_32(state, ea); source = int32_to_floatx80(d); break; } case 1: // Single-precision Real { - uint32 d = READ_EA_32(ea); + uint32 d = READ_EA_32(state, ea); source = float32_to_floatx80(d, &status); break; } case 2: // Extended-precision Real { - source = READ_EA_FPE(ea); + source = READ_EA_FPE(state, ea); break; } case 3: // Packed-decimal Real { - source = READ_EA_PACK(ea); + source = READ_EA_PACK(state, ea); break; } case 4: // Word Integer { - sint16 d = READ_EA_16(ea); + sint16 d = READ_EA_16(state, ea); source = int32_to_floatx80((sint32)d); break; } case 5: // Double-precision Real { - uint64 d = READ_EA_64(ea); + uint64 d = READ_EA_64(state, ea); source = float64_to_floatx80(d, &status); break; } case 6: // Byte Integer { - sint8 d = READ_EA_8(ea); + sint8 d = READ_EA_8(state, ea); source = int32_to_floatx80((sint32)d); break; } @@ -1743,7 +1744,7 @@ static void fpgen_rm_reg(uint16 w2) } } -static void fmove_reg_mem(uint16 w2) +static void fmove_reg_mem(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int src = (w2 >> 7) & 0x7; @@ -1755,25 +1756,25 @@ static void fmove_reg_mem(uint16 w2) case 0: // Long-Word Integer { sint32 d = (sint32)floatx80_to_int32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 1: // Single-precision Real { uint32 d = floatx80_to_float32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 2: // Extended-precision Real { - WRITE_EA_FPE(ea, REG_FP[src]); + WRITE_EA_FPE(state, ea, REG_FP[src]); break; } case 3: // Packed-decimal Real with Static K-factor { // sign-extend k k = (k & 0x40) ? (k | 0xffffff80) : (k & 0x7f); - WRITE_EA_PACK(ea, k, REG_FP[src]); + WRITE_EA_PACK(state, ea, k, REG_FP[src]); break; } case 4: // Word Integer @@ -1783,7 +1784,7 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_16(ea, (sint16)value); + WRITE_EA_16(state, ea, (sint16) value); break; } case 5: // Double-precision Real @@ -1792,7 +1793,7 @@ static void fmove_reg_mem(uint16 w2) d = floatx80_to_float64(REG_FP[src], &status); - WRITE_EA_64(ea, d); + WRITE_EA_64(state, ea, d); break; } case 6: // Byte Integer @@ -1802,12 +1803,12 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_8(ea, (sint8)value); + WRITE_EA_8(state, ea, (sint8) value); break; } case 7: // Packed-decimal Real with Dynamic K-factor { - WRITE_EA_PACK(ea, REG_D[k>>4], REG_FP[src]); + WRITE_EA_PACK(state, ea, REG_D[k >> 4], REG_FP[src]); break; } } @@ -1815,7 +1816,7 @@ static void fmove_reg_mem(uint16 w2) USE_CYCLES(12); } -static void fmove_fpcr(uint16 w2) +static void fmove_fpcr(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int dir = (w2 >> 13) & 0x1; @@ -1852,15 +1853,15 @@ static void fmove_fpcr(uint16 w2) { if (dir) // From system control reg to { - if (regsel & 4) WRITE_EA_32(ea, REG_FPCR); - if (regsel & 2) WRITE_EA_32(ea, REG_FPSR); - if (regsel & 1) WRITE_EA_32(ea, REG_FPIAR); + if (regsel & 4) WRITE_EA_32(state, ea, REG_FPCR); + if (regsel & 2) WRITE_EA_32(state, ea, REG_FPSR); + if (regsel & 1) WRITE_EA_32(state, ea, REG_FPIAR); } else // From to system control reg { - if (regsel & 4) REG_FPCR = READ_EA_32(ea); - if (regsel & 2) REG_FPSR = READ_EA_32(ea); - if (regsel & 1) REG_FPIAR = READ_EA_32(ea); + if (regsel & 4) REG_FPCR = READ_EA_32(state, ea); + if (regsel & 2) REG_FPSR = READ_EA_32(state, ea); + if (regsel & 1) REG_FPIAR = READ_EA_32(state, ea); } } @@ -1915,7 +1916,7 @@ static void fmove_fpcr(uint16 w2) USE_CYCLES(10); } -static void fmovem(uint16 w2) +static void fmovem(m68ki_cpu_core *state, uint16 w2) { int i; int ea = REG_IR & 0x3f; @@ -1957,7 +1958,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[i]); + WRITE_EA_FPE(state, ea, REG_FP[i]); break; } @@ -1981,7 +1982,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[7-i]); + WRITE_EA_FPE(state, ea, REG_FP[7 - i]); break; } @@ -2017,7 +2018,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - REG_FP[7-i] = READ_EA_FPE(ea); + REG_FP[7-i] = READ_EA_FPE(state, ea); break; } USE_CYCLES(2); @@ -2031,20 +2032,20 @@ static void fmovem(uint16 w2) } } -static void fscc() +static void fscc(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; - int condition = (sint16)(OPER_I_16()); + int condition = (sint16)(OPER_I_16(state)); - WRITE_EA_8(ea, TEST_CONDITION(condition) ? 0xff : 0); + WRITE_EA_8(state, ea, TEST_CONDITION(condition) ? 0xff : 0); USE_CYCLES(7); // ??? } -static void fbcc16(void) +static void fbcc16(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = (sint16)(OPER_I_16()); + offset = (sint16)(OPER_I_16(state)); // TODO: condition and jump!!! if (TEST_CONDITION(condition)) @@ -2056,12 +2057,12 @@ static void fbcc16(void) USE_CYCLES(7); } -static void fbcc32(void) +static void fbcc32(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = OPER_I_32(); + offset = OPER_I_32(state); // TODO: condition and jump!!! if (TEST_CONDITION(condition)) @@ -2074,7 +2075,7 @@ static void fbcc32(void) } -void m68040_fpu_op0() +void m68040_fpu_op0(m68ki_cpu_core *state) { m68ki_cpu.fpu_just_reset = 0; @@ -2082,33 +2083,33 @@ void m68040_fpu_op0() { case 0: { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); switch ((w2 >> 13) & 0x7) { case 0x0: // FPU ALU FP, FP case 0x2: // FPU ALU ea, FP { - fpgen_rm_reg(w2); + fpgen_rm_reg(state, w2); break; } case 0x3: // FMOVE FP, ea { - fmove_reg_mem(w2); + fmove_reg_mem(state, w2); break; } case 0x4: // FMOVEM ea, FPCR case 0x5: // FMOVEM FPCR, ea { - fmove_fpcr(w2); + fmove_fpcr(state, w2); break; } case 0x6: // FMOVEM ea, list case 0x7: // FMOVEM list, ea { - fmovem(w2); + fmovem(state, w2); break; } @@ -2125,7 +2126,7 @@ void m68040_fpu_op0() printf("M68kFPU: unimplemented FDBcc main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); break; default: // FScc (?) - fscc(); + fscc(state); return; } fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); @@ -2133,12 +2134,12 @@ void m68040_fpu_op0() } case 2: // FBcc disp16 { - fbcc16(); + fbcc16(state); break; } case 3: // FBcc disp32 { - fbcc32(); + fbcc32(state); break; } @@ -2146,7 +2147,7 @@ void m68040_fpu_op0() } } -static int perform_fsave(uint32 addr, int inc) +static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc) { if(m68ki_cpu.cpu_type & CPU_TYPE_040) { @@ -2188,7 +2189,7 @@ static int perform_fsave(uint32 addr, int inc) } // FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0 -static void do_frestore_null(void) +static void do_frestore_null(m68ki_cpu_core *state) { int i; @@ -2206,7 +2207,7 @@ static void do_frestore_null(void) m68ki_cpu.fpu_just_reset = 1; } -void m68040_do_fsave(uint32 addr, int reg, int inc) +void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc) { if (m68ki_cpu.fpu_just_reset) { @@ -2215,13 +2216,13 @@ void m68040_do_fsave(uint32 addr, int reg, int inc) else { // we normally generate an IDLE frame - int delta = perform_fsave(addr, inc); + int delta = perform_fsave(state, addr, inc); if(reg != -1) REG_A[reg] += delta; } } -void m68040_do_frestore(uint32 addr, int reg) +void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg) { uint32 temp = m68ki_read_32(addr); // check for nullptr frame @@ -2254,11 +2255,11 @@ void m68040_do_frestore(uint32 addr, int reg) } else { - do_frestore_null(); + do_frestore_null(state); } } -void m68040_fpu_op1() +void m68040_fpu_op1(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; int mode = (ea >> 3) & 0x7; @@ -2273,27 +2274,27 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 3: // (An)+ addr = EA_AY_PI_32(); printf("FSAVE mode %d, reg A%d=0x%08x\n",mode,reg,REG_A[reg]); - m68040_do_fsave(addr, -1, 1); // FIXME: -1 was reg + m68040_do_fsave(state, addr, -1, 1); // FIXME: -1 was reg break; case 4: // -(An) addr = EA_AY_PD_32(); - m68040_do_fsave(addr, reg, 0); // FIXME: -1 was reg + m68040_do_fsave(state, addr, reg, 0); // FIXME: -1 was reg break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 7: // @@ -2303,13 +2304,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } default: @@ -2330,22 +2331,22 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 3: // (An)+ addr = EA_AY_PI_32(); - m68040_do_frestore(addr, reg); + m68040_do_frestore(state, addr, reg); break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 7: // @@ -2355,13 +2356,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } default: @@ -2380,9 +2381,9 @@ void m68040_fpu_op1() } } -void m68881_ftrap() +void m68881_ftrap(m68ki_cpu_core *state) { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); // now check the condition if (TEST_CONDITION(w2 & 0x3f)) @@ -2395,11 +2396,11 @@ void m68881_ftrap() switch (REG_IR & 0x7) { case 2: // word operand - OPER_I_16(); + OPER_I_16(state); break; case 3: // long word operand - OPER_I_32(); + OPER_I_32(state); break; case 4: // no operand