X-Git-Url: https://git.sesse.net/?a=blobdiff_plain;f=tbb%2Finclude%2Ftbb%2Fmachine%2Flinux_intel64.h;h=353ba09fa5bc1e9039ec28fdc579d56f5bbb2468;hb=4c96b4064a92f65beead3cb2453d727187bed40f;hp=8d0576256b392e2e558ed0b54c49671b97941678;hpb=46ab0514ba58ee00183ff0584c7ea7c9e3d76494;p=casparcg

diff --git a/tbb/include/tbb/machine/linux_intel64.h b/tbb/include/tbb/machine/linux_intel64.h
index 8d0576256..353ba09fa 100644
--- a/tbb/include/tbb/machine/linux_intel64.h
+++ b/tbb/include/tbb/machine/linux_intel64.h
@@ -26,24 +26,28 @@
     the GNU General Public License.
 */
 
-#ifndef __TBB_machine_H
+#if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_intel64_H)
 #error Do not include this file directly; include tbb_machine.h instead
 #endif
 
+#define __TBB_machine_linux_intel64_H
+
 #include <stdint.h>
 #include <unistd.h>
 
 #define __TBB_WORDSIZE 8
 #define __TBB_BIG_ENDIAN 0
 
-#define __TBB_release_consistency_helper() __asm__ __volatile__("": : :"memory")
+#define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
+#define __TBB_control_consistency_helper() __TBB_compiler_fence()
+#define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
+#define __TBB_release_consistency_helper() __TBB_compiler_fence()
 
-// __TBB_full_memory_fence can be predefined
 #ifndef __TBB_full_memory_fence
 #define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
 #endif
 
-#define __MACHINE_DECL_ATOMICS(S,T,X) \
+#define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X)                                          \
 static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand )  \
 {                                                                                    \
     T result;                                                                        \
@@ -75,10 +79,12 @@ static inline  T __TBB_machine_fetchstore##S(volatile void *ptr, T value)
     return result;                                                                   \
 }                                                                                    \
                                                                                      
-__MACHINE_DECL_ATOMICS(1,int8_t,"")
-__MACHINE_DECL_ATOMICS(2,int16_t,"")
-__MACHINE_DECL_ATOMICS(4,int32_t,"")
-__MACHINE_DECL_ATOMICS(8,int64_t,"q")
+__TBB_MACHINE_DEFINE_ATOMICS(1,int8_t,"")
+__TBB_MACHINE_DEFINE_ATOMICS(2,int16_t,"")
+__TBB_MACHINE_DEFINE_ATOMICS(4,int32_t,"")
+__TBB_MACHINE_DEFINE_ATOMICS(8,int64_t,"q")
+
+#undef __TBB_MACHINE_DEFINE_ATOMICS
 
 static inline int64_t __TBB_machine_lg( uint64_t x ) {
     int64_t j;
@@ -94,29 +100,6 @@ static inline void __TBB_machine_and( volatile void *ptr, uint64_t addend ) {
     __asm__ __volatile__("lock\nandq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(addend), "m"(*(volatile uint64_t*)ptr) : "memory");
 }
 
-// Machine specific atomic operations
-
-#define __TBB_CompareAndSwap1(P,V,C) __TBB_machine_cmpswp1(P,V,C)
-#define __TBB_CompareAndSwap2(P,V,C) __TBB_machine_cmpswp2(P,V,C)
-#define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
-#define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
-#define __TBB_CompareAndSwapW(P,V,C) __TBB_machine_cmpswp8(P,V,C)
-
-#define __TBB_FetchAndAdd1(P,V) __TBB_machine_fetchadd1(P,V)
-#define __TBB_FetchAndAdd2(P,V) __TBB_machine_fetchadd2(P,V)
-#define __TBB_FetchAndAdd4(P,V) __TBB_machine_fetchadd4(P,V)
-#define __TBB_FetchAndAdd8(P,V)  __TBB_machine_fetchadd8(P,V)
-#define __TBB_FetchAndAddW(P,V)  __TBB_machine_fetchadd8(P,V)
-
-#define __TBB_FetchAndStore1(P,V) __TBB_machine_fetchstore1(P,V)
-#define __TBB_FetchAndStore2(P,V) __TBB_machine_fetchstore2(P,V)
-#define __TBB_FetchAndStore4(P,V) __TBB_machine_fetchstore4(P,V)
-#define __TBB_FetchAndStore8(P,V)  __TBB_machine_fetchstore8(P,V)
-#define __TBB_FetchAndStoreW(P,V)  __TBB_machine_fetchstore8(P,V)
-
-#undef __TBB_Store8
-#undef __TBB_Load8
-
 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
 
@@ -129,17 +112,13 @@ static inline void __TBB_machine_pause( int32_t delay ) {
     return;
 }
 #define __TBB_Pause(V) __TBB_machine_pause(V)
-#endif
-#define __TBB_Log2(V)    __TBB_machine_lg(V)
+#endif /* !__TBB_Pause */
 
-// Special atomic functions
-#define __TBB_FetchAndAddWrelease(P,V) __TBB_FetchAndAddW(P,V)
-#define __TBB_FetchAndIncrementWacquire(P) __TBB_FetchAndAddW(P,1)
-#define __TBB_FetchAndDecrementWrelease(P) __TBB_FetchAndAddW(P,-1)
+#define __TBB_Log2(V)  __TBB_machine_lg(V)
 
-// Use generic definitions from tbb_machine.h
-#undef __TBB_TryLockByte
-#undef __TBB_LockByte
+#define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE   1
+#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE    1
+#define __TBB_USE_GENERIC_RELAXED_LOAD_STORE        1
 
 // API to retrieve/update FPU control setting
 #ifndef __TBB_CPU_CTL_ENV_PRESENT
@@ -151,11 +130,21 @@ struct __TBB_cpu_ctl_env_t {
 };
 
 inline void __TBB_get_cpu_ctl_env ( __TBB_cpu_ctl_env_t* ctl ) {
+#if __TBB_ICC_12_0_INL_ASM_FSTCW_BROKEN
+    __TBB_cpu_ctl_env_t loc_ctl;
+    __asm__ __volatile__ (
+            "stmxcsr %0\n\t"
+            "fstcw %1"
+            : "=m"(loc_ctl.mxcsr), "=m"(loc_ctl.x87cw)
+    );
+    *ctl = loc_ctl;
+#else
     __asm__ __volatile__ (
             "stmxcsr %0\n\t"
             "fstcw %1"
             : "=m"(ctl->mxcsr), "=m"(ctl->x87cw)
     );
+#endif
 }
 inline void __TBB_set_cpu_ctl_env ( const __TBB_cpu_ctl_env_t* ctl ) {
     __asm__ __volatile__ (
@@ -164,4 +153,4 @@ inline void __TBB_set_cpu_ctl_env ( const __TBB_cpu_ctl_env_t* ctl ) {
             : : "m"(ctl->mxcsr), "m"(ctl->x87cw)
     );
 }
-#endif
+#endif /* !__TBB_CPU_CTL_ENV_PRESENT */