From: Rune Holm Date: Sun, 20 Jun 2021 17:47:22 +0000 (+0200) Subject: introducing CPU state paramter 2 X-Git-Url: https://git.sesse.net/?a=commitdiff_plain;h=6d74804193233a5fe5c57a2eb776219e6e1a31c1;p=pistorm introducing CPU state paramter 2 --- diff --git a/m68k_in.c b/m68k_in.c index 9b400a0..7c36327 100644 --- a/m68k_in.c +++ b/m68k_in.c @@ -283,10 +283,10 @@ M68KMAKE_OPCODE_HANDLER_HEADER #include #include "m68kcpu.h" -extern void m68040_fpu_op0(void); -extern void m68040_fpu_op1(void); -extern void m68851_mmu_ops(); -extern void m68881_ftrap(); +extern void m68040_fpu_op0(m68ki_cpu_core *state); +extern void m68040_fpu_op1(m68ki_cpu_core *state); +extern void m68851_mmu_ops(m68ki_cpu_core *state); +extern void m68881_ftrap(m68ki_cpu_core *state); /* ======================================================================== */ /* ========================= INSTRUCTION HANDLERS ========================= */ @@ -923,7 +923,7 @@ M68KMAKE_OP(040fpu0, 32, ., .) // printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU); if(HAS_FPU) { - m68040_fpu_op0(); + void m68040_fpu_op0(m68ki_cpu_core *state); return; } m68ki_exception_1111(); @@ -935,7 +935,7 @@ M68KMAKE_OP(040fpu1, 32, ., .) // printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU); if(HAS_FPU) { - m68040_fpu_op1(); + void m68040_fpu_op1(m68ki_cpu_core *state); return; } m68ki_exception_1111(); @@ -972,7 +972,7 @@ M68KMAKE_OP(abcd, 8, rr, .) M68KMAKE_OP(abcd, 8, mm, ax7) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); @@ -999,7 +999,7 @@ M68KMAKE_OP(abcd, 8, mm, ax7) M68KMAKE_OP(abcd, 8, mm, ay7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); @@ -1026,7 +1026,7 @@ M68KMAKE_OP(abcd, 8, mm, ay7) M68KMAKE_OP(abcd, 8, mm, axy7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); @@ -1053,7 +1053,7 @@ M68KMAKE_OP(abcd, 8, mm, axy7) M68KMAKE_OP(abcd, 8, mm, .) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); @@ -1307,7 +1307,7 @@ M68KMAKE_OP(adda, 32, ., .) M68KMAKE_OP(addi, 8, ., d) { uint* r_dst = &DY; - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint dst = MASK_OUT_ABOVE_8(*r_dst); uint res = src + dst; @@ -1322,7 +1322,7 @@ M68KMAKE_OP(addi, 8, ., d) M68KMAKE_OP(addi, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint ea = M68KMAKE_GET_EA_AY_8; uint dst = m68ki_read_8(ea); uint res = src + dst; @@ -1339,7 +1339,7 @@ M68KMAKE_OP(addi, 8, ., .) M68KMAKE_OP(addi, 16, ., d) { uint* r_dst = &DY; - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint dst = MASK_OUT_ABOVE_16(*r_dst); uint res = src + dst; @@ -1354,7 +1354,7 @@ M68KMAKE_OP(addi, 16, ., d) M68KMAKE_OP(addi, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint dst = m68ki_read_16(ea); uint res = src + dst; @@ -1371,7 +1371,7 @@ M68KMAKE_OP(addi, 16, ., .) M68KMAKE_OP(addi, 32, ., d) { uint* r_dst = &DY; - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint dst = *r_dst; uint res = src + dst; @@ -1386,7 +1386,7 @@ M68KMAKE_OP(addi, 32, ., d) M68KMAKE_OP(addi, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint ea = M68KMAKE_GET_EA_AY_32; uint dst = m68ki_read_32(ea); uint res = src + dst; @@ -1569,7 +1569,7 @@ M68KMAKE_OP(addx, 32, rr, .) M68KMAKE_OP(addx, 8, mm, ax7) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1587,7 +1587,7 @@ M68KMAKE_OP(addx, 8, mm, ax7) M68KMAKE_OP(addx, 8, mm, ay7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1605,7 +1605,7 @@ M68KMAKE_OP(addx, 8, mm, ay7) M68KMAKE_OP(addx, 8, mm, axy7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1623,7 +1623,7 @@ M68KMAKE_OP(addx, 8, mm, axy7) M68KMAKE_OP(addx, 8, mm, .) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1641,7 +1641,7 @@ M68KMAKE_OP(addx, 8, mm, .) M68KMAKE_OP(addx, 16, mm, .) { - uint src = OPER_AY_PD_16(); + uint src = OPER_AY_PD_16(state); uint ea = EA_AX_PD_16(); uint dst = m68ki_read_16(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1659,7 +1659,7 @@ M68KMAKE_OP(addx, 16, mm, .) M68KMAKE_OP(addx, 32, mm, .) { - uint src = OPER_AY_PD_32(); + uint src = OPER_AY_PD_32(state); uint ea = EA_AX_PD_32(); uint dst = m68ki_read_32(ea); uint res = src + dst + XFLAG_AS_1(); @@ -1779,7 +1779,7 @@ M68KMAKE_OP(and, 32, re, .) M68KMAKE_OP(andi, 8, ., d) { - FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); + FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(state) | 0xffffff00)); FLAG_N = NFLAG_8(FLAG_Z); FLAG_C = CFLAG_CLEAR; @@ -1789,7 +1789,7 @@ M68KMAKE_OP(andi, 8, ., d) M68KMAKE_OP(andi, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint ea = M68KMAKE_GET_EA_AY_8; uint res = src & m68ki_read_8(ea); @@ -1804,7 +1804,7 @@ M68KMAKE_OP(andi, 8, ., .) M68KMAKE_OP(andi, 16, ., d) { - FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); + FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(state) | 0xffff0000)); FLAG_N = NFLAG_16(FLAG_Z); FLAG_C = CFLAG_CLEAR; @@ -1814,7 +1814,7 @@ M68KMAKE_OP(andi, 16, ., d) M68KMAKE_OP(andi, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint res = src & m68ki_read_16(ea); @@ -1829,7 +1829,7 @@ M68KMAKE_OP(andi, 16, ., .) M68KMAKE_OP(andi, 32, ., d) { - FLAG_Z = DY &= (OPER_I_32()); + FLAG_Z = DY &= (OPER_I_32(state)); FLAG_N = NFLAG_32(FLAG_Z); FLAG_C = CFLAG_CLEAR; @@ -1839,7 +1839,7 @@ M68KMAKE_OP(andi, 32, ., d) M68KMAKE_OP(andi, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint ea = M68KMAKE_GET_EA_AY_32; uint res = src & m68ki_read_32(ea); @@ -1854,7 +1854,7 @@ M68KMAKE_OP(andi, 32, ., .) M68KMAKE_OP(andi, 16, toc, .) { - m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8()); + m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8(state)); } @@ -1862,9 +1862,9 @@ M68KMAKE_OP(andi, 16, tos, .) { if(FLAG_S) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() & src); + m68ki_set_sr(state, m68ki_get_sr() & src); return; } m68ki_exception_privilege_violation(); @@ -2314,7 +2314,7 @@ M68KMAKE_OP(bcc, 16, ., .) { if(M68KMAKE_CC) { - uint offset = OPER_I_16(); + uint offset = OPER_I_16(state); REG_PC -= 2; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_16(offset); @@ -2331,7 +2331,7 @@ M68KMAKE_OP(bcc, 32, ., .) { if(M68KMAKE_CC) { - uint offset = OPER_I_32(); + uint offset = OPER_I_32(state); REG_PC -= 4; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_32(offset); @@ -2377,7 +2377,7 @@ M68KMAKE_OP(bchg, 8, r, .) M68KMAKE_OP(bchg, 32, s, d) { uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); + uint mask = 1 << (OPER_I_8(state) & 0x1f); FLAG_Z = *r_dst & mask; *r_dst ^= mask; @@ -2386,7 +2386,7 @@ M68KMAKE_OP(bchg, 32, s, d) M68KMAKE_OP(bchg, 8, s, .) { - uint mask = 1 << (OPER_I_8() & 7); + uint mask = 1 << (OPER_I_8(state) & 7); uint ea = M68KMAKE_GET_EA_AY_8; uint src = m68ki_read_8(ea); @@ -2419,7 +2419,7 @@ M68KMAKE_OP(bclr, 8, r, .) M68KMAKE_OP(bclr, 32, s, d) { uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); + uint mask = 1 << (OPER_I_8(state) & 0x1f); FLAG_Z = *r_dst & mask; *r_dst &= ~mask; @@ -2428,7 +2428,7 @@ M68KMAKE_OP(bclr, 32, s, d) M68KMAKE_OP(bclr, 8, s, .) { - uint mask = 1 << (OPER_I_8() & 7); + uint mask = 1 << (OPER_I_8(state) & 7); uint ea = M68KMAKE_GET_EA_AY_8; uint src = m68ki_read_8(ea); @@ -2441,7 +2441,7 @@ M68KMAKE_OP(bfchg, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint* data = &DY; @@ -2476,7 +2476,7 @@ M68KMAKE_OP(bfchg, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint mask_base; @@ -2530,7 +2530,7 @@ M68KMAKE_OP(bfclr, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint* data = &DY; @@ -2567,7 +2567,7 @@ M68KMAKE_OP(bfclr, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint mask_base; @@ -2621,7 +2621,7 @@ M68KMAKE_OP(bfexts, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint64 data = DY; @@ -2655,7 +2655,7 @@ M68KMAKE_OP(bfexts, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint data; @@ -2706,7 +2706,7 @@ M68KMAKE_OP(bfextu, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint64 data = DY; @@ -2740,7 +2740,7 @@ M68KMAKE_OP(bfextu, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint data; @@ -2790,7 +2790,7 @@ M68KMAKE_OP(bfffo, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint64 data = DY; @@ -2828,7 +2828,7 @@ M68KMAKE_OP(bfffo, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; sint local_offset; uint width = word2; @@ -2880,7 +2880,7 @@ M68KMAKE_OP(bfins, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint* data = &DY; @@ -2922,7 +2922,7 @@ M68KMAKE_OP(bfins, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint insert_base = REG_D[(word2>>12)&7]; @@ -2992,7 +2992,7 @@ M68KMAKE_OP(bfset, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint* data = &DY; @@ -3029,7 +3029,7 @@ M68KMAKE_OP(bfset, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint mask_base; @@ -3084,7 +3084,7 @@ M68KMAKE_OP(bftst, 32, ., d) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint offset = (word2>>6)&31; uint width = word2; uint* data = &DY; @@ -3119,7 +3119,7 @@ M68KMAKE_OP(bftst, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint offset = (word2>>6)&31; uint width = word2; uint mask_base; @@ -3189,7 +3189,7 @@ M68KMAKE_OP(bra, 8, ., .) M68KMAKE_OP(bra, 16, ., .) { - uint offset = OPER_I_16(); + uint offset = OPER_I_16(state); REG_PC -= 2; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_16(offset); @@ -3203,7 +3203,7 @@ M68KMAKE_OP(bra, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint offset = OPER_I_32(); + uint offset = OPER_I_32(state); REG_PC -= 4; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_32(offset); @@ -3248,7 +3248,7 @@ M68KMAKE_OP(bset, 8, r, .) M68KMAKE_OP(bset, 32, s, d) { uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); + uint mask = 1 << (OPER_I_8(state) & 0x1f); FLAG_Z = *r_dst & mask; *r_dst |= mask; @@ -3257,7 +3257,7 @@ M68KMAKE_OP(bset, 32, s, d) M68KMAKE_OP(bset, 8, s, .) { - uint mask = 1 << (OPER_I_8() & 7); + uint mask = 1 << (OPER_I_8(state) & 7); uint ea = M68KMAKE_GET_EA_AY_8; uint src = m68ki_read_8(ea); @@ -3276,7 +3276,7 @@ M68KMAKE_OP(bsr, 8, ., .) M68KMAKE_OP(bsr, 16, ., .) { - uint offset = OPER_I_16(); + uint offset = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_push_32(REG_PC); REG_PC -= 2; @@ -3288,7 +3288,7 @@ M68KMAKE_OP(bsr, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint offset = OPER_I_32(); + uint offset = OPER_I_32(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_push_32(REG_PC); REG_PC -= 4; @@ -3320,13 +3320,13 @@ M68KMAKE_OP(btst, 8, r, .) M68KMAKE_OP(btst, 32, s, d) { - FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); + FLAG_Z = DY & (1 << (OPER_I_8(state) & 0x1f)); } M68KMAKE_OP(btst, 8, s, .) { - uint bit = OPER_I_8() & 7; + uint bit = OPER_I_8(state) & 7; FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit); } @@ -3355,7 +3355,7 @@ M68KMAKE_OP(cas, 8, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_8; uint dest = m68ki_read_8(ea); uint* compare = ®_D[word2 & 7]; @@ -3384,7 +3384,7 @@ M68KMAKE_OP(cas, 16, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint dest = m68ki_read_16(ea); uint* compare = ®_D[word2 & 7]; @@ -3413,7 +3413,7 @@ M68KMAKE_OP(cas, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_32; uint dest = m68ki_read_32(ea); uint* compare = ®_D[word2 & 7]; @@ -3442,7 +3442,7 @@ M68KMAKE_OP(cas2, 16, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_32(); + uint word2 = OPER_I_32(state); uint* compare1 = ®_D[(word2 >> 16) & 7]; uint ea1 = REG_DA[(word2 >> 28) & 15]; uint dest1 = m68ki_read_16(ea1); @@ -3487,7 +3487,7 @@ M68KMAKE_OP(cas2, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_32(); + uint word2 = OPER_I_32(state); uint* compare1 = ®_D[(word2 >> 16) & 7]; uint ea1 = REG_DA[(word2 >> 28) & 15]; uint dest1 = m68ki_read_32(ea1); @@ -3614,7 +3614,7 @@ M68KMAKE_OP(chk2cmp2, 8, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xff; @@ -3640,7 +3640,7 @@ M68KMAKE_OP(chk2cmp2, 8, ., pcdi) return; } - + m68ki_exception_illegal(); } @@ -3649,7 +3649,7 @@ M68KMAKE_OP(chk2cmp2, 8, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xff; @@ -3682,7 +3682,7 @@ M68KMAKE_OP(chk2cmp2, 8, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xff; @@ -3715,7 +3715,7 @@ M68KMAKE_OP(chk2cmp2, 16, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xffff; @@ -3748,7 +3748,7 @@ M68KMAKE_OP(chk2cmp2, 16, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xffff; @@ -3781,7 +3781,7 @@ M68KMAKE_OP(chk2cmp2, 16, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); sint compare = REG_DA[(word2 >> 12) & 15]; if(!BIT_F(word2)) compare &= 0xffff; @@ -3814,7 +3814,7 @@ M68KMAKE_OP(chk2cmp2, 32, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint32 word2 = OPER_I_16(); + uint32 word2 = OPER_I_16(state); sint64 compare = REG_DA[(word2 >> 12) & 15]; uint32 ea = EA_PCDI_32(); sint64 lower_bound = m68ki_read_pcrel_32(ea); @@ -3842,7 +3842,7 @@ M68KMAKE_OP(chk2cmp2, 32, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint32 word2 = OPER_I_16(); + uint32 word2 = OPER_I_16(state); sint64 compare = REG_DA[(word2 >> 12) & 15]; uint32 ea = EA_PCIX_32(); sint64 lower_bound = m68ki_read_32(ea); @@ -3869,8 +3869,8 @@ M68KMAKE_OP(chk2cmp2, 32, ., pcix) M68KMAKE_OP(chk2cmp2, 32, ., .) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint32 word2 = OPER_I_16(); + { + uint32 word2 = OPER_I_16(state); sint64 compare = REG_DA[(word2 >> 12) & 15]; uint32 ea = M68KMAKE_GET_EA_AY_32; sint64 lower_bound = m68ki_read_32(ea); @@ -4156,7 +4156,7 @@ M68KMAKE_OP(cmpa, 32, ., .) M68KMAKE_OP(cmpi, 8, ., d) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint dst = MASK_OUT_ABOVE_8(DY); uint res = dst - src; @@ -4169,7 +4169,7 @@ M68KMAKE_OP(cmpi, 8, ., d) M68KMAKE_OP(cmpi, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint dst = M68KMAKE_GET_OPER_AY_8; uint res = dst - src; @@ -4184,8 +4184,8 @@ M68KMAKE_OP(cmpi, 8, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_8(); - uint dst = OPER_PCDI_8(); + uint src = OPER_I_8(state); + uint dst = OPER_PCDI_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4202,8 +4202,8 @@ M68KMAKE_OP(cmpi, 8, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_8(); - uint dst = OPER_PCIX_8(); + uint src = OPER_I_8(state); + uint dst = OPER_PCIX_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4218,7 +4218,7 @@ M68KMAKE_OP(cmpi, 8, ., pcix) M68KMAKE_OP(cmpi, 16, ., d) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint dst = MASK_OUT_ABOVE_16(DY); uint res = dst - src; @@ -4231,7 +4231,7 @@ M68KMAKE_OP(cmpi, 16, ., d) M68KMAKE_OP(cmpi, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint dst = M68KMAKE_GET_OPER_AY_16; uint res = dst - src; @@ -4246,8 +4246,8 @@ M68KMAKE_OP(cmpi, 16, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_16(); - uint dst = OPER_PCDI_16(); + uint src = OPER_I_16(state); + uint dst = OPER_PCDI_16(state); uint res = dst - src; FLAG_N = NFLAG_16(res); @@ -4264,8 +4264,8 @@ M68KMAKE_OP(cmpi, 16, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_16(); - uint dst = OPER_PCIX_16(); + uint src = OPER_I_16(state); + uint dst = OPER_PCIX_16(state); uint res = dst - src; FLAG_N = NFLAG_16(res); @@ -4280,7 +4280,7 @@ M68KMAKE_OP(cmpi, 16, ., pcix) M68KMAKE_OP(cmpi, 32, ., d) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint dst = DY; uint res = dst - src; @@ -4294,7 +4294,7 @@ M68KMAKE_OP(cmpi, 32, ., d) M68KMAKE_OP(cmpi, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint dst = M68KMAKE_GET_OPER_AY_32; uint res = dst - src; @@ -4309,8 +4309,8 @@ M68KMAKE_OP(cmpi, 32, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_32(); - uint dst = OPER_PCDI_32(); + uint src = OPER_I_32(state); + uint dst = OPER_PCDI_32(state); uint res = dst - src; FLAG_N = NFLAG_32(res); @@ -4327,8 +4327,8 @@ M68KMAKE_OP(cmpi, 32, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_I_32(); - uint dst = OPER_PCIX_32(); + uint src = OPER_I_32(state); + uint dst = OPER_PCIX_32(state); uint res = dst - src; FLAG_N = NFLAG_32(res); @@ -4343,8 +4343,8 @@ M68KMAKE_OP(cmpi, 32, ., pcix) M68KMAKE_OP(cmpm, 8, ., ax7) { - uint src = OPER_AY_PI_8(); - uint dst = OPER_A7_PI_8(); + uint src = OPER_AY_PI_8(state); + uint dst = OPER_A7_PI_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4356,8 +4356,8 @@ M68KMAKE_OP(cmpm, 8, ., ax7) M68KMAKE_OP(cmpm, 8, ., ay7) { - uint src = OPER_A7_PI_8(); - uint dst = OPER_AX_PI_8(); + uint src = OPER_A7_PI_8(state); + uint dst = OPER_AX_PI_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4369,8 +4369,8 @@ M68KMAKE_OP(cmpm, 8, ., ay7) M68KMAKE_OP(cmpm, 8, ., axy7) { - uint src = OPER_A7_PI_8(); - uint dst = OPER_A7_PI_8(); + uint src = OPER_A7_PI_8(state); + uint dst = OPER_A7_PI_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4382,8 +4382,8 @@ M68KMAKE_OP(cmpm, 8, ., axy7) M68KMAKE_OP(cmpm, 8, ., .) { - uint src = OPER_AY_PI_8(); - uint dst = OPER_AX_PI_8(); + uint src = OPER_AY_PI_8(state); + uint dst = OPER_AX_PI_8(state); uint res = dst - src; FLAG_N = NFLAG_8(res); @@ -4395,8 +4395,8 @@ M68KMAKE_OP(cmpm, 8, ., .) M68KMAKE_OP(cmpm, 16, ., .) { - uint src = OPER_AY_PI_16(); - uint dst = OPER_AX_PI_16(); + uint src = OPER_AY_PI_16(state); + uint dst = OPER_AX_PI_16(state); uint res = dst - src; FLAG_N = NFLAG_16(res); @@ -4408,8 +4408,8 @@ M68KMAKE_OP(cmpm, 16, ., .) M68KMAKE_OP(cmpm, 32, ., .) { - uint src = OPER_AY_PI_32(); - uint dst = OPER_AX_PI_32(); + uint src = OPER_AY_PI_32(state); + uint dst = OPER_AX_PI_32(state); uint res = dst - src; FLAG_N = NFLAG_32(res); @@ -4481,7 +4481,7 @@ M68KMAKE_OP(cptrapcc, 32, ., .) m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68ki_disassemble_quick(ADDRESS_68K(REG_PC - 2),CPU_TYPE))); // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct - REG_PC += 4; + REG_PC += 4; return; } m68ki_exception_1111(); @@ -4491,7 +4491,7 @@ M68KMAKE_OP(ftrapcc,32, ., .) { if(HAS_FPU) { - m68881_ftrap(); + m68881_ftrap(state); } else { m68ki_exception_1111(); } @@ -4511,7 +4511,7 @@ M68KMAKE_OP(dbf, 16, ., .) *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; if(res != 0xffff) { - uint offset = OPER_I_16(); + uint offset = OPER_I_16(state); REG_PC -= 2; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_16(offset); @@ -4533,7 +4533,7 @@ M68KMAKE_OP(dbcc, 16, ., .) *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; if(res != 0xffff) { - uint offset = OPER_I_16(); + uint offset = OPER_I_16(state); REG_PC -= 2; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ m68ki_branch_16(offset); @@ -4680,7 +4680,7 @@ M68KMAKE_OP(divl, 32, ., d) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint64 divisor = DY; uint64 dividend = 0; uint64 quotient = 0; @@ -4748,7 +4748,7 @@ M68KMAKE_OP(divl, 32, ., d) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint divisor = DY; uint dividend_hi = REG_D[word2 & 7]; uint dividend_lo = REG_D[(word2 >> 12) & 7]; @@ -4891,7 +4891,7 @@ M68KMAKE_OP(divl, 32, ., .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint64 divisor = M68KMAKE_GET_OPER_AY_32; uint64 dividend = 0; uint64 quotient = 0; @@ -4959,7 +4959,7 @@ M68KMAKE_OP(divl, 32, ., .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint divisor = M68KMAKE_GET_OPER_AY_32; uint dividend_hi = REG_D[word2 & 7]; uint dividend_lo = REG_D[(word2 >> 12) & 7]; @@ -5173,7 +5173,7 @@ M68KMAKE_OP(eor, 32, ., .) M68KMAKE_OP(eori, 8, ., d) { - uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); + uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(state)); FLAG_N = NFLAG_8(res); FLAG_Z = res; @@ -5184,7 +5184,7 @@ M68KMAKE_OP(eori, 8, ., d) M68KMAKE_OP(eori, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint ea = M68KMAKE_GET_EA_AY_8; uint res = src ^ m68ki_read_8(ea); @@ -5199,7 +5199,7 @@ M68KMAKE_OP(eori, 8, ., .) M68KMAKE_OP(eori, 16, ., d) { - uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); + uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(state)); FLAG_N = NFLAG_16(res); FLAG_Z = res; @@ -5210,7 +5210,7 @@ M68KMAKE_OP(eori, 16, ., d) M68KMAKE_OP(eori, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint res = src ^ m68ki_read_16(ea); @@ -5225,7 +5225,7 @@ M68KMAKE_OP(eori, 16, ., .) M68KMAKE_OP(eori, 32, ., d) { - uint res = DY ^= OPER_I_32(); + uint res = DY ^= OPER_I_32(state); FLAG_N = NFLAG_32(res); FLAG_Z = res; @@ -5236,7 +5236,7 @@ M68KMAKE_OP(eori, 32, ., d) M68KMAKE_OP(eori, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint ea = M68KMAKE_GET_EA_AY_32; uint res = src ^ m68ki_read_32(ea); @@ -5251,7 +5251,7 @@ M68KMAKE_OP(eori, 32, ., .) M68KMAKE_OP(eori, 16, toc, .) { - m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8()); + m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8(state)); } @@ -5259,9 +5259,9 @@ M68KMAKE_OP(eori, 16, tos, .) { if(FLAG_S) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() ^ src); + m68ki_set_sr(state, m68ki_get_sr() ^ src); return; } m68ki_exception_privilege_violation(); @@ -5373,7 +5373,7 @@ M68KMAKE_OP(link, 16, ., a7) { REG_A[7] -= 4; m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state))); } @@ -5383,7 +5383,7 @@ M68KMAKE_OP(link, 16, ., .) m68ki_push_32(*r_dst); *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state))); } @@ -5393,7 +5393,7 @@ M68KMAKE_OP(link, 32, ., a7) { REG_A[7] -= 4; m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state)); return; } m68ki_exception_illegal(); @@ -5408,7 +5408,7 @@ M68KMAKE_OP(link, 32, ., .) m68ki_push_32(*r_dst); *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(state)); return; } m68ki_exception_illegal(); @@ -6831,7 +6831,7 @@ M68KMAKE_OP(move, 16, tos, d) { if(FLAG_S) { - m68ki_set_sr(DY); + m68ki_set_sr(state, DY); return; } m68ki_exception_privilege_violation(); @@ -6844,7 +6844,7 @@ M68KMAKE_OP(move, 16, tos, .) { uint new_sr = M68KMAKE_GET_OPER_AY_16; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); return; } m68ki_exception_privilege_violation(); @@ -6880,7 +6880,7 @@ M68KMAKE_OP(movec, 32, cr, .) { if(FLAG_S) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ switch (word2 & 0xfff) @@ -7010,7 +7010,7 @@ M68KMAKE_OP(movec, 32, rc, .) { if(FLAG_S) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ switch (word2 & 0xfff) @@ -7175,7 +7175,7 @@ M68KMAKE_OP(movec, 32, rc, .) M68KMAKE_OP(movem, 16, re, pd) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = AY; uint count = 0; @@ -7195,7 +7195,7 @@ M68KMAKE_OP(movem, 16, re, pd) M68KMAKE_OP(movem, 16, re, .) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint count = 0; @@ -7214,7 +7214,7 @@ M68KMAKE_OP(movem, 16, re, .) M68KMAKE_OP(movem, 32, re, pd) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = AY; uint count = 0; @@ -7235,7 +7235,7 @@ M68KMAKE_OP(movem, 32, re, pd) M68KMAKE_OP(movem, 32, re, .) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_32; uint count = 0; @@ -7254,7 +7254,7 @@ M68KMAKE_OP(movem, 32, re, .) M68KMAKE_OP(movem, 16, er, pi) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = AY; uint count = 0; @@ -7274,7 +7274,7 @@ M68KMAKE_OP(movem, 16, er, pi) M68KMAKE_OP(movem, 16, er, pcdi) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = EA_PCDI_16(); uint count = 0; @@ -7293,7 +7293,7 @@ M68KMAKE_OP(movem, 16, er, pcdi) M68KMAKE_OP(movem, 16, er, pcix) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = EA_PCIX_16(); uint count = 0; @@ -7312,7 +7312,7 @@ M68KMAKE_OP(movem, 16, er, pcix) M68KMAKE_OP(movem, 16, er, .) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint count = 0; @@ -7331,7 +7331,7 @@ M68KMAKE_OP(movem, 16, er, .) M68KMAKE_OP(movem, 32, er, pi) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = AY; uint count = 0; @@ -7351,7 +7351,7 @@ M68KMAKE_OP(movem, 32, er, pi) M68KMAKE_OP(movem, 32, er, pcdi) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = EA_PCDI_32(); uint count = 0; @@ -7370,7 +7370,7 @@ M68KMAKE_OP(movem, 32, er, pcdi) M68KMAKE_OP(movem, 32, er, pcix) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = EA_PCIX_32(); uint count = 0; @@ -7389,7 +7389,7 @@ M68KMAKE_OP(movem, 32, er, pcix) M68KMAKE_OP(movem, 32, er, .) { uint i = 0; - uint register_list = OPER_I_16(); + uint register_list = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_32; uint count = 0; @@ -7451,7 +7451,7 @@ M68KMAKE_OP(moves, 8, ., .) { if(FLAG_S) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_8; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ @@ -7486,7 +7486,7 @@ M68KMAKE_OP(moves, 16, ., .) { if(FLAG_S) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ @@ -7521,7 +7521,7 @@ M68KMAKE_OP(moves, 32, ., .) { if(FLAG_S) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_32; m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ @@ -7558,7 +7558,7 @@ M68KMAKE_OP(moveq, 32, ., .) M68KMAKE_OP(move16, 32, ., .) { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); int ax = REG_IR & 7; int ay = (w2 >> 12) & 7; @@ -7634,7 +7634,7 @@ M68KMAKE_OP(mull, 32, ., d) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint64 src = DY; uint64 dst = REG_D[(word2 >> 12) & 7]; uint64 res; @@ -7682,7 +7682,7 @@ M68KMAKE_OP(mull, 32, ., d) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint src = DY; uint dst = REG_D[(word2 >> 12) & 7]; uint neg = GET_MSB_32(src ^ dst); @@ -7758,7 +7758,7 @@ M68KMAKE_OP(mull, 32, ., .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint64 src = M68KMAKE_GET_OPER_AY_32; uint64 dst = REG_D[(word2 >> 12) & 7]; uint64 res; @@ -7806,7 +7806,7 @@ M68KMAKE_OP(mull, 32, ., .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint word2 = OPER_I_16(); + uint word2 = OPER_I_16(state); uint src = M68KMAKE_GET_OPER_AY_32; uint dst = REG_D[(word2 >> 12) & 7]; uint neg = GET_MSB_32(src ^ dst); @@ -8326,7 +8326,7 @@ M68KMAKE_OP(or, 32, re, .) M68KMAKE_OP(ori, 8, ., d) { - uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8())); + uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(state))); FLAG_N = NFLAG_8(res); FLAG_Z = res; @@ -8337,7 +8337,7 @@ M68KMAKE_OP(ori, 8, ., d) M68KMAKE_OP(ori, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint ea = M68KMAKE_GET_EA_AY_8; uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); @@ -8352,7 +8352,7 @@ M68KMAKE_OP(ori, 8, ., .) M68KMAKE_OP(ori, 16, ., d) { - uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16()); + uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(state)); FLAG_N = NFLAG_16(res); FLAG_Z = res; @@ -8363,7 +8363,7 @@ M68KMAKE_OP(ori, 16, ., d) M68KMAKE_OP(ori, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); @@ -8378,7 +8378,7 @@ M68KMAKE_OP(ori, 16, ., .) M68KMAKE_OP(ori, 32, ., d) { - uint res = DY |= OPER_I_32(); + uint res = DY |= OPER_I_32(state); FLAG_N = NFLAG_32(res); FLAG_Z = res; @@ -8389,7 +8389,7 @@ M68KMAKE_OP(ori, 32, ., d) M68KMAKE_OP(ori, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint ea = M68KMAKE_GET_EA_AY_32; uint res = src | m68ki_read_32(ea); @@ -8404,7 +8404,7 @@ M68KMAKE_OP(ori, 32, ., .) M68KMAKE_OP(ori, 16, toc, .) { - m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8()); + m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8(state)); } @@ -8412,9 +8412,9 @@ M68KMAKE_OP(ori, 16, tos, .) { if(FLAG_S) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() | src); + m68ki_set_sr(state, m68ki_get_sr() | src); return; } m68ki_exception_privilege_violation(); @@ -8426,7 +8426,7 @@ M68KMAKE_OP(pack, 16, rr, .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { /* Note: DX and DY are reversed in Motorola's docs */ - uint src = DY + OPER_I_16(); + uint src = DY + OPER_I_16(state); uint* r_dst = &DX; *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); @@ -8444,7 +8444,7 @@ M68KMAKE_OP(pack, 16, mm, ax7) uint ea_src = EA_AY_PD_8(); uint src = m68ki_read_8(ea_src); ea_src = EA_AY_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(state); m68ki_write_8(EA_A7_PD_8(), ((src >> 8) & 0x000f) | ((src<<4) & 0x00f0)); return; @@ -8461,7 +8461,7 @@ M68KMAKE_OP(pack, 16, mm, ay7) uint ea_src = EA_A7_PD_8(); uint src = m68ki_read_8(ea_src); ea_src = EA_A7_PD_8(); - src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(); + src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state); m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); return; @@ -8477,7 +8477,7 @@ M68KMAKE_OP(pack, 16, mm, axy7) uint ea_src = EA_A7_PD_8(); uint src = m68ki_read_8(ea_src); ea_src = EA_A7_PD_8(); - src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(); + src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state); m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); return; @@ -8494,7 +8494,7 @@ M68KMAKE_OP(pack, 16, mm, .) uint ea_src = EA_AY_PD_8(); uint src = m68ki_read_8(ea_src); ea_src = EA_AY_PD_8(); - src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(); + src = (src | (m68ki_read_8(ea_src) << 8)) + OPER_I_16(state); m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); return; @@ -8534,7 +8534,7 @@ M68KMAKE_OP(pmmu, 32, ., .) { if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU)) { - m68851_mmu_ops(); + void m68851_mmu_ops(m68ki_cpu_core *state); } else { @@ -9335,7 +9335,7 @@ M68KMAKE_OP(rtd, 32, ., .) uint new_pc = m68ki_pull_32(); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(state))); m68ki_jump(new_pc); return; } @@ -9359,7 +9359,7 @@ M68KMAKE_OP(rte, 32, ., .) new_sr = m68ki_pull_16(); new_pc = m68ki_pull_32(); m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; @@ -9376,7 +9376,7 @@ M68KMAKE_OP(rte, 32, ., .) new_pc = m68ki_pull_32(); m68ki_fake_pull_16(); /* format word */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9386,7 +9386,7 @@ M68KMAKE_OP(rte, 32, ., .) new_pc = m68ki_pull_32(); m68ki_fake_pull_16(); /* format word */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; m68ki_fake_pull_16(); /* special status */ @@ -9421,7 +9421,7 @@ rte_loop: new_pc = m68ki_pull_32(); m68ki_fake_pull_16(); /* format word */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9429,7 +9429,7 @@ rte_loop: new_sr = m68ki_pull_16(); m68ki_fake_pull_32(); /* program counter */ m68ki_fake_pull_16(); /* format word */ - m68ki_set_sr_noint(new_sr); + m68ki_set_sr_noint(state, new_sr); goto rte_loop; case 2: /* Trap */ new_sr = m68ki_pull_16(); @@ -9437,7 +9437,7 @@ rte_loop: m68ki_fake_pull_16(); /* format word */ m68ki_fake_pull_32(); /* address */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9461,7 +9461,7 @@ rte_loop: m68ki_fake_pull_32(); /* $34: pd2 */ m68ki_fake_pull_32(); /* $38: pd3 */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9480,7 +9480,7 @@ rte_loop: m68ki_fake_pull_32(); /* $1c: internal registers */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9515,7 +9515,7 @@ rte_loop: m68ki_fake_pull_32(); /* $58: */ m68ki_jump(new_pc); - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); CPU_INSTR_MODE = INSTRUCTION_YES; CPU_RUN_MODE = RUN_MODE_NORMAL; return; @@ -9591,7 +9591,7 @@ M68KMAKE_OP(sbcd, 8, rr, .) M68KMAKE_OP(sbcd, 8, mm, ax7) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); @@ -9621,7 +9621,7 @@ M68KMAKE_OP(sbcd, 8, mm, ax7) M68KMAKE_OP(sbcd, 8, mm, ay7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); @@ -9651,7 +9651,7 @@ M68KMAKE_OP(sbcd, 8, mm, ay7) M68KMAKE_OP(sbcd, 8, mm, axy7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); @@ -9681,7 +9681,7 @@ M68KMAKE_OP(sbcd, 8, mm, axy7) M68KMAKE_OP(sbcd, 8, mm, .) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); @@ -9755,10 +9755,10 @@ M68KMAKE_OP(stop, 0, ., .) { if(FLAG_S) { - uint new_sr = OPER_I_16(); + uint new_sr = OPER_I_16(state); m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ CPU_STOPPED |= STOP_LEVEL_STOP; - m68ki_set_sr(new_sr); + m68ki_set_sr(state, new_sr); if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR]) m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR]; else @@ -9998,7 +9998,7 @@ M68KMAKE_OP(suba, 32, ., .) M68KMAKE_OP(subi, 8, ., d) { uint* r_dst = &DY; - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint dst = MASK_OUT_ABOVE_8(*r_dst); uint res = dst - src; @@ -10013,7 +10013,7 @@ M68KMAKE_OP(subi, 8, ., d) M68KMAKE_OP(subi, 8, ., .) { - uint src = OPER_I_8(); + uint src = OPER_I_8(state); uint ea = M68KMAKE_GET_EA_AY_8; uint dst = m68ki_read_8(ea); uint res = dst - src; @@ -10030,7 +10030,7 @@ M68KMAKE_OP(subi, 8, ., .) M68KMAKE_OP(subi, 16, ., d) { uint* r_dst = &DY; - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint dst = MASK_OUT_ABOVE_16(*r_dst); uint res = dst - src; @@ -10045,7 +10045,7 @@ M68KMAKE_OP(subi, 16, ., d) M68KMAKE_OP(subi, 16, ., .) { - uint src = OPER_I_16(); + uint src = OPER_I_16(state); uint ea = M68KMAKE_GET_EA_AY_16; uint dst = m68ki_read_16(ea); uint res = dst - src; @@ -10062,7 +10062,7 @@ M68KMAKE_OP(subi, 16, ., .) M68KMAKE_OP(subi, 32, ., d) { uint* r_dst = &DY; - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint dst = *r_dst; uint res = dst - src; @@ -10077,7 +10077,7 @@ M68KMAKE_OP(subi, 32, ., d) M68KMAKE_OP(subi, 32, ., .) { - uint src = OPER_I_32(); + uint src = OPER_I_32(state); uint ea = M68KMAKE_GET_EA_AY_32; uint dst = m68ki_read_32(ea); uint res = dst - src; @@ -10259,7 +10259,7 @@ M68KMAKE_OP(subx, 32, rr, .) M68KMAKE_OP(subx, 8, mm, ax7) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10277,7 +10277,7 @@ M68KMAKE_OP(subx, 8, mm, ax7) M68KMAKE_OP(subx, 8, mm, ay7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10295,7 +10295,7 @@ M68KMAKE_OP(subx, 8, mm, ay7) M68KMAKE_OP(subx, 8, mm, axy7) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea = EA_A7_PD_8(); uint dst = m68ki_read_8(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10313,7 +10313,7 @@ M68KMAKE_OP(subx, 8, mm, axy7) M68KMAKE_OP(subx, 8, mm, .) { - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea = EA_AX_PD_8(); uint dst = m68ki_read_8(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10331,7 +10331,7 @@ M68KMAKE_OP(subx, 8, mm, .) M68KMAKE_OP(subx, 16, mm, .) { - uint src = OPER_AY_PD_16(); + uint src = OPER_AY_PD_16(state); uint ea = EA_AX_PD_16(); uint dst = m68ki_read_16(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10349,7 +10349,7 @@ M68KMAKE_OP(subx, 16, mm, .) M68KMAKE_OP(subx, 32, mm, .) { - uint src = OPER_AY_PD_32(); + uint src = OPER_AY_PD_32(state); uint ea = EA_AX_PD_32(); uint dst = m68ki_read_32(ea); uint res = dst - src - XFLAG_AS_1(); @@ -10571,7 +10571,7 @@ M68KMAKE_OP(tst, 8, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCDI_8(); + uint res = OPER_PCDI_8(state); FLAG_N = NFLAG_8(res); FLAG_Z = res; @@ -10587,7 +10587,7 @@ M68KMAKE_OP(tst, 8, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCIX_8(); + uint res = OPER_PCIX_8(state); FLAG_N = NFLAG_8(res); FLAG_Z = res; @@ -10603,7 +10603,7 @@ M68KMAKE_OP(tst, 8, ., i) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_I_8(); + uint res = OPER_I_8(state); FLAG_N = NFLAG_8(res); FLAG_Z = res; @@ -10657,7 +10657,7 @@ M68KMAKE_OP(tst, 16, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCDI_16(); + uint res = OPER_PCDI_16(state); FLAG_N = NFLAG_16(res); FLAG_Z = res; @@ -10673,7 +10673,7 @@ M68KMAKE_OP(tst, 16, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCIX_16(); + uint res = OPER_PCIX_16(state); FLAG_N = NFLAG_16(res); FLAG_Z = res; @@ -10689,7 +10689,7 @@ M68KMAKE_OP(tst, 16, ., i) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_I_16(); + uint res = OPER_I_16(state); FLAG_N = NFLAG_16(res); FLAG_Z = res; @@ -10743,7 +10743,7 @@ M68KMAKE_OP(tst, 32, ., pcdi) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCDI_32(); + uint res = OPER_PCDI_32(state); FLAG_N = NFLAG_32(res); FLAG_Z = res; @@ -10759,7 +10759,7 @@ M68KMAKE_OP(tst, 32, ., pcix) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_PCIX_32(); + uint res = OPER_PCIX_32(state); FLAG_N = NFLAG_32(res); FLAG_Z = res; @@ -10775,7 +10775,7 @@ M68KMAKE_OP(tst, 32, ., i) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint res = OPER_I_32(); + uint res = OPER_I_32(state); FLAG_N = NFLAG_32(res); FLAG_Z = res; @@ -10810,7 +10810,7 @@ M68KMAKE_OP(unpk, 16, rr, .) uint src = DY; uint* r_dst = &DX; - *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff); + *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state)) & 0xffff); return; } m68ki_exception_illegal(); @@ -10822,10 +10822,10 @@ M68KMAKE_OP(unpk, 16, mm, ax7) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea_dst; - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state); ea_dst = EA_A7_PD_8(); m68ki_write_8(ea_dst, src & 0xff); ea_dst = EA_A7_PD_8(); @@ -10841,10 +10841,10 @@ M68KMAKE_OP(unpk, 16, mm, ay7) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea_dst; - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state); ea_dst = EA_AX_PD_8(); m68ki_write_8(ea_dst, src & 0xff); ea_dst = EA_AX_PD_8(); @@ -10859,10 +10859,10 @@ M68KMAKE_OP(unpk, 16, mm, axy7) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - uint src = OPER_A7_PD_8(); + uint src = OPER_A7_PD_8(state); uint ea_dst; - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state); ea_dst = EA_A7_PD_8(); m68ki_write_8(ea_dst, src & 0xff); ea_dst = EA_A7_PD_8(); @@ -10878,10 +10878,10 @@ M68KMAKE_OP(unpk, 16, mm, .) if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); + uint src = OPER_AY_PD_8(state); uint ea_dst; - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(state); ea_dst = EA_AX_PD_8(); m68ki_write_8(ea_dst, src & 0xff); ea_dst = EA_AX_PD_8(); diff --git a/m68kcpu.c b/m68kcpu.c index d30ad93..d933eca 100644 --- a/m68kcpu.c +++ b/m68kcpu.c @@ -37,10 +37,10 @@ /* ======================================================================== */ /* ================================ INCLUDES ============================== */ /* ======================================================================== */ - -extern void m68040_fpu_op0(void); -extern void m68040_fpu_op1(void); -extern void m68851_mmu_ops(); +struct m68ki_cpu_core; +extern void m68040_fpu_op0(struct m68ki_cpu_core *state); +extern void m68040_fpu_op1(struct m68ki_cpu_core *state); +extern void m68851_mmu_ops(struct m68ki_cpu_core *state); extern unsigned char m68ki_cycles[][0x10000]; extern void m68ki_build_opcode_table(void); @@ -974,7 +974,7 @@ int m68k_execute(m68ki_cpu_core *state, int num_cycles) m68ki_initial_cycles = num_cycles; /* See if interrupts came in */ - m68ki_check_interrupts(); + m68ki_check_interrupts(state); /* Make sure we're not stopped */ if(!CPU_STOPPED) @@ -989,7 +989,7 @@ int m68k_execute(m68ki_cpu_core *state, int num_cycles) /* Main loop. Keep going until we run out of clock cycles */ do { - /* Set tracing accodring to T1. (T0 is done inside instruction) */ + /* Set tracing according to T1. (T0 is done inside instruction) */ m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ /* Set the address space for reads */ @@ -1010,8 +1010,8 @@ int m68k_execute(m68ki_cpu_core *state, int num_cycles) #endif /* Read an instruction and call its handler */ - REG_IR = m68ki_read_imm_16(); - m68ki_instruction_jump_table[REG_IR](&m68ki_cpu); + REG_IR = m68ki_read_imm_16(state); + m68ki_instruction_jump_table[REG_IR](state); USE_CYCLES(CYC_INSTRUCTION[REG_IR]); /* Trace m68k_exception, if necessary */ @@ -1158,8 +1158,8 @@ void m68k_pulse_reset(m68ki_cpu_core *state) /* Read the initial stack pointer and program counter */ m68ki_jump(0); - REG_SP = m68ki_read_imm_32(); - REG_PC = m68ki_read_imm_32(); + REG_SP = m68ki_read_imm_32(state); + REG_PC = m68ki_read_imm_32(state); m68ki_jump(REG_PC); CPU_RUN_MODE = RUN_MODE_NORMAL; @@ -1167,7 +1167,7 @@ void m68k_pulse_reset(m68ki_cpu_core *state) RESET_CYCLES = CYC_EXCEPTION[EXCEPTION_RESET]; /* flush the MMU's cache */ - pmmu_atc_flush(); + pmmu_atc_flush(state); if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { diff --git a/m68kcpu.h b/m68kcpu.h index cd4d07e..dd8d1cf 100644 --- a/m68kcpu.h +++ b/m68kcpu.h @@ -725,10 +725,10 @@ extern jmp_buf m68ki_aerr_trap; #define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */ #define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */ #define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */ -#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */ +#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16(state))) /* displacement */ #define EA_AY_DI_16() EA_AY_DI_8() #define EA_AY_DI_32() EA_AY_DI_8() -#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */ +#define EA_AY_IX_8() m68ki_get_ea_ix(state, AY) /* indirect + index */ #define EA_AY_IX_16() EA_AY_IX_8() #define EA_AY_IX_32() EA_AY_IX_8() @@ -741,33 +741,33 @@ extern jmp_buf m68ki_aerr_trap; #define EA_AX_PD_8() (--AX) #define EA_AX_PD_16() (AX-=2) #define EA_AX_PD_32() (AX-=4) -#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16())) +#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16(state))) #define EA_AX_DI_16() EA_AX_DI_8() #define EA_AX_DI_32() EA_AX_DI_8() -#define EA_AX_IX_8() m68ki_get_ea_ix(AX) +#define EA_AX_IX_8() m68ki_get_ea_ix(state, AX) #define EA_AX_IX_16() EA_AX_IX_8() #define EA_AX_IX_32() EA_AX_IX_8() #define EA_A7_PI_8() ((REG_A[7]+=2)-2) #define EA_A7_PD_8() (REG_A[7]-=2) -#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */ +#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16(state)) /* absolute word */ #define EA_AW_16() EA_AW_8() #define EA_AW_32() EA_AW_8() -#define EA_AL_8() m68ki_read_imm_32() /* absolute long */ +#define EA_AL_8() m68ki_read_imm_32(state) /* absolute long */ #define EA_AL_16() EA_AL_8() #define EA_AL_32() EA_AL_8() -#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */ +#define EA_PCDI_8() m68ki_get_ea_pcdi(state) /* pc indirect + displacement */ #define EA_PCDI_16() EA_PCDI_8() #define EA_PCDI_32() EA_PCDI_8() -#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */ +#define EA_PCIX_8() m68ki_get_ea_pcix(state) /* pc indirect + index */ #define EA_PCIX_16() EA_PCIX_8() #define EA_PCIX_32() EA_PCIX_8() -#define OPER_I_8() m68ki_read_imm_8() -#define OPER_I_16() m68ki_read_imm_16() -#define OPER_I_32() m68ki_read_imm_32() +#define OPER_I_8(state) m68ki_read_imm_8(state) +#define OPER_I_16(state) m68ki_read_imm_16(state) +#define OPER_I_32(state) m68ki_read_imm_32(state) @@ -1084,8 +1084,8 @@ extern uint m68ki_aerr_fc; /* Forward declarations to keep some of the macros happy */ static inline uint m68ki_read_16_fc (uint address, uint fc); static inline uint m68ki_read_32_fc (uint address, uint fc); -static inline uint m68ki_get_ea_ix(uint An); -static inline void m68ki_check_interrupts(void); /* ASG: check for interrupts */ +static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An); +static inline void m68ki_check_interrupts(m68ki_cpu_core *state); /* ASG: check for interrupts */ /* quick disassembly (used for logging) */ char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type); @@ -1107,7 +1107,7 @@ inline void m68ki_ic_clear(m68ki_cpu_core *state) } } -extern uint32 pmmu_translate_addr(uint32 addr_in, const uint16 rw); +extern uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw); // read immediate word using the instruction cache @@ -1169,7 +1169,7 @@ uint m68ki_read_imm6_addr_slowpath(uint32_t pc, address_translation_cache *cache -static inline uint m68ki_read_imm_16(void) +static inline uint m68ki_read_imm_16(m68ki_cpu_core *state) { uint32_t pc = REG_PC; @@ -1182,13 +1182,13 @@ static inline uint m68ki_read_imm_16(void) return m68ki_read_imm6_addr_slowpath(pc, cache); } -static inline uint m68ki_read_imm_8(void) +static inline uint m68ki_read_imm_8(m68ki_cpu_core *state) { /* map read immediate 8 to read immediate 16 */ - return MASK_OUT_ABOVE_8(m68ki_read_imm_16()); + return MASK_OUT_ABOVE_8(m68ki_read_imm_16(state)); } -static inline uint m68ki_read_imm_32(void) +static inline uint m68ki_read_imm_32(m68ki_cpu_core *state) { #if M68K_SEPARATE_READS #if M68K_EMULATE_PMMU @@ -1403,18 +1403,18 @@ static inline void m68ki_write_32_pd_fc(uint address, uint fc, uint value) /* The program counter relative addressing modes cause operands to be * retrieved from program space, not data space. */ -static inline uint m68ki_get_ea_pcdi(void) +static inline uint m68ki_get_ea_pcdi(m68ki_cpu_core *state) { uint old_pc = REG_PC; m68ki_use_program_space(); /* auto-disable */ - return old_pc + MAKE_INT_16(m68ki_read_imm_16()); + return old_pc + MAKE_INT_16(m68ki_read_imm_16(state)); } -static inline uint m68ki_get_ea_pcix(void) +static inline uint m68ki_get_ea_pcix(m68ki_cpu_core *state) { m68ki_use_program_space(); /* auto-disable */ - return m68ki_get_ea_ix(REG_PC); + return m68ki_get_ea_ix(state, REG_PC); } /* Indexed addressing modes are encoded as follows: @@ -1459,10 +1459,10 @@ static inline uint m68ki_get_ea_pcix(void) * 1 011 mem indir with long outer * 1 100-111 reserved */ -static inline uint m68ki_get_ea_ix(uint An) +static inline uint m68ki_get_ea_ix(m68ki_cpu_core *state, uint An) { /* An = base register */ - uint extension = m68ki_read_imm_16(); + uint extension = m68ki_read_imm_16(state); uint Xn = 0; /* Index register */ uint bd = 0; /* Base Displacement */ uint od = 0; /* Outer Displacement */ @@ -1512,7 +1512,7 @@ static inline uint m68ki_get_ea_ix(uint An) /* Check if base displacement is present */ if(BIT_5(extension)) /* BD SIZE */ - bd = BIT_4(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16()); + bd = BIT_4(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state)); /* If no indirect action, we are done */ if(!(extension&7)) /* No Memory Indirect */ @@ -1520,7 +1520,7 @@ static inline uint m68ki_get_ea_ix(uint An) /* Check if outer displacement is present */ if(BIT_1(extension)) /* I/IS: od */ - od = BIT_0(extension) ? m68ki_read_imm_32() : (uint32)MAKE_INT_16(m68ki_read_imm_16()); + od = BIT_0(extension) ? m68ki_read_imm_32(state) : (uint32)MAKE_INT_16(m68ki_read_imm_16(state)); /* Postindex */ if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */ @@ -1532,53 +1532,53 @@ static inline uint m68ki_get_ea_ix(uint An) /* Fetch operands */ -static inline uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } -static inline uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} -static inline uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} -static inline uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } -static inline uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} -static inline uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} - -static inline uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } -static inline uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} -static inline uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} -static inline uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } -static inline uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} -static inline uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} -static inline uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } -static inline uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} -static inline uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} - -static inline uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } -static inline uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } - -static inline uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } -static inline uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} -static inline uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} -static inline uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } -static inline uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} -static inline uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} -static inline uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } -static inline uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} -static inline uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} -static inline uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } -static inline uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} -static inline uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} +static inline uint OPER_AY_AI_8(m68ki_cpu_core *state) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_AI_16(m68ki_cpu_core *state) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_AI_32(m68ki_cpu_core *state) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_PI_8(m68ki_cpu_core *state) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_PI_16(m68ki_cpu_core *state) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_PI_32(m68ki_cpu_core *state) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_PD_8(m68ki_cpu_core *state) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_PD_16(m68ki_cpu_core *state) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_PD_32(m68ki_cpu_core *state) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_DI_8(m68ki_cpu_core *state) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_DI_16(m68ki_cpu_core *state) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_DI_32(m68ki_cpu_core *state) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_IX_8(m68ki_cpu_core *state) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_IX_16(m68ki_cpu_core *state) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_IX_32(m68ki_cpu_core *state) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} + +static inline uint OPER_AX_AI_8(m68ki_cpu_core *state) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_AI_16(m68ki_cpu_core *state) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_AI_32(m68ki_cpu_core *state) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_PI_8(m68ki_cpu_core *state) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_PI_16(m68ki_cpu_core *state) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_PI_32(m68ki_cpu_core *state) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_PD_8(m68ki_cpu_core *state) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_PD_16(m68ki_cpu_core *state) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_PD_32(m68ki_cpu_core *state) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_DI_8(m68ki_cpu_core *state) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_DI_16(m68ki_cpu_core *state) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_DI_32(m68ki_cpu_core *state) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_IX_8(m68ki_cpu_core *state) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_IX_16(m68ki_cpu_core *state) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_IX_32(m68ki_cpu_core *state) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} + +static inline uint OPER_A7_PI_8(m68ki_cpu_core *state) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_A7_PD_8(m68ki_cpu_core *state) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } + +static inline uint OPER_AW_8(m68ki_cpu_core *state) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } +static inline uint OPER_AW_16(m68ki_cpu_core *state) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} +static inline uint OPER_AW_32(m68ki_cpu_core *state) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} +static inline uint OPER_AL_8(m68ki_cpu_core *state) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } +static inline uint OPER_AL_16(m68ki_cpu_core *state) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} +static inline uint OPER_AL_32(m68ki_cpu_core *state) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} +static inline uint OPER_PCDI_8(m68ki_cpu_core *state) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } +static inline uint OPER_PCDI_16(m68ki_cpu_core *state) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} +static inline uint OPER_PCDI_32(m68ki_cpu_core *state) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} +static inline uint OPER_PCIX_8(m68ki_cpu_core *state) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } +static inline uint OPER_PCIX_16(m68ki_cpu_core *state) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} +static inline uint OPER_PCIX_32(m68ki_cpu_core *state) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} @@ -1724,7 +1724,7 @@ static inline void m68ki_set_ccr(uint value) } /* Set the status register but don't check for interrupts */ -static inline void m68ki_set_sr_noint(uint value) +static inline void m68ki_set_sr_noint(m68ki_cpu_core *state, uint value) { /* Mask out the "unimplemented" bits */ value &= CPU_SR_MASK; @@ -1754,10 +1754,10 @@ static inline void m68ki_set_sr_noint_nosp(uint value) } /* Set the status register and check for interrupts */ -static inline void m68ki_set_sr(uint value) +static inline void m68ki_set_sr(m68ki_cpu_core *state, uint value) { - m68ki_set_sr_noint(value); - m68ki_check_interrupts(); + m68ki_set_sr_noint(state, value); + m68ki_check_interrupts(state); } @@ -2376,7 +2376,7 @@ static inline void m68ki_exception_interrupt(uint int_level) /* ASG: Check for interrupts */ -static inline void m68ki_check_interrupts(void) +static inline void m68ki_check_interrupts(m68ki_cpu_core *state) { if(m68ki_cpu.nmi_pending) { diff --git a/m68kfpu.c b/m68kfpu.c index 68c3f6f..43210fe 100644 --- a/m68kfpu.c +++ b/m68kfpu.c @@ -4,6 +4,7 @@ #include #include "softfloat/softfloat.h" + float_status status; extern void exit(int); @@ -380,7 +381,7 @@ static inline int TEST_CONDITION(int condition) return r; } -static uint8 READ_EA_8(int ea) +static uint8 READ_EA_8(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -422,13 +423,13 @@ static uint8 READ_EA_8(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_8(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_8(ea); } @@ -439,12 +440,12 @@ static uint8 READ_EA_8(int ea) } case 3: // (PC) + (Xn) + d8 { - uint32 ea = EA_PCIX_8(); + uint32 ea = EA_PCIX_8(); return m68ki_read_8(ea); } case 4: // # { - return OPER_I_8(); + return OPER_I_8(state); } default: fatalerror("M68kFPU: READ_EA_8: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -456,7 +457,7 @@ static uint8 READ_EA_8(int ea) return 0; } -static uint16 READ_EA_16(int ea) +static uint16 READ_EA_16(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -498,13 +499,13 @@ static uint16 READ_EA_16(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_16(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_16(ea); } @@ -520,7 +521,7 @@ static uint16 READ_EA_16(int ea) } case 4: // # { - return OPER_I_16(); + return OPER_I_16(state); } default: fatalerror("M68kFPU: READ_EA_16: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); @@ -533,7 +534,7 @@ static uint16 READ_EA_16(int ea) return 0; } -static uint32 READ_EA_32(int ea) +static uint32 READ_EA_32(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -575,13 +576,13 @@ static uint32 READ_EA_32(int ea) { case 0: // (xxx).W { - uint32 ea = (uint32)OPER_I_16(); + uint32 ea = (uint32) OPER_I_16(state); return m68ki_read_32(ea); } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return m68ki_read_32(ea); } @@ -597,7 +598,7 @@ static uint32 READ_EA_32(int ea) } case 4: // # { - return OPER_I_32(); + return OPER_I_32(state); } default: fatalerror("M68kFPU: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } @@ -608,7 +609,7 @@ static uint32 READ_EA_32(int ea) return 0; } -static uint64 READ_EA_64(int ea) +static uint64 READ_EA_64(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -659,8 +660,8 @@ static uint64 READ_EA_64(int ea) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return (uint64)(m68ki_read_32(ea)) << 32 | (uint64)(m68ki_read_32(ea+4)); } @@ -673,8 +674,8 @@ static uint64 READ_EA_64(int ea) } case 4: // # { - h1 = OPER_I_32(); - h2 = OPER_I_32(); + h1 = OPER_I_32(state); + h2 = OPER_I_32(state); return (uint64)(h1) << 32 | (uint64)(h2); } case 2: // (d16, PC) @@ -695,7 +696,7 @@ static uint64 READ_EA_64(int ea) } -static floatx80 READ_EA_FPE(uint32 ea) +static floatx80 READ_EA_FPE(m68ki_cpu_core *state, uint32 ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -745,8 +746,8 @@ static floatx80 READ_EA_FPE(uint32 ea) { case 1: // (xxx) { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; fpr = load_extended_float80(ea); } @@ -787,7 +788,7 @@ static floatx80 READ_EA_FPE(uint32 ea) return fpr; } -static floatx80 READ_EA_PACK(int ea) +static floatx80 READ_EA_PACK(m68ki_cpu_core *state, int ea) { floatx80 fpr; int mode = (ea >> 3) & 0x7; @@ -834,7 +835,7 @@ static floatx80 READ_EA_PACK(int ea) return fpr; } -static void WRITE_EA_8(int ea, uint8 data) +static void WRITE_EA_8(m68ki_cpu_core *state, int ea, uint8 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -882,8 +883,8 @@ static void WRITE_EA_8(int ea, uint8 data) { case 1: // (xxx).B { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_8(ea, data); break; @@ -902,7 +903,7 @@ static void WRITE_EA_8(int ea, uint8 data) } } -static void WRITE_EA_16(int ea, uint16 data) +static void WRITE_EA_16(m68ki_cpu_core *state, int ea, uint16 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -950,8 +951,8 @@ static void WRITE_EA_16(int ea, uint16 data) { case 1: // (xxx).W { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_16(ea, data); break; @@ -970,7 +971,7 @@ static void WRITE_EA_16(int ea, uint16 data) } } -static void WRITE_EA_32(int ea, uint32 data) +static void WRITE_EA_32(m68ki_cpu_core *state, int ea, uint32 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1023,14 +1024,14 @@ static void WRITE_EA_32(int ea, uint32 data) { case 0: // (xxx).W { - uint32 ea = OPER_I_16(); + uint32 ea = OPER_I_16(state); m68ki_write_32(ea, data); break; } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_32(ea, data); break; @@ -1049,7 +1050,7 @@ static void WRITE_EA_32(int ea, uint32 data) } } -static void WRITE_EA_64(int ea, uint64 data) +static void WRITE_EA_64(m68ki_cpu_core *state, int ea, uint64 data) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1100,8 +1101,8 @@ static void WRITE_EA_64(int ea, uint64 data) { case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; m68ki_write_32(ea+0, (uint32)(data >> 32)); m68ki_write_32(ea+4, (uint32)(data)); @@ -1122,7 +1123,7 @@ static void WRITE_EA_64(int ea, uint64 data) } } -static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) +static void WRITE_EA_FPE(m68ki_cpu_core *state, uint32 ea, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1173,7 +1174,7 @@ static void WRITE_EA_FPE(uint32 ea, floatx80 fpr) } } -static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) +static void WRITE_EA_PACK(m68ki_cpu_core *state, int ea, int k, floatx80 fpr) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -1219,7 +1220,7 @@ static void WRITE_EA_PACK(int ea, int k, floatx80 fpr) } -static void fpgen_rm_reg(uint16 w2) +static void fpgen_rm_reg(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int rm = (w2 >> 14) & 0x1; @@ -1236,42 +1237,42 @@ static void fpgen_rm_reg(uint16 w2) { case 0: // Long-Word Integer { - sint32 d = READ_EA_32(ea); + sint32 d = READ_EA_32(state, ea); source = int32_to_floatx80(d); break; } case 1: // Single-precision Real { - uint32 d = READ_EA_32(ea); + uint32 d = READ_EA_32(state, ea); source = float32_to_floatx80(d, &status); break; } case 2: // Extended-precision Real { - source = READ_EA_FPE(ea); + source = READ_EA_FPE(state, ea); break; } case 3: // Packed-decimal Real { - source = READ_EA_PACK(ea); + source = READ_EA_PACK(state, ea); break; } case 4: // Word Integer { - sint16 d = READ_EA_16(ea); + sint16 d = READ_EA_16(state, ea); source = int32_to_floatx80((sint32)d); break; } case 5: // Double-precision Real { - uint64 d = READ_EA_64(ea); + uint64 d = READ_EA_64(state, ea); source = float64_to_floatx80(d, &status); break; } case 6: // Byte Integer { - sint8 d = READ_EA_8(ea); + sint8 d = READ_EA_8(state, ea); source = int32_to_floatx80((sint32)d); break; } @@ -1743,7 +1744,7 @@ static void fpgen_rm_reg(uint16 w2) } } -static void fmove_reg_mem(uint16 w2) +static void fmove_reg_mem(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int src = (w2 >> 7) & 0x7; @@ -1755,25 +1756,25 @@ static void fmove_reg_mem(uint16 w2) case 0: // Long-Word Integer { sint32 d = (sint32)floatx80_to_int32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 1: // Single-precision Real { uint32 d = floatx80_to_float32(REG_FP[src], &status); - WRITE_EA_32(ea, d); + WRITE_EA_32(state, ea, d); break; } case 2: // Extended-precision Real { - WRITE_EA_FPE(ea, REG_FP[src]); + WRITE_EA_FPE(state, ea, REG_FP[src]); break; } case 3: // Packed-decimal Real with Static K-factor { // sign-extend k k = (k & 0x40) ? (k | 0xffffff80) : (k & 0x7f); - WRITE_EA_PACK(ea, k, REG_FP[src]); + WRITE_EA_PACK(state, ea, k, REG_FP[src]); break; } case 4: // Word Integer @@ -1783,7 +1784,7 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_16(ea, (sint16)value); + WRITE_EA_16(state, ea, (sint16) value); break; } case 5: // Double-precision Real @@ -1792,7 +1793,7 @@ static void fmove_reg_mem(uint16 w2) d = floatx80_to_float64(REG_FP[src], &status); - WRITE_EA_64(ea, d); + WRITE_EA_64(state, ea, d); break; } case 6: // Byte Integer @@ -1802,12 +1803,12 @@ static void fmove_reg_mem(uint16 w2) { REG_FPSR |= FPES_OE | FPAE_IOP; } - WRITE_EA_8(ea, (sint8)value); + WRITE_EA_8(state, ea, (sint8) value); break; } case 7: // Packed-decimal Real with Dynamic K-factor { - WRITE_EA_PACK(ea, REG_D[k>>4], REG_FP[src]); + WRITE_EA_PACK(state, ea, REG_D[k >> 4], REG_FP[src]); break; } } @@ -1815,7 +1816,7 @@ static void fmove_reg_mem(uint16 w2) USE_CYCLES(12); } -static void fmove_fpcr(uint16 w2) +static void fmove_fpcr(m68ki_cpu_core *state, uint16 w2) { int ea = REG_IR & 0x3f; int dir = (w2 >> 13) & 0x1; @@ -1852,15 +1853,15 @@ static void fmove_fpcr(uint16 w2) { if (dir) // From system control reg to { - if (regsel & 4) WRITE_EA_32(ea, REG_FPCR); - if (regsel & 2) WRITE_EA_32(ea, REG_FPSR); - if (regsel & 1) WRITE_EA_32(ea, REG_FPIAR); + if (regsel & 4) WRITE_EA_32(state, ea, REG_FPCR); + if (regsel & 2) WRITE_EA_32(state, ea, REG_FPSR); + if (regsel & 1) WRITE_EA_32(state, ea, REG_FPIAR); } else // From to system control reg { - if (regsel & 4) REG_FPCR = READ_EA_32(ea); - if (regsel & 2) REG_FPSR = READ_EA_32(ea); - if (regsel & 1) REG_FPIAR = READ_EA_32(ea); + if (regsel & 4) REG_FPCR = READ_EA_32(state, ea); + if (regsel & 2) REG_FPSR = READ_EA_32(state, ea); + if (regsel & 1) REG_FPIAR = READ_EA_32(state, ea); } } @@ -1915,7 +1916,7 @@ static void fmove_fpcr(uint16 w2) USE_CYCLES(10); } -static void fmovem(uint16 w2) +static void fmovem(m68ki_cpu_core *state, uint16 w2) { int i; int ea = REG_IR & 0x3f; @@ -1957,7 +1958,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[i]); + WRITE_EA_FPE(state, ea, REG_FP[i]); break; } @@ -1981,7 +1982,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - WRITE_EA_FPE(ea, REG_FP[7-i]); + WRITE_EA_FPE(state, ea, REG_FP[7 - i]); break; } @@ -2017,7 +2018,7 @@ static void fmovem(uint16 w2) mem_addr += 12; break; default: - REG_FP[7-i] = READ_EA_FPE(ea); + REG_FP[7-i] = READ_EA_FPE(state, ea); break; } USE_CYCLES(2); @@ -2031,20 +2032,20 @@ static void fmovem(uint16 w2) } } -static void fscc() +static void fscc(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; - int condition = (sint16)(OPER_I_16()); + int condition = (sint16)(OPER_I_16(state)); - WRITE_EA_8(ea, TEST_CONDITION(condition) ? 0xff : 0); + WRITE_EA_8(state, ea, TEST_CONDITION(condition) ? 0xff : 0); USE_CYCLES(7); // ??? } -static void fbcc16(void) +static void fbcc16(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = (sint16)(OPER_I_16()); + offset = (sint16)(OPER_I_16(state)); // TODO: condition and jump!!! if (TEST_CONDITION(condition)) @@ -2056,12 +2057,12 @@ static void fbcc16(void) USE_CYCLES(7); } -static void fbcc32(void) +static void fbcc32(m68ki_cpu_core *state) { sint32 offset; int condition = REG_IR & 0x3f; - offset = OPER_I_32(); + offset = OPER_I_32(state); // TODO: condition and jump!!! if (TEST_CONDITION(condition)) @@ -2074,7 +2075,7 @@ static void fbcc32(void) } -void m68040_fpu_op0() +void m68040_fpu_op0(m68ki_cpu_core *state) { m68ki_cpu.fpu_just_reset = 0; @@ -2082,33 +2083,33 @@ void m68040_fpu_op0() { case 0: { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); switch ((w2 >> 13) & 0x7) { case 0x0: // FPU ALU FP, FP case 0x2: // FPU ALU ea, FP { - fpgen_rm_reg(w2); + fpgen_rm_reg(state, w2); break; } case 0x3: // FMOVE FP, ea { - fmove_reg_mem(w2); + fmove_reg_mem(state, w2); break; } case 0x4: // FMOVEM ea, FPCR case 0x5: // FMOVEM FPCR, ea { - fmove_fpcr(w2); + fmove_fpcr(state, w2); break; } case 0x6: // FMOVEM ea, list case 0x7: // FMOVEM list, ea { - fmovem(w2); + fmovem(state, w2); break; } @@ -2125,7 +2126,7 @@ void m68040_fpu_op0() printf("M68kFPU: unimplemented FDBcc main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); break; default: // FScc (?) - fscc(); + fscc(state); return; } fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (REG_IR >> 6) & 0x3, (REG_IR >> 3) & 0x7, REG_PC-4); @@ -2133,12 +2134,12 @@ void m68040_fpu_op0() } case 2: // FBcc disp16 { - fbcc16(); + fbcc16(state); break; } case 3: // FBcc disp32 { - fbcc32(); + fbcc32(state); break; } @@ -2146,7 +2147,7 @@ void m68040_fpu_op0() } } -static int perform_fsave(uint32 addr, int inc) +static int perform_fsave(m68ki_cpu_core *state, uint32 addr, int inc) { if(m68ki_cpu.cpu_type & CPU_TYPE_040) { @@ -2188,7 +2189,7 @@ static int perform_fsave(uint32 addr, int inc) } // FRESTORE on a NULL frame reboots the FPU - all registers to NaN, the 3 status regs to 0 -static void do_frestore_null(void) +static void do_frestore_null(m68ki_cpu_core *state) { int i; @@ -2206,7 +2207,7 @@ static void do_frestore_null(void) m68ki_cpu.fpu_just_reset = 1; } -void m68040_do_fsave(uint32 addr, int reg, int inc) +void m68040_do_fsave(m68ki_cpu_core *state, uint32 addr, int reg, int inc) { if (m68ki_cpu.fpu_just_reset) { @@ -2215,13 +2216,13 @@ void m68040_do_fsave(uint32 addr, int reg, int inc) else { // we normally generate an IDLE frame - int delta = perform_fsave(addr, inc); + int delta = perform_fsave(state, addr, inc); if(reg != -1) REG_A[reg] += delta; } } -void m68040_do_frestore(uint32 addr, int reg) +void m68040_do_frestore(m68ki_cpu_core *state, uint32 addr, int reg) { uint32 temp = m68ki_read_32(addr); // check for nullptr frame @@ -2254,11 +2255,11 @@ void m68040_do_frestore(uint32 addr, int reg) } else { - do_frestore_null(); + do_frestore_null(state); } } -void m68040_fpu_op1() +void m68040_fpu_op1(m68ki_cpu_core *state) { int ea = REG_IR & 0x3f; int mode = (ea >> 3) & 0x7; @@ -2273,27 +2274,27 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 3: // (An)+ addr = EA_AY_PI_32(); printf("FSAVE mode %d, reg A%d=0x%08x\n",mode,reg,REG_A[reg]); - m68040_do_fsave(addr, -1, 1); // FIXME: -1 was reg + m68040_do_fsave(state, addr, -1, 1); // FIXME: -1 was reg break; case 4: // -(An) addr = EA_AY_PD_32(); - m68040_do_fsave(addr, reg, 0); // FIXME: -1 was reg + m68040_do_fsave(state, addr, reg, 0); // FIXME: -1 was reg break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; case 7: // @@ -2303,13 +2304,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_fsave(addr, -1, 1); + m68040_do_fsave(state, addr, -1, 1); break; } default: @@ -2330,22 +2331,22 @@ void m68040_fpu_op1() { case 2: // (An) addr = REG_A[reg]; - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 3: // (An)+ addr = EA_AY_PI_32(); - m68040_do_frestore(addr, reg); + m68040_do_frestore(state, addr, reg); break; case 5: // (D16, An) addr = EA_AY_DI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 6: // (An) + (Xn) + d8 addr = EA_AY_IX_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; case 7: // @@ -2355,13 +2356,13 @@ void m68040_fpu_op1() case 1: // (abs32) { addr = EA_AL_32(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } case 2: // (d16, PC) { addr = EA_PCDI_16(); - m68040_do_frestore(addr, -1); + m68040_do_frestore(state, addr, -1); break; } default: @@ -2380,9 +2381,9 @@ void m68040_fpu_op1() } } -void m68881_ftrap() +void m68881_ftrap(m68ki_cpu_core *state) { - uint16 w2 = OPER_I_16(); + uint16 w2 = OPER_I_16(state); // now check the condition if (TEST_CONDITION(w2 & 0x3f)) @@ -2395,11 +2396,11 @@ void m68881_ftrap() switch (REG_IR & 0x7) { case 2: // word operand - OPER_I_16(); + OPER_I_16(state); break; case 3: // long word operand - OPER_I_32(); + OPER_I_32(state); break; case 4: // no operand diff --git a/m68kmake.c b/m68kmake.c index 3e5a5c1..b8669ac 100644 --- a/m68kmake.c +++ b/m68kmake.c @@ -880,11 +880,11 @@ void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* rep add_replace_string(replace, ID_OPHANDLER_EA_AY_16, str); sprintf(str, "EA_%s_32()", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_EA_AY_32, str); - sprintf(str, "OPER_%s_8()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_8(state)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_8, str); - sprintf(str, "OPER_%s_16()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_16(state)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_16, str); - sprintf(str, "OPER_%s_32()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_32(state)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_32, str); } diff --git a/m68kmmu.h b/m68kmmu.h index 9085314..d3bd403 100644 --- a/m68kmmu.h +++ b/m68kmmu.h @@ -9,6 +9,9 @@ // MMU status register bit definitions + + +struct m68ki_cpu_core; #if 0 #define MMULOG(A) printf A #else @@ -61,7 +64,7 @@ #define m_side_effects_disabled 0 /* decodes the effective address */ -uint32 DECODE_EA_32(int ea) +uint32 DECODE_EA_32(m68ki_cpu_core *state, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); @@ -93,13 +96,13 @@ uint32 DECODE_EA_32(int ea) { case 0: // (xxx).W { - uint32 ea = OPER_I_16(); + uint32 ea = OPER_I_16(state); return ea; } case 1: // (xxx).L { - uint32 d1 = OPER_I_16(); - uint32 d2 = OPER_I_16(); + uint32 d1 = OPER_I_16(state); + uint32 d2 = OPER_I_16(state); uint32 ea = (d1 << 16) | d2; return ea; } @@ -117,7 +120,7 @@ uint32 DECODE_EA_32(int ea) return 0; } -void pmmu_set_buserror(uint32 addr_in) +void pmmu_set_buserror(m68ki_cpu_core *state, uint32 addr_in) { if (!m_side_effects_disabled && ++m68ki_cpu.mmu_tmp_buserror_occurred == 1) { @@ -130,7 +133,7 @@ void pmmu_set_buserror(uint32 addr_in) // pmmu_atc_add: adds this address to the ATC -void pmmu_atc_add(uint32 logical, uint32 physical, int fc, int rw) +void pmmu_atc_add(m68ki_cpu_core *state, uint32 logical, uint32 physical, int fc, int rw) { // get page size (i.e. # of bits to ignore); is 10 for Apollo int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf; @@ -195,7 +198,7 @@ void pmmu_atc_add(uint32 logical, uint32 physical, int fc, int rw) // pmmu_atc_flush: flush entire ATC // 7fff0003 001ffd10 80f05750 is what should load -void pmmu_atc_flush() +void pmmu_atc_flush(m68ki_cpu_core *state) { MMULOG(("ATC flush: pc=%08x\n", m68ki_cpu.ppc)); // std::fill(std::begin(m68ki_cpu.mmu_atc_tag), std::end(m68ki_cpu.mmu_atc_tag), 0); @@ -206,7 +209,7 @@ void pmmu_atc_flush() int fc_from_modes(uint16 modes); -void pmmu_atc_flush_fc_ea(uint16 modes) +void pmmu_atc_flush_fc_ea(m68ki_cpu_core *state, uint16 modes) { unsigned int fcmask = (modes >> 5) & 7; unsigned int fc = fc_from_modes(modes) & fcmask; @@ -218,7 +221,7 @@ void pmmu_atc_flush_fc_ea(uint16 modes) { case 1: // PFLUSHA MMULOG(("PFLUSHA: mode %d\n", mode)); - pmmu_atc_flush(); + pmmu_atc_flush(state); break; case 4: // flush by fc @@ -236,7 +239,7 @@ void pmmu_atc_flush_fc_ea(uint16 modes) case 6: // flush by fc + ea - ea = DECODE_EA_32(m68ki_cpu.ir); + ea = DECODE_EA_32(state, m68ki_cpu.ir); MMULOG(("flush by fc/ea: fc %d, mask %d, ea %08x\n", fc, fcmask, ea)); for(unsigned int i=0,e;i -uint16 pmmu_atc_lookup(uint32 addr_in, int fc, uint16 rw, - uint32 *addr_out,int ptest) +uint16 pmmu_atc_lookup(m68ki_cpu_core *state, uint32 addr_in, int fc, uint16 rw, uint32 *addr_out, int ptest) { MMULOG(("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d, rw=%d\n", __func__, addr_in, fc, ptest,rw)); unsigned int ps = (m68ki_cpu.mmu_tc >> 20) & 0xf; @@ -318,7 +320,7 @@ uint16 pmmu_atc_lookup(uint32 addr_in, int fc, uint16 rw, return 0; } -uint16 pmmu_match_tt(uint32 addr_in, int fc, uint32 tt, uint16 rw) +uint16 pmmu_match_tt(m68ki_cpu_core *state, uint32 addr_in, int fc, uint32 tt, uint16 rw) { if (!(tt & M68K_MMU_TT_ENABLE)) { @@ -352,7 +354,7 @@ uint16 pmmu_match_tt(uint32 addr_in, int fc, uint32 tt, uint16 rw) return 1; } -void update_descriptor(uint32 tptr, int type, uint32 entry, int16 rw) +void update_descriptor(m68ki_cpu_core *state, uint32 tptr, int type, uint32 entry, int16 rw) { if (type == M68K_MMU_DF_DT_PAGE && !rw && !(entry & M68K_MMU_DF_MODIFIED) && @@ -370,7 +372,7 @@ void update_descriptor(uint32 tptr, int type, uint32 entry, int16 rw) //template -void update_sr(int type, uint32 tbl_entry, int fc,uint16 _long) +void update_sr(m68ki_cpu_core *state, int type, uint32 tbl_entry, int fc, uint16 _long) { if (m_side_effects_disabled) { @@ -411,8 +413,8 @@ void update_sr(int type, uint32 tbl_entry, int fc,uint16 _long) } //template -uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc, - int limit, uint16 rw, uint32 *addr_out, int ptest) +uint16 pmmu_walk_tables(m68ki_cpu_core *state, uint32 addr_in, int type, uint32 table, uint8 fc, int limit, uint16 rw, + uint32 *addr_out, int ptest) { int level = 0; uint32 bits = m68ki_cpu.mmu_tc & 0xffff; @@ -478,10 +480,10 @@ uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc, table = tbl_entry & M68K_MMU_DF_ADDR_MASK; if (!m_side_effects_disabled) { - update_sr(type, tbl_entry, fc,0); + update_sr(state, type, tbl_entry, fc, 0); if (!ptest) { - update_descriptor(*addr_out, type, tbl_entry, rw); + update_descriptor(state, *addr_out, type, tbl_entry, rw); } } break; @@ -507,10 +509,10 @@ uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc, table = tbl_entry2 & M68K_MMU_DF_ADDR_MASK; if (!m_side_effects_disabled) { - update_sr(type, tbl_entry, fc,1); + update_sr(state, type, tbl_entry, fc, 1); if (!ptest) { - update_descriptor(*addr_out, type, tbl_entry, rw); + update_descriptor(state, *addr_out, type, tbl_entry, rw); } } break; @@ -552,7 +554,8 @@ uint16 pmmu_walk_tables(uint32 addr_in, int type, uint32 table, uint8 fc, // pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation //template -uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limit,int ptest,int pload) +uint32 pmmu_translate_addr_with_fc(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint16 rw, int limit, int ptest, + int pload) { uint32 addr_out = 0; @@ -563,8 +566,8 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi m68ki_cpu.mmu_last_logical_addr = addr_in; - if (pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt0, rw) || - pmmu_match_tt(addr_in, fc, m68ki_cpu.mmu_tt1, rw) || + if (pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt0, rw) || + pmmu_match_tt(state, addr_in, fc, m68ki_cpu.mmu_tt1, rw) || fc == 7) { return addr_in; @@ -572,17 +575,17 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi if (ptest && limit == 0) { - pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 1); + pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 1); return addr_out; } - if (!ptest && !pload && pmmu_atc_lookup(addr_in, fc, rw, &addr_out, 0)) + if (!ptest && !pload && pmmu_atc_lookup(state, addr_in, fc, rw, &addr_out, 0)) { if ((m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m68ki_cpu.mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))) { MMULOG(("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_rw, m68ki_cpu.mmu_tmp_fc, m68ki_cpu.mmu_tmp_sz)); - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } return addr_out; } @@ -601,7 +604,7 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi type = m68ki_cpu.mmu_crp_limit & M68K_MMU_DF_DT; } - if (!pmmu_walk_tables(addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest)) + if (!pmmu_walk_tables(state, addr_in, type, tbl_addr, fc, limit, rw, &addr_out, ptest)) { MMULOG(("%s: addr_in=%08x, type=%x, tbl_addr=%x, fc=%d, limit=%x, rw=%x, addr_out=%x, ptest=%d\n", __func__, addr_in, type, tbl_addr, fc, limit, rw, addr_out, ptest)); @@ -620,7 +623,7 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi if (!pload) { MMULOG(("%s: set buserror (SR %04X)\n", __func__, m68ki_cpu.mmu_tmp_sr)); - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } } @@ -629,7 +632,7 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi // between RW and the root type if (!m_side_effects_disabled) { - pmmu_atc_add(addr_in, addr_out, fc, rw && type != 1); + pmmu_atc_add(state, addr_in, addr_out, fc, rw && type != 1); } MMULOG(("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m68ki_cpu.mmu_tmp_sr)); return addr_out; @@ -637,7 +640,7 @@ uint32 pmmu_translate_addr_with_fc(uint32 addr_in, uint8 fc, uint16 rw, int limi // FC bits: 2 = supervisor, 1 = program, 0 = data // the 68040 is a subset of the 68851 and 68030 PMMUs - the page table sizes are fixed, there is no early termination, etc, etc. -uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) +uint32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *state, uint32 addr_in, uint8 fc, uint8 ptest) { uint32 addr_out, tt0, tt1; @@ -675,7 +678,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) MMULOG(("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask)); if ((tt0 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect? { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } return addr_in; @@ -695,7 +698,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) MMULOG(("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask)); if ((tt1 & 4) && !m68ki_cpu.mmu_tmp_rw && !ptest) // write protect? { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } return addr_in; @@ -760,7 +763,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) // write protected by the root or pointer entries? if ((((root_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((pointer_entry & 4) && !m68ki_cpu.mmu_tmp_rw)) && !ptest) { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); return addr_in; } @@ -768,7 +771,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) if (!(pointer_entry & 2) && !ptest) { logerror("Invalid pointer entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in); - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); return addr_in; } @@ -780,7 +783,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) if (!ptest) { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } return addr_in; @@ -819,7 +822,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) // is the page write protected or supervisor protected? if ((((page_entry & 4) && !m68ki_cpu.mmu_tmp_rw) || ((page_entry & 0x80) && !(fc & 4))) && !ptest) { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); return addr_in; } @@ -829,7 +832,7 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) MMULOG(("Invalid page entry! PC=%x, addr=%x\n", m68ki_cpu.ppc, addr_in)); if (!ptest) { - pmmu_set_buserror(addr_in); + pmmu_set_buserror(state, addr_in); } return addr_in; @@ -881,17 +884,17 @@ uint32 pmmu_translate_addr_with_fc_040(uint32 addr_in, uint8 fc, uint8 ptest) } // pmmu_translate_addr: perform 68851/68030-style PMMU address translation -uint32 pmmu_translate_addr(uint32 addr_in, uint16 rw) +uint32 pmmu_translate_addr(m68ki_cpu_core *state, uint32 addr_in, uint16 rw) { uint32 addr_out; if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type)) { - addr_out = pmmu_translate_addr_with_fc_040(addr_in, m68ki_cpu.mmu_tmp_fc, 0); + addr_out = pmmu_translate_addr_with_fc_040(state, addr_in, m68ki_cpu.mmu_tmp_fc, 0); } else { - addr_out = pmmu_translate_addr_with_fc(addr_in, m68ki_cpu.mmu_tmp_fc, rw,7,0,0); + addr_out = pmmu_translate_addr_with_fc(state, addr_in, m68ki_cpu.mmu_tmp_fc, rw, 7, 0, 0); MMULOG(("ADDRIN %08X, ADDROUT %08X\n", addr_in, addr_out)); } return addr_out; @@ -940,9 +943,9 @@ int fc_from_modes(uint16 modes) return 0; } -void m68851_pload(uint32 ea, uint16 modes) +void m68851_pload(m68ki_cpu_core *state, uint32 ea, uint16 modes) { - uint32 ltmp = DECODE_EA_32(ea); + uint32 ltmp = DECODE_EA_32(state, ea); int fc = fc_from_modes(modes); uint16 rw = !!(modes & 0x200); @@ -953,11 +956,11 @@ void m68851_pload(uint32 ea, uint16 modes) { if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type)) { - pmmu_translate_addr_with_fc_040(ltmp, fc, 0); + pmmu_translate_addr_with_fc_040(state, ltmp, fc, 0); } else { - pmmu_translate_addr_with_fc(ltmp, fc, rw , 7, 0, 1); + pmmu_translate_addr_with_fc(state, ltmp, fc, rw, 7, 0, 1); } } else @@ -968,9 +971,9 @@ void m68851_pload(uint32 ea, uint16 modes) } } -void m68851_ptest(uint32 ea, uint16 modes) +void m68851_ptest(m68ki_cpu_core *state, uint32 ea, uint16 modes) { - uint32 v_addr = DECODE_EA_32(ea); + uint32 v_addr = DECODE_EA_32(state, ea); uint32 p_addr; int level = (modes >> 10) & 7; @@ -983,11 +986,11 @@ void m68851_ptest(uint32 ea, uint16 modes) if (CPU_TYPE_IS_040_PLUS(m68ki_cpu.cpu_type)) { - p_addr = pmmu_translate_addr_with_fc_040(v_addr, fc, 1); + p_addr = pmmu_translate_addr_with_fc_040(state, v_addr, fc, 1); } else { - p_addr = pmmu_translate_addr_with_fc(v_addr, fc, rw, level, 1, 0); + p_addr = pmmu_translate_addr_with_fc(state, v_addr, fc, rw, level, 1, 0); } m68ki_cpu.mmu_sr = m68ki_cpu.mmu_tmp_sr; @@ -996,34 +999,34 @@ void m68851_ptest(uint32 ea, uint16 modes) if (modes & 0x100) { int areg = (modes >> 5) & 7; - WRITE_EA_32(0x08 | areg, p_addr); + WRITE_EA_32(state, 0x08 | areg, p_addr); } } -void m68851_pmove_get(uint32 ea, uint16 modes) +void m68851_pmove_get(m68ki_cpu_core *state, uint32 ea, uint16 modes) { switch ((modes>>10) & 0x3f) { case 0x02: // transparent translation register 0 - WRITE_EA_32(ea, m68ki_cpu.mmu_tt0); + WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt0); MMULOG(("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt0)); break; case 0x03: // transparent translation register 1 - WRITE_EA_32(ea, m68ki_cpu.mmu_tt1); + WRITE_EA_32(state, ea, m68ki_cpu.mmu_tt1); MMULOG(("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tt1)); break; case 0x10: // translation control register - WRITE_EA_32(ea, m68ki_cpu.mmu_tc); + WRITE_EA_32(state, ea, m68ki_cpu.mmu_tc); MMULOG(("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_tc)); break; case 0x12: // supervisor root pointer - WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr); + WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr); MMULOG(("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr)); break; case 0x13: // CPU root pointer - WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr); + WRITE_EA_64(state, ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr); MMULOG(("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", m68ki_cpu.ppc, m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr)); break; @@ -1034,19 +1037,19 @@ void m68851_pmove_get(uint32 ea, uint16 modes) if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP, TT with FD bit clear { - pmmu_atc_flush(); + pmmu_atc_flush(state); } } -void m68851_pmove_put(uint32 ea, uint16 modes) +void m68851_pmove_put(m68ki_cpu_core *state, uint32 ea, uint16 modes) { uint64 temp64; switch ((modes>>13) & 7) { case 0: { - uint32 temp = READ_EA_32(ea); + uint32 temp = READ_EA_32(state, ea); if (((modes >> 10) & 7) == 2) { @@ -1063,7 +1066,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) // FIXME: unreachable if (!(modes & 0x100)) { - pmmu_atc_flush(); + pmmu_atc_flush(state); } } /* fall through */ @@ -1077,7 +1080,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) switch ((modes >> 10) & 7) { case 0: // translation control register - m68ki_cpu.mmu_tc = READ_EA_32(ea); + m68ki_cpu.mmu_tc = READ_EA_32(state, ea); MMULOG(("PMMU: TC = %08x\n", m68ki_cpu.mmu_tc)); if (m68ki_cpu.mmu_tc & 0x80000000) @@ -1106,12 +1109,12 @@ void m68851_pmove_put(uint32 ea, uint16 modes) if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear { - pmmu_atc_flush(); + pmmu_atc_flush(state); } break; case 2: // supervisor root pointer - temp64 = READ_EA_64(ea); + temp64 = READ_EA_64(state, ea); m68ki_cpu.mmu_srp_limit = (temp64 >> 32) & 0xffffffff; m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff; MMULOG(("PMMU: SRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_srp_limit, m68ki_cpu.mmu_srp_aptr)); @@ -1124,12 +1127,12 @@ void m68851_pmove_put(uint32 ea, uint16 modes) if (!(modes & 0x100)) { - pmmu_atc_flush(); + pmmu_atc_flush(state); } break; case 3: // CPU root pointer - temp64 = READ_EA_64(ea); + temp64 = READ_EA_64(state, ea); m68ki_cpu.mmu_crp_limit = (temp64 >> 32) & 0xffffffff; m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff; MMULOG(("PMMU: CRP limit = %08x aptr = %08x\n", m68ki_cpu.mmu_crp_limit, m68ki_cpu.mmu_crp_aptr)); @@ -1142,7 +1145,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) if (!(modes & 0x100)) { - pmmu_atc_flush(); + pmmu_atc_flush(state); } break; @@ -1150,7 +1153,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) if (m68ki_cpu.cpu_type == CPU_TYPE_020) { // DomainOS on Apollo DN3000 will only reset this to 0 - uint16 mmu_ac = READ_EA_16(ea); + uint16 mmu_ac = READ_EA_16(state, ea); if (mmu_ac != 0) { MMULOG(("680x0 PMMU: pc=%x PMOVE to mmu_ac=%08x\n", @@ -1168,7 +1171,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) break; case 3: // MMU status { - uint32 temp = READ_EA_32(ea); + uint32 temp = READ_EA_32(state, ea); logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68ki_cpu.pc); } break; @@ -1176,7 +1179,7 @@ void m68851_pmove_put(uint32 ea, uint16 modes) } -void m68851_pmove(uint32 ea, uint16 modes) +void m68851_pmove(m68ki_cpu_core *state, uint32 ea, uint16 modes) { switch ((modes>>13) & 0x7) { @@ -1184,23 +1187,23 @@ void m68851_pmove(uint32 ea, uint16 modes) case 2: // MC68851 form, FD never set if (modes & 0x200) { - m68851_pmove_get(ea, modes); + m68851_pmove_get(state, ea, modes); break; } else // top 3 bits of modes: 010 for this, 011 for status, 000 for transparent translation regs { - m68851_pmove_put(ea, modes); + m68851_pmove_put(state, ea, modes); break; } case 3: // MC68030 to/from status reg if (modes & 0x200) { MMULOG(("%s: read SR = %04x\n", __func__, m68ki_cpu.mmu_sr)); - WRITE_EA_16(ea, m68ki_cpu.mmu_sr); + WRITE_EA_16(state, ea, m68ki_cpu.mmu_sr); } else { - m68ki_cpu.mmu_sr = READ_EA_16(ea); + m68ki_cpu.mmu_sr = READ_EA_16(state, ea); MMULOG(("%s: write SR = %04X\n", __func__, m68ki_cpu.mmu_sr)); } break; @@ -1213,7 +1216,7 @@ void m68851_pmove(uint32 ea, uint16 modes) } -void m68851_mmu_ops() +void m68851_mmu_ops(m68ki_cpu_core *state) { uint16 modes; uint32 ea = m68ki_cpu.ir & 0x3f; @@ -1232,28 +1235,28 @@ void m68851_mmu_ops() else if ((m68ki_cpu.ir & 0xffe0) == 0xf500) { MMULOG(("68040 pflush: pc=%08x ir=%04x opmode=%d register=%d\n", REG_PC-4, m68ki_cpu.ir, (m68ki_cpu.ir >> 3) & 3, m68ki_cpu.ir & 7)); - pmmu_atc_flush(); + pmmu_atc_flush(state); } else // the rest are 1111000xxxXXXXXX where xxx is the instruction family { switch ((m68ki_cpu.ir>>9) & 0x7) { case 0: - modes = OPER_I_16(); + modes = OPER_I_16(state); if ((modes & 0xfde0) == 0x2000) // PLOAD { - m68851_pload(ea, modes); + m68851_pload(state, ea, modes); return; } else if ((modes & 0xe200) == 0x2000) // PFLUSH { - pmmu_atc_flush_fc_ea(modes); + pmmu_atc_flush_fc_ea(state, modes); return; } else if (modes == 0xa000) // PFLUSHR { - pmmu_atc_flush(); + pmmu_atc_flush(state); return; } else if (modes == 0x2800) // PVALID (FORMAT 1) @@ -1268,12 +1271,12 @@ void m68851_mmu_ops() } else if ((modes & 0xe000) == 0x8000) // PTEST { - m68851_ptest(ea, modes); + m68851_ptest(state, ea, modes); return; } else { - m68851_pmove(ea, modes); + m68851_pmove(state, ea, modes); } break;