2 * copyright (c) 2010 Sveriges Television AB <info@casparcg.com>
\r
4 * This file is part of CasparCG.
\r
6 * CasparCG is free software: you can redistribute it and/or modify
\r
7 * it under the terms of the GNU General Public License as published by
\r
8 * the Free Software Foundation, either version 3 of the License, or
\r
9 * (at your option) any later version.
\r
11 * CasparCG is distributed in the hope that it will be useful,
\r
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 * GNU General Public License for more details.
\r
16 * You should have received a copy of the GNU General Public License
\r
17 * along with CasparCG. If not, see <http://www.gnu.org/licenses/>.
\r
21 #include "../stdafx.h"
\r
29 namespace caspar { namespace common {
\r
32 FPU(0), VME(0), DE(0), PSE(0), TSC(0), MSR(0), PAE(0), MCE(0), CX8(0), APIC(0), SEP(0), MTRR(0),
\r
33 PGE(0), MCA(0), CMOV(0), PAT(0), PSE_36(0), PSN(0), CLFSH(0), DS(0), ACPI(0), MMX(0), FXSR(0),
\r
34 SSE(0), SSE2(0),SSE3(0),SSSE3(0), SSE4_1(0), SSE4_2(0), SSE5(0), SS(0), HTT(0), TM(0),
\r
35 IA_64(0),Family(0), Model(0), ModelEx(0), Stepping(0), FamilyEx(0), Brand(0), Type(0)
\r
37 int CPUInfo[4] = {-1};
\r
38 __cpuid(CPUInfo, 0);
\r
40 int nIds = CPUInfo[0];
\r
42 ID.append(reinterpret_cast<char*>(&CPUInfo[1]), 4);
\r
43 ID.append(reinterpret_cast<char*>(&CPUInfo[3]), 4);
\r
44 ID.append(reinterpret_cast<char*>(&CPUInfo[2]), 4);
\r
46 for (int i = 0; i <= nIds; ++i)
\r
48 __cpuid(CPUInfo, i);
\r
52 Stepping = (CPUInfo[0] ) & 0x0F;
\r
53 Model = (CPUInfo[0] >> 4 ) & 0x0F;
\r
54 Family = (CPUInfo[0] >> 8 ) & 0x0F;
\r
55 Type = (CPUInfo[0] >> 12) & 0x03;
\r
56 ModelEx = (CPUInfo[0] >> 16) & 0x0F;
\r
57 FamilyEx = (CPUInfo[0] >> 20) & 0xFF;
\r
58 Brand = (CPUInfo[1] ) & 0xFF;
\r
60 if(ID == "GenuineIntel")
\r
62 FPU = (CPUInfo[3] & (1 << 0)) != 0;
\r
63 VME = (CPUInfo[3] & (1 << 1)) != 0;
\r
64 DE = (CPUInfo[3] & (1 << 2)) != 0;
\r
65 PSE = (CPUInfo[3] & (1 << 3)) != 0;
\r
66 TSC = (CPUInfo[3] & (1 << 4)) != 0;
\r
67 MSR = (CPUInfo[3] & (1 << 5)) != 0;
\r
68 PAE = (CPUInfo[3] & (1 << 6)) != 0;
\r
69 MCE = (CPUInfo[3] & (1 << 7)) != 0;
\r
70 CX8 = (CPUInfo[3] & (1 << 8)) != 0;
\r
71 APIC = (CPUInfo[3] & (1 << 9)) != 0;
\r
72 // = (CPUInfo[3] & (1 << 10)) != 0;
\r
73 SEP = (CPUInfo[3] & (1 << 11)) != 0;
\r
74 MTRR = (CPUInfo[3] & (1 << 12)) != 0;
\r
75 PGE = (CPUInfo[3] & (1 << 13)) != 0;
\r
76 MCA = (CPUInfo[3] & (1 << 14)) != 0;
\r
77 CMOV = (CPUInfo[3] & (1 << 15)) != 0;
\r
78 PAT = (CPUInfo[3] & (1 << 16)) != 0;
\r
79 PSE_36 = (CPUInfo[3] & (1 << 17)) != 0;
\r
80 PSN = (CPUInfo[3] & (1 << 18)) != 0;
\r
81 CLFSH = (CPUInfo[3] & (1 << 19)) != 0;
\r
82 // = (CPUInfo[3] & (1 << 20)) != 0;
\r
83 DS = (CPUInfo[3] & (1 << 21)) != 0;
\r
84 ACPI = (CPUInfo[3] & (1 << 22)) != 0;
\r
85 MMX = (CPUInfo[3] & (1 << 23)) != 0;
\r
86 FXSR = (CPUInfo[3] & (1 << 24)) != 0;
\r
87 SSE = (CPUInfo[3] & (1 << 25)) != 0;
\r
88 SSE2 = (CPUInfo[3] & (1 << 26)) != 0;
\r
89 SS = (CPUInfo[3] & (1 << 27)) != 0;
\r
90 HTT = (CPUInfo[3] & (1 << 28)) != 0;
\r
91 TM = (CPUInfo[3] & (1 << 29)) != 0;
\r
92 // = (CPUInfo[3] & (1 << 30)) != 0;
\r
93 IA_64 = (CPUInfo[3] & (1 << 31)) != 0;
\r
95 SSE3 = (CPUInfo[2] & (1 << 0)) != 0;
\r
96 SSSE3 = (CPUInfo[2] & (1 << 9)) != 0;
\r
97 SSE4_1 = (CPUInfo[2] & (1 << 19)) != 0;
\r
98 SSE4_2 = (CPUInfo[2] & (1 << 20)) != 0;
\r
100 else if(ID == "AuthenticAMD")
\r
107 SIMD = common::SSE5;
\r
109 SIMD = common::SSE4_2;
\r
111 SIMD = common::SSE4_1;
\r
113 SIMD = common::SSSE3;
\r
115 SIMD = common::SSE3;
\r
117 SIMD = common::SSE2;
\r
119 SIMD = common::SSE;
\r
121 SIMD = common::REF;
\r