1 // Copyright (c) 2008 Google Inc. All rights reserved.
3 // Redistribution and use in source and binary forms, with or without
4 // modification, are permitted provided that the following conditions are
7 // * Redistributions of source code must retain the above copyright
8 // notice, this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above
10 // copyright notice, this list of conditions and the following disclaimer
11 // in the documentation and/or other materials provided with the
13 // * Neither the name of Google Inc. nor the name Chromium Embedded
14 // Framework nor the names of its contributors may be used to endorse
15 // or promote products derived from this software without specific prior
16 // written permission.
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 // Do not include this header file directly. Use base/cef_atomicops.h
33 #ifndef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_
34 #define CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_
40 #include "include/base/cef_macros.h"
42 #if defined(ARCH_CPU_64_BITS)
43 // windows.h #defines this (only on x64). This causes problems because the
44 // public API also uses MemoryBarrier at the public name for this fence. So, on
45 // X64, undef it, and call its documented
46 // (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx)
47 // implementation directly.
54 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
57 LONG result = _InterlockedCompareExchange(
58 reinterpret_cast<volatile LONG*>(ptr),
59 static_cast<LONG>(new_value),
60 static_cast<LONG>(old_value));
61 return static_cast<Atomic32>(result);
64 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
66 LONG result = _InterlockedExchange(
67 reinterpret_cast<volatile LONG*>(ptr),
68 static_cast<LONG>(new_value));
69 return static_cast<Atomic32>(result);
72 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
74 return _InterlockedExchangeAdd(
75 reinterpret_cast<volatile LONG*>(ptr),
76 static_cast<LONG>(increment)) + increment;
79 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
81 return Barrier_AtomicIncrement(ptr, increment);
84 #if !(defined(_MSC_VER) && _MSC_VER >= 1400)
85 #error "We require at least vs2005 for MemoryBarrier"
87 inline void MemoryBarrier() {
88 #if defined(ARCH_CPU_64_BITS)
89 // See #undef and note at the top of this file.
92 // We use MemoryBarrier from WinNT.h
97 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
100 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
103 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
105 Atomic32 new_value) {
106 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
109 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
113 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
114 NoBarrier_AtomicExchange(ptr, value);
115 // acts as a barrier in this implementation
118 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
119 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
120 // See comments in Atomic64 version of Release_Store() below.
123 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
127 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
128 Atomic32 value = *ptr;
132 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
139 // 64-bit low-level operations on 64-bit platform.
141 COMPILE_ASSERT(sizeof(Atomic64) == sizeof(PVOID), atomic_word_is_atomic);
143 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
145 Atomic64 new_value) {
146 PVOID result = InterlockedCompareExchangePointer(
147 reinterpret_cast<volatile PVOID*>(ptr),
148 reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value));
149 return reinterpret_cast<Atomic64>(result);
152 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
153 Atomic64 new_value) {
154 PVOID result = InterlockedExchangePointer(
155 reinterpret_cast<volatile PVOID*>(ptr),
156 reinterpret_cast<PVOID>(new_value));
157 return reinterpret_cast<Atomic64>(result);
160 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
161 Atomic64 increment) {
162 return InterlockedExchangeAdd64(
163 reinterpret_cast<volatile LONGLONG*>(ptr),
164 static_cast<LONGLONG>(increment)) + increment;
167 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
168 Atomic64 increment) {
169 return Barrier_AtomicIncrement(ptr, increment);
172 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
176 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
177 NoBarrier_AtomicExchange(ptr, value);
178 // acts as a barrier in this implementation
181 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
182 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
184 // When new chips come out, check:
185 // IA-32 Intel Architecture Software Developer's Manual, Volume 3:
186 // System Programming Guide, Chatper 7: Multiple-processor management,
187 // Section 7.2, Memory Ordering.
189 // http://developer.intel.com/design/pentium4/manuals/index_new.htm
192 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
196 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
197 Atomic64 value = *ptr;
201 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
206 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
208 Atomic64 new_value) {
209 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
212 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
214 Atomic64 new_value) {
215 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
219 #endif // defined(_WIN64)
221 } // namespace base::subtle
224 #endif // CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_MSVC_H_