2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
26 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
27 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
28 #define BCM2708_PERI_BASE 0x3F000000 // pi3
29 #define BCM2708_PERI_SIZE 0x01000000
30 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
31 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
32 #define GPIO_ADDR 0x200000 /* GPIO controller */
33 #define GPCLK_ADDR 0x101000
34 #define CLK_PASSWD 0x5a000000
35 #define CLK_GP0_CTL 0x070
36 #define CLK_GP0_DIV 0x074
42 #define STATUSREGADDR \
43 GPIO_CLR = 1 << SA0; \
44 GPIO_CLR = 1 << SA1; \
47 GPIO_CLR = 1 << SA0; \
48 GPIO_CLR = 1 << SA1; \
51 GPIO_SET = 1 << SA0; \
52 GPIO_CLR = 1 << SA1; \
55 GPIO_CLR = 1 << SA0; \
56 GPIO_SET = 1 << SA1; \
59 GPIO_SET = 1 << SA0; \
60 GPIO_SET = 1 << SA1; \
63 #define PAGE_SIZE (4 * 1024)
64 #define BLOCK_SIZE (4 * 1024)
66 #define GPIOSET(no, ishigh) \
71 reset |= (1 << (no)); \
74 int fast_base_configured;
75 unsigned int fast_base;
76 #define FAST_SIZE (256 * 1024 * 1024)
78 #define GAYLEBASE 0xD80000
79 #define GAYLESIZE (448 * 1024)
81 #define KICKBASE 0xF80000
82 #define KICKSIZE (512 * 1024)
86 int gayle_emulation_enabled = 1;
91 volatile unsigned int *gpio;
92 volatile unsigned int *gpclk;
93 volatile unsigned int gpfsel0;
94 volatile unsigned int gpfsel1;
95 volatile unsigned int gpfsel2;
96 volatile unsigned int gpfsel0_o;
97 volatile unsigned int gpfsel1_o;
98 volatile unsigned int gpfsel2_o;
100 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
102 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
103 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
104 #define SET_GPIO_ALT(g, a) \
105 *(gpio + (((g) / 10))) |= \
106 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
109 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
111 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
113 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
115 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
116 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
120 uint32_t read8(uint32_t address);
121 void write8(uint32_t address, uint32_t data);
123 uint32_t read16(uint32_t address);
124 void write16(uint32_t address, uint32_t data);
126 void write32(uint32_t address, uint32_t data);
127 uint32_t read32(uint32_t address);
129 uint16_t read_reg(void);
130 void write_reg(unsigned int value);
132 volatile uint16_t srdata;
133 volatile uint32_t srdata2;
134 volatile uint32_t srdata2_old;
136 unsigned char g_kick[KICKSIZE];
137 unsigned char fast_ram_array[FAST_SIZE]; /* RAM */
138 unsigned char toggle;
139 static volatile unsigned char ovl;
140 static volatile unsigned char maprom;
142 void sigint_handler(int sig_num) {
143 printf("\n Exit Ctrl+C %d\n", sig_num);
147 void *iplThread(void *args) {
148 printf("IPL thread running/n");
151 if (GET_GPIO(1) == 0) {
153 m68k_end_timeslice();
154 //printf("thread!/n");
162 int main(int argc, char *argv[]) {
164 const struct sched_param priority = {99};
166 // Some command line switch stuffles
167 for (g = 1; g < argc; g++) {
168 if (strcmp(argv[g], "--disable-gayle") == 0) {
169 gayle_emulation_enabled = 0;
173 sched_setscheduler(0, SCHED_FIFO, &priority);
174 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
178 signal(SIGINT, sigint_handler);
181 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
183 printf("Enable 200MHz GPCLK0 on GPIO4\n");
185 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
187 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
190 *(gpclk + (CLK_GP0_DIV / 4)) =
191 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
193 *(gpclk + (CLK_GP0_CTL / 4)) =
194 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
196 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
200 SET_GPIO_ALT(4, 0); // gpclk0
210 // set gpio0 (aux0) and gpio1 (aux1) to input
214 // Set GPIO pins 6,7 and 8-23 to output
215 for (g = 6; g <= 23; g++) {
219 printf("Precalculate GPIO8-23 as Output\n");
220 gpfsel0_o = *(gpio); // store gpio ddr
221 printf("gpfsel0: %#x\n", gpfsel0_o);
222 gpfsel1_o = *(gpio + 1); // store gpio ddr
223 printf("gpfsel1: %#x\n", gpfsel1_o);
224 gpfsel2_o = *(gpio + 2); // store gpio ddr
225 printf("gpfsel2: %#x\n", gpfsel2_o);
227 // Set GPIO pins 8-23 to input
228 for (g = 8; g <= 23; g++) {
231 printf("Precalculate GPIO8-23 as Input\n");
232 gpfsel0 = *(gpio); // store gpio ddr
233 printf("gpfsel0: %#x\n", gpfsel0);
234 gpfsel1 = *(gpio + 1); // store gpio ddr
235 printf("gpfsel1: %#x\n", gpfsel1);
236 gpfsel2 = *(gpio + 2); // store gpio ddr
237 printf("gpfsel2: %#x\n", gpfsel2);
246 // reset cpld statemachine first
254 // load kick.rom if present
257 fd = open("kick.rom", O_RDONLY);
259 printf("Failed loading kick.rom, using motherboard kickstart\n");
262 int size = (int)lseek(fd, 0, SEEK_END);
263 if (size == 0x40000) {
264 lseek(fd, 0, SEEK_SET);
265 read(fd, &g_kick, size);
266 lseek(fd, 0, SEEK_SET);
267 read(fd, &g_kick[0x40000], size);
269 lseek(fd, 0, SEEK_SET);
270 read(fd, &g_kick, size);
272 printf("Loaded kick.rom with size %d kib\n", size / 1024);
275 // reset amiga and statemachine
278 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
279 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
284 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
288 m68k_set_reg(M68K_REG_PC, 0xF80002);
290 m68k_set_reg(M68K_REG_PC, 0x0);
296 err = pthread_create(&id, NULL, &iplThread, NULL);
298 printf("\ncan't create IPL thread :[%s]", strerror(err));
300 printf("\n IPL Thread created successfully\n");
309 m68k_set_irq((srdata >> 13) & 0xff);
316 if (GET_GPIO(1) == 0) {
318 m68k_set_irq((srdata >> 13) & 0xff);
320 if (CheckIrq() == 1) {
321 write16(0xdff09c, 0x8008);
331 void cpu_pulse_reset(void) {
333 // printf("Status Reg%x\n",read_reg());
336 // printf("Status Reg%x\n",read_reg());
339 int cpu_irq_ack(int level) {
340 printf("cpu irq ack\n");
344 unsigned int m68k_read_memory_8(unsigned int address) {
345 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
346 return fast_ram_array[address - fast_base];
350 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
351 return g_kick[address - KICKBASE];
355 if (gayle_emulation_enabled) {
356 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
357 return readGayleB(address);
362 // if (address < 0xffffff) {
363 return read8((uint32_t)address);
369 unsigned int m68k_read_memory_16(unsigned int address) {
370 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
371 return be16toh(*(uint16_t *)&fast_ram_array[address - fast_base]);
375 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
376 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
380 if (gayle_emulation_enabled) {
381 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
382 return readGayle(address);
386 // if (address < 0xffffff) {
388 return (unsigned int)read16((uint32_t)address);
394 unsigned int m68k_read_memory_32(unsigned int address) {
395 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
396 return be32toh(*(uint32_t *)&fast_ram_array[address - fast_base]);
400 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
401 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
405 if (gayle_emulation_enabled) {
406 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
407 return readGayleL(address);
411 // if (address < 0xffffff) {
413 uint16_t a = read16(address);
414 uint16_t b = read16(address + 2);
415 return (a << 16) | b;
421 void m68k_write_memory_8(unsigned int address, unsigned int value) {
422 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
423 fast_ram_array[address - fast_base] = value;
427 if (gayle_emulation_enabled) {
428 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
429 writeGayleB(address, value);
434 if (address == 0xbfe001) {
435 ovl = (value & (1 << 0));
436 printf("OVL:%x\n", ovl);
439 // if (address < 0xffffff) {
441 write8((uint32_t)address, value);
448 void m68k_write_memory_16(unsigned int address, unsigned int value) {
449 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
450 *(uint16_t *)&fast_ram_array[address - fast_base] = htobe16(value);
454 if (gayle_emulation_enabled) {
455 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
456 writeGayle(address, value);
461 // if (address < 0xffffff) {
463 write16((uint32_t)address, value);
469 void m68k_write_memory_32(unsigned int address, unsigned int value) {
470 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
471 *(uint32_t *)&fast_ram_array[address - fast_base] = htobe32(value);
475 if (gayle_emulation_enabled) {
476 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
477 writeGayleL(address, value);
481 // if (address < 0xffffff) {
483 write16(address, value >> 16);
484 write16(address + 2, value);
491 void write16(uint32_t address, uint32_t data) {
492 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
493 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
494 uint32_t addr_l_s = (address >> 16) << 8;
495 uint32_t addr_l_r = (~address >> 16) << 8;
496 uint32_t data_s = (data & 0x0000ffff) << 8;
497 uint32_t data_r = (~data & 0x0000ffff) << 8;
499 // asm volatile ("dmb" ::: "memory");
502 *(gpio + 1) = gpfsel1_o;
503 *(gpio + 2) = gpfsel2_o;
505 *(gpio + 7) = addr_h_s;
506 *(gpio + 10) = addr_h_r;
510 *(gpio + 7) = addr_l_s;
511 *(gpio + 10) = addr_l_r;
516 *(gpio + 7) = data_s;
517 *(gpio + 10) = data_r;
522 *(gpio + 1) = gpfsel1;
523 *(gpio + 2) = gpfsel2;
524 while ((GET_GPIO(0)))
526 // asm volatile ("dmb" ::: "memory");
529 void write8(uint32_t address, uint32_t data) {
530 if ((address & 1) == 0)
531 data = data + (data << 8); // EVEN, A0=0,UDS
533 data = data & 0xff; // ODD , A0=1,LDS
534 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
535 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
536 uint32_t addr_l_s = (address >> 16) << 8;
537 uint32_t addr_l_r = (~address >> 16) << 8;
538 uint32_t data_s = (data & 0x0000ffff) << 8;
539 uint32_t data_r = (~data & 0x0000ffff) << 8;
541 // asm volatile ("dmb" ::: "memory");
544 *(gpio + 1) = gpfsel1_o;
545 *(gpio + 2) = gpfsel2_o;
547 *(gpio + 7) = addr_h_s;
548 *(gpio + 10) = addr_h_r;
552 *(gpio + 7) = addr_l_s;
553 *(gpio + 10) = addr_l_r;
558 *(gpio + 7) = data_s;
559 *(gpio + 10) = data_r;
564 *(gpio + 1) = gpfsel1;
565 *(gpio + 2) = gpfsel2;
566 while ((GET_GPIO(0)))
568 // asm volatile ("dmb" ::: "memory");
571 uint32_t read16(uint32_t address) {
573 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
574 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
575 uint32_t addr_l_s = (address >> 16) << 8;
576 uint32_t addr_l_r = (~address >> 16) << 8;
578 // asm volatile ("dmb" ::: "memory");
581 *(gpio + 1) = gpfsel1_o;
582 *(gpio + 2) = gpfsel2_o;
584 *(gpio + 7) = addr_h_s;
585 *(gpio + 10) = addr_h_r;
589 *(gpio + 7) = addr_l_s;
590 *(gpio + 10) = addr_l_r;
596 *(gpio + 1) = gpfsel1;
597 *(gpio + 2) = gpfsel2;
599 while (!(GET_GPIO(0)))
604 // asm volatile ("dmb" ::: "memory");
605 return (val >> 8) & 0xffff;
608 uint32_t read8(uint32_t address) {
610 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
611 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
612 uint32_t addr_l_s = (address >> 16) << 8;
613 uint32_t addr_l_r = (~address >> 16) << 8;
615 // asm volatile ("dmb" ::: "memory");
618 *(gpio + 1) = gpfsel1_o;
619 *(gpio + 2) = gpfsel2_o;
621 *(gpio + 7) = addr_h_s;
622 *(gpio + 10) = addr_h_r;
626 *(gpio + 7) = addr_l_s;
627 *(gpio + 10) = addr_l_r;
633 *(gpio + 1) = gpfsel1;
634 *(gpio + 2) = gpfsel2;
637 while (!(GET_GPIO(0)))
642 // asm volatile ("dmb" ::: "memory");
644 val = (val >> 8) & 0xffff;
645 if ((address & 1) == 0)
646 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
648 return val & 0xff; // ODD , A0=1,LDS
651 /******************************************************/
653 void write_reg(unsigned int value) {
656 *(gpio + 1) = gpfsel1_o;
657 *(gpio + 2) = gpfsel2_o;
658 *(gpio + 7) = (value & 0xffff) << 8;
659 *(gpio + 10) = (~value & 0xffff) << 8;
661 GPIO_CLR = 1 << 7; // delay
666 *(gpio + 1) = gpfsel1;
667 *(gpio + 2) = gpfsel2;
670 uint16_t read_reg(void) {
675 *(gpio + 1) = gpfsel1;
676 *(gpio + 2) = gpfsel2;
678 GPIO_CLR = 1 << 6; // delay
683 return (uint16_t)(val >> 8);
687 // Set up a memory regions to access GPIO
691 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
692 printf("can't open /dev/mem \n");
698 NULL, // Any adddress in our space will do
699 BCM2708_PERI_SIZE, // Map length
700 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
701 MAP_SHARED, // Shared with other processes
702 mem_fd, // File to map
703 BCM2708_PERI_BASE // Offset to GPIO peripheral
706 close(mem_fd); // No need to keep mem_fd open after mmap
708 if (gpio_map == MAP_FAILED) {
709 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
713 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
714 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;