20 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
21 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
22 #define BCM2708_PERI_BASE 0x3F000000 //pi3
23 #define BCM2708_PERI_SIZE 0x01000000
24 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
25 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
26 #define GPIO_ADDR 0x200000 /* GPIO controller */
27 #define GPCLK_ADDR 0x101000
28 #define CLK_PASSWD 0x5a000000
29 #define CLK_GP0_CTL 0x070
30 #define CLK_GP0_DIV 0x074
36 #define STATUSREGADDR GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_SET = 1<<SA2;
37 #define W16 GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
38 #define R16 GPIO_SET = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
39 #define W8 GPIO_CLR = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
40 #define R8 GPIO_SET = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
42 #define PAGE_SIZE (4*1024)
43 #define BLOCK_SIZE (4*1024)
45 #define GPIOSET(no, ishigh) \
50 reset |= (1 << (no)); \
54 #define FASTBASE 0x07FFFFFF
55 //#define FASTSIZE 0xFFFFFF
56 #define FASTSIZE 0xFFFFFFF
59 #define GAYLEBASE 0xD80000 //D7FFFF
60 #define GAYLESIZE 0x6FFFF
68 volatile unsigned int *gpio;
69 volatile unsigned int *gpclk;
70 volatile unsigned int gpfsel0;
71 volatile unsigned int gpfsel1;
72 volatile unsigned int gpfsel2;
73 volatile unsigned int gpfsel0_o;
74 volatile unsigned int gpfsel1_o;
75 volatile unsigned int gpfsel2_o;
77 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y)
78 #define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
79 #define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3))
80 #define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
82 #define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0
83 #define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0
85 #define GET_GPIO(g) (*(gpio+13)&(1<<g)) // 0 if LOW, (1<<g) if HIGH
87 #define GPIO_PULL *(gpio+37) // Pull up/pull down
88 #define GPIO_PULLCLK0 *(gpio+38) // Pull up/pull down clock
93 uint32_t read8(uint32_t address);
94 void write8(uint32_t address, uint32_t data);
96 uint32_t read16(uint32_t address);
97 void write16(uint32_t address, uint32_t data);
99 void write32(uint32_t address, uint32_t data);
100 uint32_t read32(uint32_t address);
102 uint16_t read_reg(void);
103 void write_reg(unsigned int value);
105 volatile uint16_t srdata;
106 volatile uint32_t srdata2;
107 volatile uint32_t srdata2_old;
110 unsigned char g_kick[524288];
111 unsigned char g_ram[FASTSIZE+1]; /* RAM */
112 unsigned char toggle;
113 static volatile unsigned char ovl;
114 static volatile unsigned char maprom;
117 /* Signal Handler for SIGINT */
118 void sigint_handler(int sig_num)
120 /* Reset handler to catch SIGINT next time.
121 Refer http://en.cppreference.com/w/c/program/signal */
122 printf("\n User provided signal handler for Ctrl+C \n");
124 /* Do a graceful cleanup of the program like: free memory/resources/etc and exit */
129 void* iplThread(void *args){
132 //srdata2_old = read_reg();
136 //printf("thread!/n");
137 if (GET_GPIO(1) == 0){
139 if (srdata != srdata2_old){
140 srdata2 = ((srdata >> 13)&0xff);
141 //printf("STATUS: %d\n", srdata2);
142 srdata2_old = srdata;
143 m68k_set_irq(srdata2);
150 srdata2 = ((srdata >> 13)&0xff);
151 srdata2_old = srdata;
152 m68k_set_irq(srdata2);
155 //printf("STATUS: 0\n");
171 const struct sched_param priority = {99};
173 sched_setscheduler(0, SCHED_RR , &priority);
174 printf("YES locked in memory\n");
175 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
182 ide0 = ide_allocate("cf");
183 fd = open("hd0.img", O_RDWR);
185 printf("HDD Image hd0.image failed open\n");
187 ide_attach(ide0, 0, fd);
188 ide_reset_begin(ide0);
189 printf("HDD Image hd0.image attached\n");
192 signal(SIGINT, sigint_handler);
195 //Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending on pi model
196 printf("Enable GPCLK0 on GPIO4\n");
198 *(gpclk+ (CLK_GP0_CTL/4)) = CLK_PASSWD | (1 << 5);
200 while ( (*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7));
202 *(gpclk+(CLK_GP0_DIV/4)) = CLK_PASSWD | (6 << 12); //divider , 6=200MHz on pi3
204 *(gpclk+(CLK_GP0_CTL/4)) = CLK_PASSWD | 5 | (1 << 4); //pll? 6=plld, 5=pllc
206 while (((*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7))== 0);
209 SET_GPIO_ALT(4,0); //gpclk0
219 //set gpio0 (aux0) and gpio1 (aux1) to input
223 // Set GPIO pins 6,7 and 8-23 to output
224 for (g=6; g<=23; g++)
229 printf ("Precalculate GPIO8-23 aus Output\n");
230 gpfsel0_o =*(gpio); //store gpio ddr
231 printf ("gpfsel0: %#x\n", gpfsel0_o);
232 gpfsel1_o =*(gpio+1); //store gpio ddr
233 printf ("gpfsel1: %#x\n", gpfsel1_o);
234 gpfsel2_o =*(gpio+2); //store gpio ddr
235 printf ("gpfsel2: %#x\n", gpfsel2_o);
237 // Set GPIO pins 8-23 to input
238 for (g=8; g<=23; g++)
242 printf ("Precalculate GPIO8-23 as Input\n");
243 gpfsel0 =*(gpio); //store gpio ddr
244 printf ("gpfsel0: %#x\n", gpfsel0);
245 gpfsel1 =*(gpio+1); //store gpio ddr
246 printf ("gpfsel1: %#x\n", gpfsel1);
247 gpfsel2 =*(gpio+2); //store gpio ddr
248 printf ("gpfsel2: %#x\n", gpfsel2);
257 //reset cpld statemachine first
267 fp = fopen("kick.rom", "rb");
270 printf("kick.rom cannot be opened\n");
272 printf("kick.rom found, using that instead of motherboard rom\n");
275 unsigned int reads = fread(&g_kick, sizeof(g_kick), 1, fp);
277 printf("failed loading kick.rom\n");
279 printf("loaded kick.rom\n");
287 m68k_write_memory_8(0xbfe201,0x0001); //AMIGA OVL
288 m68k_write_memory_8(0xbfe001,0x0001); //AMIGA OVL high (ROM@0x0)
294 m68k_set_cpu_type(M68K_CPU_TYPE_68EC030);
296 srdata2_old = read_reg();
297 printf("STATUS: %d\n", srdata2_old);
304 //err = pthread_create(&id, NULL, &iplThread, NULL);
306 printf("\ncan't create IPL thread :[%s]", strerror(err));
308 printf("\n IPL Thread created successfully\n");
316 //printf("IRQ:0x%06x\n",CheckIrq());
324 if (GET_GPIO(1) == 0 || CheckIrq() == 1){
326 // if (CheckIrq() == 1) srdata |= (1 << 14);
327 if (srdata != srdata2_old){
328 srdata2 = ((srdata >> 13)&0xff);
329 //printf("STATUS: %d\n", srdata2);
330 srdata2_old = srdata;
331 m68k_set_irq(srdata2);
338 srdata2 = ((srdata >> 13)&0xff);
339 srdata2_old = srdata;
340 m68k_set_irq(srdata2);
341 //printf("STATUS: 0\n");
353 void cpu_pulse_reset(void){
361 int cpu_irq_ack(int level)
363 printf("cpu irq ack\n");
369 unsigned int m68k_read_memory_8(unsigned int address){
371 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
372 return readGayleB(address);
375 if(address>FASTBASE){
376 return g_ram[address- FASTBASE];
380 if (ovl == 1 && address<0x07FFFF ){
381 return g_kick[address];}
382 if (ovl == 0 && (address>0xF80000-1 && address<0xFFFFFF)){
383 return g_kick[address-0xF80000];}
386 return read8((uint32_t)address);
389 unsigned int m68k_read_memory_16(unsigned int address){
391 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
392 return readGayle(address);
395 if(address>FASTBASE){
396 uint16_t value = *(uint16_t*)&g_ram[address- FASTBASE];
397 value = (value << 8) | (value >> 8);
402 if (ovl == 1 && address<0x07FFFF ){
403 uint16_t value = *(uint16_t*)&g_kick[address];
404 return (value << 8) | (value >> 8);}
405 if (ovl == 0 && (address>0xF80000-1 && address<0xFFFFFF)){
406 //printf("kread16/n");
407 uint16_t value = *(uint16_t*)&g_kick[address-0xF80000];
408 return (value << 8) | (value >> 8);}
411 return (unsigned int)read16((uint32_t)address);
414 unsigned int m68k_read_memory_32(unsigned int address){
416 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
417 return readGayleL(address);
420 if(address>FASTBASE){
421 uint32_t value = *(uint32_t*)&g_ram[address- FASTBASE];
422 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
423 return value << 16 | value >> 16;
427 if (ovl == 1 && address<0x07FFFF){
428 uint32_t value = *(uint32_t*)&g_kick[address];
429 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
430 return value << 16 | value >> 16;}
432 if (ovl == 0 && (address>0xF80000-1 && address<0xFFFFFF)){
433 //printf("kread32/n");
434 uint32_t value = *(uint32_t*)&g_kick[address-0xF80000];
435 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
436 return value << 16 | value >> 16;}
439 uint16_t a = read16(address);
440 uint16_t b = read16(address+2);
441 return (a << 16) | b;
444 void m68k_write_memory_8(unsigned int address, unsigned int value){
447 if (address == 0xbfe001){
448 ovl = (value & (1<<0));
449 //printf("OVL:%x\n", ovl );
453 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
454 writeGayleB(address, value);
459 if(address>FASTBASE){
460 g_ram[address- FASTBASE] = value;
464 write8((uint32_t)address,value);
468 void m68k_write_memory_16(unsigned int address, unsigned int value){
469 // if (address==0xdff030) printf("%c", value);
471 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
472 writeGayle(address,value);
476 if (address == 0xbfe001)
477 printf("16CIA Output:%x\n", value );
480 if(address>FASTBASE){
481 uint16_t* dest = (uint16_t*)&g_ram[address- FASTBASE];
482 value = (value << 8) | (value >> 8);
487 write16((uint32_t)address,value);
491 void m68k_write_memory_32(unsigned int address, unsigned int value){
494 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
495 writeGayleL(address, value);
498 if(address>FASTBASE){
499 uint32_t* dest = (uint32_t*)&g_ram[address- FASTBASE];
500 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
501 value = value << 16 | value >> 16;
506 write16(address , value >> 16);
507 write16(address+2 , value );
512 void write32(uint32_t address, uint32_t data){
513 write16(address+2 , data);
514 write16(address , data >>16 );
517 uint32_t read32(uint32_t address){
518 uint16_t a = read16(address+2);
519 uint16_t b = read16(address);
524 void write16(uint32_t address, uint32_t data)
526 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
527 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
528 uint32_t addr_l_s = (address >> 16) << 8;
529 uint32_t addr_l_r = (~address >> 16) << 8;
530 uint32_t data_s = (data & 0x0000ffff) << 8;
531 uint32_t data_r = (~data & 0x0000ffff) << 8;
533 // asm volatile ("dmb" ::: "memory");
536 *(gpio + 1) = gpfsel1_o;
537 *(gpio + 2) = gpfsel2_o;
539 *(gpio + 7) = addr_h_s;
540 *(gpio + 10) = addr_h_r;
544 *(gpio + 7) = addr_l_s;
545 *(gpio + 10) = addr_l_r;
550 *(gpio + 7) = data_s;
551 *(gpio + 10) = data_r;
556 *(gpio + 1) = gpfsel1;
557 *(gpio + 2) = gpfsel2;
558 while ((GET_GPIO(0)));
559 // asm volatile ("dmb" ::: "memory");
563 void write8(uint32_t address, uint32_t data)
566 if ((address & 1) == 0)
567 data = data + (data << 8); //EVEN, A0=0,UDS
568 else data = data & 0xff ; //ODD , A0=1,LDS
569 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
570 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
571 uint32_t addr_l_s = (address >> 16) << 8;
572 uint32_t addr_l_r = (~address >> 16) << 8;
573 uint32_t data_s = (data & 0x0000ffff) << 8;
574 uint32_t data_r = (~data & 0x0000ffff) << 8;
577 // asm volatile ("dmb" ::: "memory");
580 *(gpio + 1) = gpfsel1_o;
581 *(gpio + 2) = gpfsel2_o;
583 *(gpio + 7) = addr_h_s;
584 *(gpio + 10) = addr_h_r;
588 *(gpio + 7) = addr_l_s;
589 *(gpio + 10) = addr_l_r;
594 *(gpio + 7) = data_s;
595 *(gpio + 10) = data_r;
600 *(gpio + 1) = gpfsel1;
601 *(gpio + 2) = gpfsel2;
602 while ((GET_GPIO(0)));
603 // asm volatile ("dmb" ::: "memory");
608 uint32_t read16(uint32_t address)
611 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
612 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
613 uint32_t addr_l_s = (address >> 16) << 8;
614 uint32_t addr_l_r = (~address >> 16) << 8;
616 // asm volatile ("dmb" ::: "memory");
620 *(gpio + 1) = gpfsel1_o;
621 *(gpio + 2) = gpfsel2_o;
623 *(gpio + 7) = addr_h_s;
624 *(gpio + 10) = addr_h_r;
628 *(gpio + 7) = addr_l_s;
629 *(gpio + 10) = addr_l_r;
637 *(gpio + 1) = gpfsel1;
638 *(gpio + 2) = gpfsel2;
641 while (!(GET_GPIO(0)));
643 asm volatile ("nop" ::);
644 asm volatile ("nop" ::);
645 asm volatile ("nop" ::);
648 // asm volatile ("dmb" ::: "memory");
649 return (val >>8)&0xffff;
653 uint32_t read8(uint32_t address)
656 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
657 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
658 uint32_t addr_l_s = (address >> 16) << 8;
659 uint32_t addr_l_r = (~address >> 16) << 8;
661 // asm volatile ("dmb" ::: "memory");
664 *(gpio + 1) = gpfsel1_o;
665 *(gpio + 2) = gpfsel2_o;
667 *(gpio + 7) = addr_h_s;
668 *(gpio + 10) = addr_h_r;
672 *(gpio + 7) = addr_l_s;
673 *(gpio + 10) = addr_l_r;
680 *(gpio + 1) = gpfsel1;
681 *(gpio + 2) = gpfsel2;
684 while (!(GET_GPIO(0)));
686 asm volatile ("nop" ::);
687 asm volatile ("nop" ::);
688 asm volatile ("nop" ::);
691 // asm volatile ("dmb" ::: "memory");
693 val = (val >>8)&0xffff;
694 if ((address & 1) == 0)
695 val = (val >> 8) & 0xff ; //EVEN, A0=0,UDS
697 val = val & 0xff ; //ODD , A0=1,LDS
703 /******************************************************/
705 void write_reg(unsigned int value)
707 asm volatile ("dmb" ::: "memory");
709 asm volatile ("nop" ::);
710 asm volatile ("nop" ::);
711 asm volatile ("nop" ::);
712 //Write Status register
718 *(gpio + 1) = gpfsel1_o;
719 *(gpio + 2) = gpfsel2_o;
720 *(gpio + 7) = (value & 0xffff) << 8;
721 *(gpio + 10) = (~value & 0xffff) << 8;
723 GPIO_CLR = 1 << 7; //delay
728 *(gpio + 1) = gpfsel1;
729 *(gpio + 2) = gpfsel2;
730 asm volatile ("dmb" ::: "memory");
734 uint16_t read_reg(void)
738 asm volatile ("dmb" ::: "memory");
740 asm volatile ("nop" ::);
741 asm volatile ("nop" ::);
742 asm volatile ("nop" ::);
745 *(gpio + 1) = gpfsel1;
746 *(gpio + 2) = gpfsel2;
749 GPIO_CLR = 1 << 6; //delay
754 asm volatile ("dmb" ::: "memory");
756 return (uint16_t)(val >> 8);
761 // Set up a memory regions to access GPIO
766 if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
767 printf("can't open /dev/mem \n");
773 NULL, //Any adddress in our space will do
774 BCM2708_PERI_SIZE, //Map length
775 PROT_READ|PROT_WRITE,// Enable reading & writting to mapped memory
776 MAP_SHARED, //Shared with other processes
777 mem_fd, //File to map
778 BCM2708_PERI_BASE //Offset to GPIO peripheral
781 close(mem_fd); //No need to keep mem_fd open after mmap
783 if (gpio_map == MAP_FAILED) {
784 printf("gpio mmap error %d\n", (int)gpio_map);//errno also set!
788 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR/4;
789 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR/4;