14 #include <sys/types.h>
21 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
22 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
23 #define BCM2708_PERI_BASE 0x3F000000 // pi3
24 #define BCM2708_PERI_SIZE 0x01000000
25 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
26 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
27 #define GPIO_ADDR 0x200000 /* GPIO controller */
28 #define GPCLK_ADDR 0x101000
29 #define CLK_PASSWD 0x5a000000
30 #define CLK_GP0_CTL 0x070
31 #define CLK_GP0_DIV 0x074
37 #define STATUSREGADDR \
38 GPIO_CLR = 1 << SA0; \
39 GPIO_CLR = 1 << SA1; \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_SET = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_CLR = 1 << SA0; \
51 GPIO_SET = 1 << SA1; \
54 GPIO_SET = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 #define PAGE_SIZE (4 * 1024)
59 #define BLOCK_SIZE (4 * 1024)
61 #define GPIOSET(no, ishigh) \
66 reset |= (1 << (no)); \
69 #define FASTBASE 0x07FFFFFF
70 #define FASTSIZE 0xFFFFFFF
71 #define GAYLEBASE 0xD80000 // D7FFFF
72 #define GAYLESIZE 0x6FFFF
74 #define KICKBASE 0xF80000
75 #define KICKSIZE 0x7FFFF
79 int gayle_emulation_enabled = 1;
84 volatile unsigned int *gpio;
85 volatile unsigned int *gpclk;
86 volatile unsigned int gpfsel0;
87 volatile unsigned int gpfsel1;
88 volatile unsigned int gpfsel2;
89 volatile unsigned int gpfsel0_o;
90 volatile unsigned int gpfsel1_o;
91 volatile unsigned int gpfsel2_o;
93 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
95 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
96 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
97 #define SET_GPIO_ALT(g, a) \
98 *(gpio + (((g) / 10))) |= \
99 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
102 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
104 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
106 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
108 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
109 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
113 uint32_t read8(uint32_t address);
114 void write8(uint32_t address, uint32_t data);
116 uint32_t read16(uint32_t address);
117 void write16(uint32_t address, uint32_t data);
119 void write32(uint32_t address, uint32_t data);
120 uint32_t read32(uint32_t address);
122 uint16_t read_reg(void);
123 void write_reg(unsigned int value);
125 volatile uint16_t srdata;
126 volatile uint32_t srdata2;
127 volatile uint32_t srdata2_old;
129 unsigned char g_kick[524288];
130 unsigned char g_ram[FASTSIZE + 1]; /* RAM */
131 unsigned char toggle;
132 static volatile unsigned char ovl;
133 static volatile unsigned char maprom;
135 void sigint_handler(int sig_num) {
136 printf("\n Exit Ctrl+C %d\n", sig_num);
140 void *iplThread(void *args) {
141 printf("IPL thread running/n");
145 if (GET_GPIO(1) == 0){
147 m68k_end_timeslice();
148 //printf("thread!/n");
157 int main(int argc, char *argv[]) {
159 const struct sched_param priority = {99};
161 // Some command line switch stuffles
162 for (g = 1; g < argc; g++) {
163 if (strcmp(argv[g], "--disable-gayle") == 0) {
164 gayle_emulation_enabled = 0;
168 sched_setscheduler(0, SCHED_FIFO, &priority);
169 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
173 signal(SIGINT, sigint_handler);
176 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
178 printf("Enable 200MHz GPCLK0 on GPIO4\n");
180 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
182 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
185 *(gpclk + (CLK_GP0_DIV / 4)) =
186 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
188 *(gpclk + (CLK_GP0_CTL / 4)) =
189 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
191 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
195 SET_GPIO_ALT(4, 0); // gpclk0
205 // set gpio0 (aux0) and gpio1 (aux1) to input
209 // Set GPIO pins 6,7 and 8-23 to output
210 for (g = 6; g <= 23; g++) {
214 printf("Precalculate GPIO8-23 as Output\n");
215 gpfsel0_o = *(gpio); // store gpio ddr
216 printf("gpfsel0: %#x\n", gpfsel0_o);
217 gpfsel1_o = *(gpio + 1); // store gpio ddr
218 printf("gpfsel1: %#x\n", gpfsel1_o);
219 gpfsel2_o = *(gpio + 2); // store gpio ddr
220 printf("gpfsel2: %#x\n", gpfsel2_o);
222 // Set GPIO pins 8-23 to input
223 for (g = 8; g <= 23; g++) {
226 printf("Precalculate GPIO8-23 as Input\n");
227 gpfsel0 = *(gpio); // store gpio ddr
228 printf("gpfsel0: %#x\n", gpfsel0);
229 gpfsel1 = *(gpio + 1); // store gpio ddr
230 printf("gpfsel1: %#x\n", gpfsel1);
231 gpfsel2 = *(gpio + 2); // store gpio ddr
232 printf("gpfsel2: %#x\n", gpfsel2);
241 // reset cpld statemachine first
249 // load kick.rom if present
252 fd = open("kick.rom", O_RDONLY);
254 printf("Failed loading kick.rom, using motherboard kickstart\n");
257 int size = (int)lseek(fd, 0, SEEK_END);
258 if (size == 0x40000) {
259 lseek(fd, 0, SEEK_SET);
260 read(fd, &g_kick, size);
261 lseek(fd, 0, SEEK_SET);
262 read(fd, &g_kick[0x40000], size);
264 lseek(fd, 0, SEEK_SET);
265 read(fd, &g_kick, size);
267 printf("Loaded kick.rom with size %d kib\n", size / 1024);
270 // reset amiga and statemachine
273 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
274 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
279 m68k_set_cpu_type(M68K_CPU_TYPE_68030);
283 m68k_set_reg(M68K_REG_PC, 0xF80002);
285 m68k_set_reg(M68K_REG_PC, 0x0);
291 err = pthread_create(&id, NULL, &iplThread, NULL);
293 printf("\ncan't create IPL thread :[%s]", strerror(err));
295 printf("\n IPL Thread created successfully\n");
305 m68k_set_irq((srdata >> 13) & 0xff);
313 if (GET_GPIO(1) == 0){
315 m68k_set_irq((srdata >> 13) & 0xff);
317 // if (CheckIrq() == 1)
328 void cpu_pulse_reset(void) {
330 // printf("Status Reg%x\n",read_reg());
333 // printf("Status Reg%x\n",read_reg());
336 int cpu_irq_ack(int level) {
337 printf("cpu irq ack\n");
341 unsigned int m68k_read_memory_8(unsigned int address) {
342 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
343 return g_ram[address - FASTBASE];
347 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
348 return g_kick[address - KICKBASE];
352 if (gayle_emulation_enabled) {
353 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
354 return readGayleB(address);
359 // if (address < 0xffffff) {
360 return read8((uint32_t)address);
366 unsigned int m68k_read_memory_16(unsigned int address) {
367 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
368 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
372 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
373 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
377 if (gayle_emulation_enabled) {
378 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
379 return readGayle(address);
383 // if (address < 0xffffff) {
385 return (unsigned int)read16((uint32_t)address);
391 unsigned int m68k_read_memory_32(unsigned int address) {
392 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
393 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
397 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
398 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
402 if (gayle_emulation_enabled) {
403 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
404 return readGayleL(address);
408 // if (address < 0xffffff) {
410 uint16_t a = read16(address);
411 uint16_t b = read16(address + 2);
412 return (a << 16) | b;
418 void m68k_write_memory_8(unsigned int address, unsigned int value) {
419 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
420 g_ram[address - FASTBASE] = value;
424 if (gayle_emulation_enabled) {
425 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
426 writeGayleB(address, value);
431 if (address == 0xbfe001) {
432 ovl = (value & (1 << 0));
433 printf("OVL:%x\n", ovl);
436 // if (address < 0xffffff) {
438 write8((uint32_t)address, value);
445 void m68k_write_memory_16(unsigned int address, unsigned int value) {
446 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
447 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
451 if (gayle_emulation_enabled) {
452 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
453 writeGayle(address, value);
458 // if (address < 0xffffff) {
460 write16((uint32_t)address, value);
466 void m68k_write_memory_32(unsigned int address, unsigned int value) {
467 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
468 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
472 if (gayle_emulation_enabled) {
473 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
474 writeGayleL(address, value);
478 // if (address < 0xffffff) {
480 write16(address, value >> 16);
481 write16(address + 2, value);
488 void write16(uint32_t address, uint32_t data) {
489 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
490 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
491 uint32_t addr_l_s = (address >> 16) << 8;
492 uint32_t addr_l_r = (~address >> 16) << 8;
493 uint32_t data_s = (data & 0x0000ffff) << 8;
494 uint32_t data_r = (~data & 0x0000ffff) << 8;
496 // asm volatile ("dmb" ::: "memory");
499 *(gpio + 1) = gpfsel1_o;
500 *(gpio + 2) = gpfsel2_o;
502 *(gpio + 7) = addr_h_s;
503 *(gpio + 10) = addr_h_r;
507 *(gpio + 7) = addr_l_s;
508 *(gpio + 10) = addr_l_r;
513 *(gpio + 7) = data_s;
514 *(gpio + 10) = data_r;
519 *(gpio + 1) = gpfsel1;
520 *(gpio + 2) = gpfsel2;
521 while ((GET_GPIO(0)))
523 // asm volatile ("dmb" ::: "memory");
526 void write8(uint32_t address, uint32_t data) {
527 if ((address & 1) == 0)
528 data = data + (data << 8); // EVEN, A0=0,UDS
530 data = data & 0xff; // ODD , A0=1,LDS
531 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
532 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
533 uint32_t addr_l_s = (address >> 16) << 8;
534 uint32_t addr_l_r = (~address >> 16) << 8;
535 uint32_t data_s = (data & 0x0000ffff) << 8;
536 uint32_t data_r = (~data & 0x0000ffff) << 8;
538 // asm volatile ("dmb" ::: "memory");
541 *(gpio + 1) = gpfsel1_o;
542 *(gpio + 2) = gpfsel2_o;
544 *(gpio + 7) = addr_h_s;
545 *(gpio + 10) = addr_h_r;
549 *(gpio + 7) = addr_l_s;
550 *(gpio + 10) = addr_l_r;
555 *(gpio + 7) = data_s;
556 *(gpio + 10) = data_r;
561 *(gpio + 1) = gpfsel1;
562 *(gpio + 2) = gpfsel2;
563 while ((GET_GPIO(0)))
565 // asm volatile ("dmb" ::: "memory");
568 uint32_t read16(uint32_t address) {
570 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
571 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
572 uint32_t addr_l_s = (address >> 16) << 8;
573 uint32_t addr_l_r = (~address >> 16) << 8;
575 // asm volatile ("dmb" ::: "memory");
578 *(gpio + 1) = gpfsel1_o;
579 *(gpio + 2) = gpfsel2_o;
581 *(gpio + 7) = addr_h_s;
582 *(gpio + 10) = addr_h_r;
586 *(gpio + 7) = addr_l_s;
587 *(gpio + 10) = addr_l_r;
593 *(gpio + 1) = gpfsel1;
594 *(gpio + 2) = gpfsel2;
596 while (!(GET_GPIO(0)))
601 // asm volatile ("dmb" ::: "memory");
602 return (val >> 8) & 0xffff;
605 uint32_t read8(uint32_t address) {
607 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
608 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
609 uint32_t addr_l_s = (address >> 16) << 8;
610 uint32_t addr_l_r = (~address >> 16) << 8;
612 // asm volatile ("dmb" ::: "memory");
615 *(gpio + 1) = gpfsel1_o;
616 *(gpio + 2) = gpfsel2_o;
618 *(gpio + 7) = addr_h_s;
619 *(gpio + 10) = addr_h_r;
623 *(gpio + 7) = addr_l_s;
624 *(gpio + 10) = addr_l_r;
630 *(gpio + 1) = gpfsel1;
631 *(gpio + 2) = gpfsel2;
634 while (!(GET_GPIO(0)))
639 // asm volatile ("dmb" ::: "memory");
641 val = (val >> 8) & 0xffff;
642 if ((address & 1) == 0)
643 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
645 return val & 0xff; // ODD , A0=1,LDS
648 /******************************************************/
650 void write_reg(unsigned int value) {
653 *(gpio + 1) = gpfsel1_o;
654 *(gpio + 2) = gpfsel2_o;
655 *(gpio + 7) = (value & 0xffff) << 8;
656 *(gpio + 10) = (~value & 0xffff) << 8;
658 GPIO_CLR = 1 << 7; // delay
663 *(gpio + 1) = gpfsel1;
664 *(gpio + 2) = gpfsel2;
667 uint16_t read_reg(void) {
672 *(gpio + 1) = gpfsel1;
673 *(gpio + 2) = gpfsel2;
675 GPIO_CLR = 1 << 6; // delay
680 return (uint16_t)(val >> 8);
684 // Set up a memory regions to access GPIO
688 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
689 printf("can't open /dev/mem \n");
695 NULL, // Any adddress in our space will do
696 BCM2708_PERI_SIZE, // Map length
697 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
698 MAP_SHARED, // Shared with other processes
699 mem_fd, // File to map
700 BCM2708_PERI_BASE // Offset to GPIO peripheral
703 close(mem_fd); // No need to keep mem_fd open after mmap
705 if (gpio_map == MAP_FAILED) {
706 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
710 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
711 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;