20 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
21 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
22 #define BCM2708_PERI_BASE 0x3F000000 //pi3
23 #define BCM2708_PERI_SIZE 0x01000000
24 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
25 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
26 #define GPIO_ADDR 0x200000 /* GPIO controller */
27 #define GPCLK_ADDR 0x101000
28 #define CLK_PASSWD 0x5a000000
29 #define CLK_GP0_CTL 0x070
30 #define CLK_GP0_DIV 0x074
36 #define STATUSREGADDR GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_SET = 1<<SA2;
37 #define W16 GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
38 #define R16 GPIO_SET = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
39 #define W8 GPIO_CLR = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
40 #define R8 GPIO_SET = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
42 #define PAGE_SIZE (4*1024)
43 #define BLOCK_SIZE (4*1024)
45 #define GPIOSET(no, ishigh) \
50 reset |= (1 << (no)); \
54 #define FASTBASE 0x07FFFFFF
55 #define FASTSIZE 0xFFFFFFF
56 #define GAYLEBASE 0xD80000 //D7FFFF
57 #define GAYLESIZE 0x6FFFF
59 #define KICKBASE 0xF80000
60 #define KICKSIZE 0x7FFFF
68 volatile unsigned int *gpio;
69 volatile unsigned int *gpclk;
70 volatile unsigned int gpfsel0;
71 volatile unsigned int gpfsel1;
72 volatile unsigned int gpfsel2;
73 volatile unsigned int gpfsel0_o;
74 volatile unsigned int gpfsel1_o;
75 volatile unsigned int gpfsel2_o;
77 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y)
78 #define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
79 #define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3))
80 #define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
82 #define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0
83 #define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0
85 #define GET_GPIO(g) (*(gpio+13)&(1<<g)) // 0 if LOW, (1<<g) if HIGH
87 #define GPIO_PULL *(gpio+37) // Pull up/pull down
88 #define GPIO_PULLCLK0 *(gpio+38) // Pull up/pull down clock
93 uint32_t read8(uint32_t address);
94 void write8(uint32_t address, uint32_t data);
96 uint32_t read16(uint32_t address);
97 void write16(uint32_t address, uint32_t data);
99 void write32(uint32_t address, uint32_t data);
100 uint32_t read32(uint32_t address);
102 uint16_t read_reg(void);
103 void write_reg(unsigned int value);
105 volatile uint16_t srdata;
106 volatile uint32_t srdata2;
107 volatile uint32_t srdata2_old;
110 unsigned char g_kick[524288];
111 unsigned char g_ram[FASTSIZE+1]; /* RAM */
112 unsigned char toggle;
113 static volatile unsigned char ovl;
114 static volatile unsigned char maprom;
117 /* Signal Handler for SIGINT */
118 void sigint_handler(int sig_num)
120 /* Reset handler to catch SIGINT next time.
121 Refer http://en.cppreference.com/w/c/program/signal */
122 printf("\n User provided signal handler for Ctrl+C \n");
124 /* Do a graceful cleanup of the program like: free memory/resources/etc and exit */
129 void* iplThread(void *args){
132 //srdata2_old = read_reg();
136 //printf("thread!/n");
137 if (GET_GPIO(1) == 0){
139 if (srdata != srdata2_old){
140 srdata2 = ((srdata >> 13)&0xff);
141 //printf("STATUS: %d\n", srdata2);
142 srdata2_old = srdata;
143 m68k_set_irq(srdata2);
150 srdata2 = ((srdata >> 13)&0xff);
151 srdata2_old = srdata;
152 m68k_set_irq(srdata2);
155 //printf("STATUS: 0\n");
169 const struct sched_param priority = {99};
171 sched_setscheduler(0, SCHED_RR , &priority);
172 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
177 signal(SIGINT, sigint_handler);
180 //Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending on pi model
181 printf("Enable GPCLK0 on GPIO4\n");
183 *(gpclk+ (CLK_GP0_CTL/4)) = CLK_PASSWD | (1 << 5);
185 while ( (*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7));
187 *(gpclk+(CLK_GP0_DIV/4)) = CLK_PASSWD | (6 << 12); //divider , 6=200MHz on pi3
189 *(gpclk+(CLK_GP0_CTL/4)) = CLK_PASSWD | 5 | (1 << 4); //pll? 6=plld, 5=pllc
191 while (((*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7))== 0);
194 SET_GPIO_ALT(4,0); //gpclk0
204 //set gpio0 (aux0) and gpio1 (aux1) to input
208 // Set GPIO pins 6,7 and 8-23 to output
209 for (g=6; g<=23; g++)
214 printf ("Precalculate GPIO8-23 aus Output\n");
215 gpfsel0_o =*(gpio); //store gpio ddr
216 printf ("gpfsel0: %#x\n", gpfsel0_o);
217 gpfsel1_o =*(gpio+1); //store gpio ddr
218 printf ("gpfsel1: %#x\n", gpfsel1_o);
219 gpfsel2_o =*(gpio+2); //store gpio ddr
220 printf ("gpfsel2: %#x\n", gpfsel2_o);
222 // Set GPIO pins 8-23 to input
223 for (g=8; g<=23; g++)
227 printf ("Precalculate GPIO8-23 as Input\n");
228 gpfsel0 =*(gpio); //store gpio ddr
229 printf ("gpfsel0: %#x\n", gpfsel0);
230 gpfsel1 =*(gpio+1); //store gpio ddr
231 printf ("gpfsel1: %#x\n", gpfsel1);
232 gpfsel2 =*(gpio+2); //store gpio ddr
233 printf ("gpfsel2: %#x\n", gpfsel2);
242 //reset cpld statemachine first
253 fp = fopen("kick.rom", "rb");
256 printf("kick.rom cannot be opened\n");
258 printf("kick.rom found, using that instead of motherboard rom\n");
261 unsigned int reads = fread(&g_kick, sizeof(g_kick), 1, fp);
263 printf("failed loading kick.rom\n");
265 printf("loaded kick.rom\n");
274 fd = open("kick.rom",O_RDONLY);
276 printf("failed loading kick.rom, using motherboard kickstart\n");
279 int size = (int)lseek(fd, 0, SEEK_END);
281 lseek(fd, 0, SEEK_SET);
282 read(fd, &g_kick, size);
283 lseek(fd, 0, SEEK_SET);
284 read(fd, &g_kick[0x40000], size);
286 lseek(fd, 0, SEEK_SET);
287 read(fd, &g_kick, size);
289 printf("loaded kick.rom with size %d kib\n",size/1024);
293 m68k_write_memory_8(0xbfe201,0x0001); //AMIGA OVL
294 m68k_write_memory_8(0xbfe001,0x0001); //AMIGA OVL high (ROM@0x0)
300 m68k_set_cpu_type(M68K_CPU_TYPE_68030);
304 m68k_set_reg(M68K_REG_PC, 0xF80002);
306 m68k_set_reg(M68K_REG_PC, 0x0);
312 //err = pthread_create(&id, NULL, &iplThread, NULL);
314 printf("\ncan't create IPL thread :[%s]", strerror(err));
316 printf("\n IPL Thread created successfully\n");
323 if (GET_GPIO(1) == 0){
325 m68k_set_irq((srdata >> 13)&0xff);
336 void cpu_pulse_reset(void){
346 int cpu_irq_ack(int level)
348 printf("cpu irq ack\n");
354 unsigned int m68k_read_memory_8(unsigned int address){
358 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
359 return g_kick[address-KICKBASE];
363 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
364 return readGayleB(address);
367 if(address>FASTBASE){
368 return g_ram[address- FASTBASE];
372 if (ovl == 1 && address<KICKSIZE){
373 return g_kick[address];}
374 if (ovl == 0 && (address>KICKBASE && address<KICKBASE + KICKSIZE)){
375 return g_kick[address-KICKBASE];}
378 if (address < 0xffffff){
379 return read8((uint32_t)address);
385 unsigned int m68k_read_memory_16(unsigned int address){
389 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
390 uint16_t value = *(uint16_t*)&g_kick[address-KICKBASE];
391 value = (value << 8) | (value >> 8);
396 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
397 return readGayle(address);
400 if(address>FASTBASE){
401 uint16_t value = *(uint16_t*)&g_ram[address- FASTBASE];
402 value = (value << 8) | (value >> 8);
408 if (ovl == 1 && address<KICKSIZE ){
409 uint16_t value = *(uint16_t*)&g_kick[address];
410 return (value << 8) | (value >> 8);}
411 if (ovl == 0 && (address>KICKBASE && address<KICKBASE + KICKSIZE)){
412 //printf("kread16 addr: %x\n",address);
413 uint16_t value = *(uint16_t*)&g_kick[address-KICKBASE];
414 return (value << 8) | (value >> 8);}
417 if (address < 0xffffff){
418 return (unsigned int)read16((uint32_t)address);
424 unsigned int m68k_read_memory_32(unsigned int address){
427 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
428 uint32_t value = *(uint32_t*)&g_kick[address-KICKBASE];
429 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
430 return value << 16 | value >> 16;
434 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
435 return readGayleL(address);
438 if(address>FASTBASE){
439 uint32_t value = *(uint32_t*)&g_ram[address- FASTBASE];
440 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
441 return value << 16 | value >> 16;
446 if (ovl == 1 && address<KICKSIZE){
447 uint32_t value = *(uint32_t*)&g_kick[address];
448 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
449 return value << 16 | value >> 16;}
450 if (ovl == 0 && (address>KICKBASE && address<KICKBASE + KICKSIZE)){
451 //printf("kread32/n");
452 uint32_t value = *(uint32_t*)&g_kick[address-KICKBASE];
453 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
454 return value << 16 | value >> 16;}
457 if (address < 0xffffff){
458 uint16_t a = read16(address);
459 uint16_t b = read16(address+2);
460 return (a << 16) | b;
466 void m68k_write_memory_8(unsigned int address, unsigned int value){
469 if (address == 0xbfe001){
470 ovl = (value & (1<<0));
471 printf("OVL:%x\n", ovl );
475 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
476 writeGayleB(address, value);
481 if(address>FASTBASE){
482 g_ram[address- FASTBASE] = value;
486 if (address < 0xffffff){
487 write8((uint32_t)address,value);
494 void m68k_write_memory_16(unsigned int address, unsigned int value){
495 // if (address==0xdff030) printf("%c", value);
497 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
498 writeGayle(address,value);
502 if (address == 0xbfe001)
503 printf("16CIA Output:%x\n", value );
506 if(address>FASTBASE){
507 uint16_t* dest = (uint16_t*)&g_ram[address- FASTBASE];
508 value = (value << 8) | (value >> 8);
513 if (address < 0xffffff){
514 write16((uint32_t)address,value);
520 void m68k_write_memory_32(unsigned int address, unsigned int value){
523 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
524 writeGayleL(address, value);
527 if(address>FASTBASE){
528 uint32_t* dest = (uint32_t*)&g_ram[address- FASTBASE];
529 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
530 value = value << 16 | value >> 16;
535 if (address < 0xffffff){
536 write16(address , value >> 16);
537 write16(address+2 , value );
545 void write32(uint32_t address, uint32_t data){
546 write16(address+2 , data);
547 write16(address , data >>16 );
550 uint32_t read32(uint32_t address){
551 uint16_t a = read16(address+2);
552 uint16_t b = read16(address);
557 void write16(uint32_t address, uint32_t data)
559 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
560 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
561 uint32_t addr_l_s = (address >> 16) << 8;
562 uint32_t addr_l_r = (~address >> 16) << 8;
563 uint32_t data_s = (data & 0x0000ffff) << 8;
564 uint32_t data_r = (~data & 0x0000ffff) << 8;
566 // asm volatile ("dmb" ::: "memory");
569 *(gpio + 1) = gpfsel1_o;
570 *(gpio + 2) = gpfsel2_o;
572 *(gpio + 7) = addr_h_s;
573 *(gpio + 10) = addr_h_r;
577 *(gpio + 7) = addr_l_s;
578 *(gpio + 10) = addr_l_r;
583 *(gpio + 7) = data_s;
584 *(gpio + 10) = data_r;
589 *(gpio + 1) = gpfsel1;
590 *(gpio + 2) = gpfsel2;
591 while ((GET_GPIO(0)));
592 // asm volatile ("dmb" ::: "memory");
596 void write8(uint32_t address, uint32_t data)
599 if ((address & 1) == 0)
600 data = data + (data << 8); //EVEN, A0=0,UDS
601 else data = data & 0xff ; //ODD , A0=1,LDS
602 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
603 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
604 uint32_t addr_l_s = (address >> 16) << 8;
605 uint32_t addr_l_r = (~address >> 16) << 8;
606 uint32_t data_s = (data & 0x0000ffff) << 8;
607 uint32_t data_r = (~data & 0x0000ffff) << 8;
610 // asm volatile ("dmb" ::: "memory");
613 *(gpio + 1) = gpfsel1_o;
614 *(gpio + 2) = gpfsel2_o;
616 *(gpio + 7) = addr_h_s;
617 *(gpio + 10) = addr_h_r;
621 *(gpio + 7) = addr_l_s;
622 *(gpio + 10) = addr_l_r;
627 *(gpio + 7) = data_s;
628 *(gpio + 10) = data_r;
633 *(gpio + 1) = gpfsel1;
634 *(gpio + 2) = gpfsel2;
635 while ((GET_GPIO(0)));
636 // asm volatile ("dmb" ::: "memory");
641 uint32_t read16(uint32_t address)
644 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
645 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
646 uint32_t addr_l_s = (address >> 16) << 8;
647 uint32_t addr_l_r = (~address >> 16) << 8;
649 // asm volatile ("dmb" ::: "memory");
653 *(gpio + 1) = gpfsel1_o;
654 *(gpio + 2) = gpfsel2_o;
656 *(gpio + 7) = addr_h_s;
657 *(gpio + 10) = addr_h_r;
661 *(gpio + 7) = addr_l_s;
662 *(gpio + 10) = addr_l_r;
670 *(gpio + 1) = gpfsel1;
671 *(gpio + 2) = gpfsel2;
674 while (!(GET_GPIO(0)));
676 asm volatile ("nop" ::);
677 asm volatile ("nop" ::);
678 asm volatile ("nop" ::);
681 // asm volatile ("dmb" ::: "memory");
682 return (val >>8)&0xffff;
686 uint32_t read8(uint32_t address)
689 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
690 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
691 uint32_t addr_l_s = (address >> 16) << 8;
692 uint32_t addr_l_r = (~address >> 16) << 8;
694 // asm volatile ("dmb" ::: "memory");
697 *(gpio + 1) = gpfsel1_o;
698 *(gpio + 2) = gpfsel2_o;
700 *(gpio + 7) = addr_h_s;
701 *(gpio + 10) = addr_h_r;
705 *(gpio + 7) = addr_l_s;
706 *(gpio + 10) = addr_l_r;
713 *(gpio + 1) = gpfsel1;
714 *(gpio + 2) = gpfsel2;
717 while (!(GET_GPIO(0)));
719 asm volatile ("nop" ::);
720 asm volatile ("nop" ::);
721 asm volatile ("nop" ::);
724 // asm volatile ("dmb" ::: "memory");
726 val = (val >>8)&0xffff;
727 if ((address & 1) == 0)
728 val = (val >> 8) & 0xff ; //EVEN, A0=0,UDS
730 val = val & 0xff ; //ODD , A0=1,LDS
736 /******************************************************/
738 void write_reg(unsigned int value)
740 asm volatile ("dmb" ::: "memory");
742 asm volatile ("nop" ::);
743 asm volatile ("nop" ::);
744 asm volatile ("nop" ::);
745 //Write Status register
751 *(gpio + 1) = gpfsel1_o;
752 *(gpio + 2) = gpfsel2_o;
753 *(gpio + 7) = (value & 0xffff) << 8;
754 *(gpio + 10) = (~value & 0xffff) << 8;
756 GPIO_CLR = 1 << 7; //delay
761 *(gpio + 1) = gpfsel1;
762 *(gpio + 2) = gpfsel2;
763 asm volatile ("dmb" ::: "memory");
767 uint16_t read_reg(void)
771 asm volatile ("dmb" ::: "memory");
773 asm volatile ("nop" ::);
774 asm volatile ("nop" ::);
775 asm volatile ("nop" ::);
778 *(gpio + 1) = gpfsel1;
779 *(gpio + 2) = gpfsel2;
782 GPIO_CLR = 1 << 6; //delay
785 asm volatile ("nop" ::);
786 asm volatile ("nop" ::);
787 asm volatile ("nop" ::);
790 asm volatile ("dmb" ::: "memory");
792 return (uint16_t)(val >> 8);
797 // Set up a memory regions to access GPIO
802 if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
803 printf("can't open /dev/mem \n");
809 NULL, //Any adddress in our space will do
810 BCM2708_PERI_SIZE, //Map length
811 PROT_READ|PROT_WRITE,// Enable reading & writting to mapped memory
812 MAP_SHARED, //Shared with other processes
813 mem_fd, //File to map
814 BCM2708_PERI_BASE //Offset to GPIO peripheral
817 close(mem_fd); //No need to keep mem_fd open after mmap
819 if (gpio_map == MAP_FAILED) {
820 printf("gpio mmap error %d\n", (int)gpio_map);//errno also set!
824 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR/4;
825 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR/4;