6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright Karl Stenerud. All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
29 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 /* Special thanks to Bart Trzynadlowski for his insight into the
36 * undocumented features of this chip:
38 * http://dynarec.com/~bart/files/68knotes.txt
42 /* Input file for m68kmake
43 * -----------------------
45 * All sections begin with 80 X's in a row followed by an end-of-line
47 * After this, m68kmake will expect to find one of the following section
49 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
50 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
51 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
52 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
53 * M68KMAKE_TABLE_BODY - the table itself
54 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
55 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
56 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
58 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
59 * M68KMAKE_TABLE_BODY must be second last in the file.
61 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
62 * primitives themselves. Each opcode handler begins with:
63 * M68KMAKE_OP(A, B, C, D)
65 * where A is the opcode handler name, B is the size of the operation,
66 * C denotes any special processing mode, and D denotes a specific
68 * For C and D where nothing is specified, use "."
71 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
72 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
73 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
75 * All opcode handler primitives end with a closing curly brace "}" at column 1
77 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
78 * and do not put a closing curly brace at column 1 unless it is
79 * marking the end of the handler!
81 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
82 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
83 * opcode handlers to handle variations in the opcode handler.
84 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
85 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
86 * be interpreted on instructions where the corresponding table entry
87 * specifies multiple effective addressing modes.
89 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
91 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
92 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
93 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
96 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
97 M68KMAKE_PROTOTYPE_HEADER
99 #ifndef M68KOPS__HEADER
100 #define M68KOPS__HEADER
102 /* ======================================================================== */
103 /* ============================ OPCODE HANDLERS =========================== */
104 /* ======================================================================== */
108 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
109 M68KMAKE_PROTOTYPE_FOOTER
112 /* Build the opcode handler table */
113 void m68ki_build_opcode_table(void);
115 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
116 extern unsigned char m68ki_cycles[][0x10000];
119 /* ======================================================================== */
120 /* ============================== END OF FILE ============================= */
121 /* ======================================================================== */
123 #endif /* M68KOPS__HEADER */
127 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
128 M68KMAKE_TABLE_HEADER
130 /* ======================================================================== */
131 /* ========================= OPCODE TABLE BUILDER ========================= */
132 /* ======================================================================== */
137 #define NUM_CPU_TYPES 5
139 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
140 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
142 /* This is used to generate the opcode handler jump table */
145 void (*opcode_handler)(void); /* handler function */
146 unsigned int mask; /* mask on opcode */
147 unsigned int match; /* what to match after masking */
148 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
149 } opcode_handler_struct;
152 /* Opcode handler table */
153 static const opcode_handler_struct m68k_opcode_handler_table[] =
155 /* function mask match 000 010 020 040 */
159 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
160 M68KMAKE_TABLE_FOOTER
162 {0, 0, 0, {0, 0, 0, 0, 0}}
166 /* Build the opcode handler jump table */
167 void m68ki_build_opcode_table(void)
169 const opcode_handler_struct *ostruct;
176 for(i = 0; i < 0x10000; i++)
178 /* default to illegal */
179 m68ki_instruction_jump_table[i] = m68k_op_illegal;
180 for(k=0;k<NUM_CPU_TYPES;k++)
181 m68ki_cycles[k][i] = 0;
184 ostruct = m68k_opcode_handler_table;
185 while(ostruct->mask != 0xff00)
187 for(i = 0;i < 0x10000;i++)
189 if((i & ostruct->mask) == ostruct->match)
191 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
192 for(k=0;k<NUM_CPU_TYPES;k++)
193 m68ki_cycles[k][i] = ostruct->cycles[k];
198 while(ostruct->mask == 0xff00)
200 for(i = 0;i <= 0xff;i++)
202 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
203 for(k=0;k<NUM_CPU_TYPES;k++)
204 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
208 while(ostruct->mask == 0xf1f8)
214 instr = ostruct->match | (i << 9) | j;
215 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
216 for(k=0;k<NUM_CPU_TYPES;k++)
217 m68ki_cycles[k][instr] = ostruct->cycles[k];
218 // For all shift operations with known shift distance (encoded in instruction word)
219 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
221 // On the 68000 and 68010 shift distance affect execution time.
222 // Add the cycle cost of shifting; 2 times the shift distance
223 cycle_cost = ((((i-1)&7)+1)<<1);
224 m68ki_cycles[0][instr] += cycle_cost;
225 m68ki_cycles[1][instr] += cycle_cost;
226 // On the 68020 shift distance does not affect execution time
227 m68ki_cycles[2][instr] += 0;
233 while(ostruct->mask == 0xfff0)
235 for(i = 0;i <= 0x0f;i++)
237 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
238 for(k=0;k<NUM_CPU_TYPES;k++)
239 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
243 while(ostruct->mask == 0xf1ff)
245 for(i = 0;i <= 0x07;i++)
247 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
248 for(k=0;k<NUM_CPU_TYPES;k++)
249 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
253 while(ostruct->mask == 0xfff8)
255 for(i = 0;i <= 0x07;i++)
257 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
258 for(k=0;k<NUM_CPU_TYPES;k++)
259 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
263 while(ostruct->mask == 0xffff)
265 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
266 for(k=0;k<NUM_CPU_TYPES;k++)
267 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
273 /* ======================================================================== */
274 /* ============================== END OF FILE ============================= */
275 /* ======================================================================== */
279 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
280 M68KMAKE_OPCODE_HANDLER_HEADER
284 extern void m68040_fpu_op0(void);
285 extern void m68040_fpu_op1(void);
286 extern void m68881_mmu_ops();
287 extern void m68881_ftrap();
289 /* ======================================================================== */
290 /* ========================= INSTRUCTION HANDLERS ========================= */
291 /* ======================================================================== */
295 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
296 M68KMAKE_OPCODE_HANDLER_FOOTER
298 /* ======================================================================== */
299 /* ============================== END OF FILE ============================= */
300 /* ======================================================================== */
304 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
307 The following table is arranged as follows:
309 name: Opcode mnemonic
313 spec proc: Special processing mode:
317 rr: register to register
319 er: effective address to register
320 re: register to effective address
321 dd: data register to data register
322 da: data register to address register
323 aa: address register to address register
324 cr: control register to register
325 rc: register to control register
326 toc: to condition code register
327 tos: to status register
328 tou: to user stack pointer
329 frc: from condition code register
330 frs: from status register
331 fru: from user stack pointer
332 * for move.x, the special processing mode is a specific
333 destination effective addressing mode.
335 spec ea: Specific effective addressing mode:
340 ai: address register indirect
341 pi: address register indirect with postincrement
342 pd: address register indirect with predecrement
343 di: address register indirect with displacement
344 ix: address register indirect with index
345 aw: absolute word address
346 al: absolute long address
347 pcdi: program counter relative with displacement
348 pcix: program counter relative with index
349 a7: register specified in instruction is A7
350 ax7: register field X of instruction is A7
351 ay7: register field Y of instruction is A7
352 axy7: register fields X and Y of instruction are A7
354 bit pattern: Pattern to recognize this opcode. "." means don't care.
356 allowed ea: List of allowed addressing modes:
358 A: address register indirect
359 +: ARI (address register indirect) with postincrement
360 -: ARI with predecrement
361 D: ARI with displacement
363 W: absolute word address
364 L: absolute long address
365 d: program counter indirect with displacement
366 x: program counter indirect with index
368 mode: CPU operating mode for each cpu type. U = user or supervisor,
369 S = supervisor only, "." = opcode not present.
371 cpu cycles: Base number of cycles required to execute this opcode on the
373 Use "." if CPU does not have this opcode.
377 spec spec allowed ea mode cpu cycles
378 name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments
379 ====== ==== ==== ==== ================ ========== = = = = = === === === === === =============
381 1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4
382 1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4
383 040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0
384 040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0
385 abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4
386 abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16
387 abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16
388 abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16
389 abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16
390 add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2
391 add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
392 add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2
393 add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2
394 add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
395 add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2
396 add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2
397 add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
398 add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4
399 add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4
400 add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4
401 adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2
402 adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2
403 adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
404 adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2
405 adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2
406 adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
407 addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2
408 addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4
409 addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2
410 addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4
411 addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2
412 addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4
413 addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2
414 addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4
415 addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2
416 addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2
417 addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4
418 addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2
419 addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2
420 addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4
421 addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2
422 addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2
423 addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2
424 addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12
425 addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12
426 addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12
427 addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12
428 addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12
429 addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12
430 and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2
431 and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
432 and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2
433 and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
434 and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2
435 and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
436 and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4
437 and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4
438 and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4
439 andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12
440 andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12
441 andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2
442 andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4
443 andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2
444 andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4
445 andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2
446 andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4
447 asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6
448 asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6
449 asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6
450 asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6
451 asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6
452 asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6
453 asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5
454 asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8
455 asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8
456 asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8
457 asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8
458 asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8
459 asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8
460 asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6
461 bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6
462 bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6
463 bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6
464 bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4
465 bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4
466 bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4
467 bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4
468 bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4
469 bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4
470 bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4
471 bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4
472 bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct
473 bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20
474 bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12
475 bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20
476 bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8
477 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15
478 bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8
479 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15
480 bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18
481 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28
482 bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10
483 bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17
484 bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12
485 bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20
486 bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6
487 bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13
488 bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10
489 bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10
490 bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10
491 bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10
492 bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4
493 bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4
494 bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4
495 bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4
496 bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7
497 bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7
498 bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7
499 btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4
500 btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4
501 btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4
502 btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4
503 callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated
504 cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12
505 cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12
506 cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12
507 cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12
508 cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12
509 chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8
510 chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8
511 chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8
512 chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8
513 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23
514 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23
515 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18
516 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23
517 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23
518 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18
519 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23
520 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23
521 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18
522 clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2
523 clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4
524 clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2
525 clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4
526 clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2
527 clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4
528 cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2
529 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
530 cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2
531 cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2
532 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
533 cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2
534 cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2
535 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
536 cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4
537 cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4
538 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4
539 cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4
540 cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4
541 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4
542 cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2
543 cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2
544 cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7
545 cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9
546 cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2
547 cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2
548 cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7
549 cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9
550 cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2
551 cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2
552 cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7
553 cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9
554 cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9
555 cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9
556 cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9
557 cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9
558 cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9
559 cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9
560 cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated
561 cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated
562 cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated
563 cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated
564 cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated
565 ftrapcc 32 . . 1111001001111... .......... . . U U . . . 4 4 .
566 dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6
567 dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6
568 dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6
569 divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56
570 divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56
571 divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44
572 divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44
573 divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84
574 divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84
575 eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2
576 eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4
577 eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2
578 eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4
579 eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2
580 eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4
581 eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12
582 eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12
583 eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2
584 eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4
585 eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2
586 eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4
587 eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2
588 eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4
589 exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2
590 exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2
591 exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2
592 ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4
593 ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4
594 extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4
595 illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4
596 jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0
597 jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0
598 lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2
599 link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5
600 link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5
601 link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6
602 link 32 . . 0100100000001... .......... . . U U U . . 6 6 6
603 lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4
604 lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4
605 lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4
606 lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6
607 lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6
608 lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6
609 lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5
610 lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4
611 lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4
612 lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4
613 lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6
614 lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6
615 lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6
616 lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5
617 move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2
618 move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
619 move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4
620 move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
621 move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4
622 move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
623 move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4
624 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4
625 move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5
626 move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
627 move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5
628 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5
629 move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5
630 move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
631 move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7
632 move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
633 move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4
634 move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
635 move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6
636 move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
637 move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2
638 move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2
639 move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
640 move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4
641 move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4
642 move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4
643 move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4
644 move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4
645 move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4
646 move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5
647 move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5
648 move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5
649 move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5
650 move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5
651 move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5
652 move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7
653 move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7
654 move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7
655 move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4
656 move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4
657 move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4
658 move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6
659 move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6
660 move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6
661 move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2
662 move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2
663 move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
664 move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4
665 move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4
666 move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4
667 move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4
668 move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4
669 move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4
670 move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5
671 move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5
672 move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5
673 move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5
674 move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5
675 move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5
676 move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7
677 move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7
678 move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7
679 move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4
680 move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4
681 move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4
682 move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6
683 move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6
684 move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6
685 movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2
686 movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2
687 movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
688 movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2
689 movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2
690 movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
691 move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4
692 move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4
693 move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4
694 move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4
695 move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000
696 move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000
697 move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8
698 move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8
699 move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2
700 move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2
701 movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6
702 movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12
703 movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4
704 movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4
705 movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4
706 movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4
707 movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8
708 movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9
709 movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11
710 movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8
711 movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8
712 movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9
713 movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11
714 movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8
715 movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12
716 movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18
717 movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11
718 movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17
719 moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2
720 moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5
721 moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5
722 moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5
723 move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing
724 muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27
725 muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27
726 mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27
727 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27
728 mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43
729 mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43
730 nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6
731 nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6
732 neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2
733 neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4
734 neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2
735 neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4
736 neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2
737 neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4
738 negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2
739 negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4
740 negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2
741 negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4
742 negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2
743 negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4
744 nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2
745 not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2
746 not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4
747 not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2
748 not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4
749 not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2
750 not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4
751 or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2
752 or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
753 or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2
754 or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
755 or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2
756 or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
757 or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4
758 or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4
759 or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4
760 ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12
761 ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12
762 ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2
763 ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4
764 ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2
765 ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4
766 ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2
767 ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4
768 pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6
769 pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13
770 pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13
771 pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13
772 pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13
773 pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5
774 pflush 32 . . 1111010100011000 .......... . . . . S . . . . 4 TODO: correct timing
775 pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8
776 reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0
777 ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8
778 ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8
779 ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8
780 ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8
781 ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8
782 ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8
783 ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7
784 rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8
785 rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8
786 rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8
787 rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8
788 rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8
789 rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8
790 rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7
791 roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12
792 roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12
793 roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12
794 roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12
795 roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12
796 roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12
797 roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5
798 roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12
799 roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12
800 roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12
801 roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12
802 roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12
803 roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12
804 roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5
805 rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10
806 rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated
807 rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated
808 rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14
809 rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10
810 sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4
811 sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16
812 sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16
813 sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16
814 sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16
815 st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4
816 st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6
817 sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4
818 sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6
819 scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4
820 scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6
821 stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8
822 sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2
823 sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2
824 sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2
825 sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2
826 sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2
827 sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2
828 sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2
829 sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2
830 sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4
831 sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4
832 sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4
833 suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2
834 suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2
835 suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2
836 suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2
837 suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2
838 suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2
839 subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2
840 subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4
841 subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2
842 subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4
843 subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2
844 subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4
845 subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2
846 subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4
847 subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2
848 subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2
849 subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4
850 subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2
851 subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2
852 subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4
853 subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2
854 subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2
855 subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2
856 subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12
857 subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12
858 subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12
859 subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12
860 subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12
861 subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12
862 swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4
863 tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4
864 tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12
865 trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4
866 trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4
867 trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6
868 trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8
869 trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4
870 trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6
871 trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8
872 trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4
873 trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6
874 trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8
875 trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4
876 tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2
877 tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2
878 tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7
879 tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9
880 tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6
881 tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2
882 tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2
883 tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2
884 tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7
885 tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9
886 tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6
887 tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2
888 tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2
889 tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2
890 tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7
891 tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9
892 tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6
893 unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6
894 unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6
895 unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8
896 unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13
897 unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13
898 unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13
899 unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13
903 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
904 M68KMAKE_OPCODE_HANDLER_BODY
906 M68KMAKE_OP(1010, 0, ., .)
908 m68ki_exception_1010();
912 M68KMAKE_OP(1111, 0, ., .)
914 m68ki_exception_1111();
918 M68KMAKE_OP(040fpu0, 32, ., .)
920 // printf("FPU 040fpu0 HAS_FPU=%d\n",!!HAS_FPU);
926 m68ki_exception_1111();
930 M68KMAKE_OP(040fpu1, 32, ., .)
932 // printf("FPU 040fpu1 HAS_FPU=%d\n",!!HAS_FPU);
938 m68ki_exception_1111();
943 M68KMAKE_OP(abcd, 8, rr, .)
948 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
950 FLAG_V = ~res; /* Undefined V behavior */
954 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
955 FLAG_X = FLAG_C = (res > 0x99) << 8;
959 FLAG_V &= res; /* Undefined V behavior part II */
960 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
962 res = MASK_OUT_ABOVE_8(res);
965 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
969 M68KMAKE_OP(abcd, 8, mm, ax7)
971 uint src = OPER_AY_PD_8();
972 uint ea = EA_A7_PD_8();
973 uint dst = m68ki_read_8(ea);
974 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
976 FLAG_V = ~res; /* Undefined V behavior */
980 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
981 FLAG_X = FLAG_C = (res > 0x99) << 8;
985 FLAG_V &= res; /* Undefined V behavior part II */
986 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
988 res = MASK_OUT_ABOVE_8(res);
991 m68ki_write_8(ea, res);
995 M68KMAKE_OP(abcd, 8, mm, ay7)
997 uint src = OPER_A7_PD_8();
998 uint ea = EA_AX_PD_8();
999 uint dst = m68ki_read_8(ea);
1000 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1002 FLAG_V = ~res; /* Undefined V behavior */
1006 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1007 FLAG_X = FLAG_C = (res > 0x99) << 8;
1011 FLAG_V &= res; /* Undefined V behavior part II */
1012 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1014 res = MASK_OUT_ABOVE_8(res);
1017 m68ki_write_8(ea, res);
1021 M68KMAKE_OP(abcd, 8, mm, axy7)
1023 uint src = OPER_A7_PD_8();
1024 uint ea = EA_A7_PD_8();
1025 uint dst = m68ki_read_8(ea);
1026 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1028 FLAG_V = ~res; /* Undefined V behavior */
1032 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1033 FLAG_X = FLAG_C = (res > 0x99) << 8;
1037 FLAG_V &= res; /* Undefined V behavior part II */
1038 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1040 res = MASK_OUT_ABOVE_8(res);
1043 m68ki_write_8(ea, res);
1047 M68KMAKE_OP(abcd, 8, mm, .)
1049 uint src = OPER_AY_PD_8();
1050 uint ea = EA_AX_PD_8();
1051 uint dst = m68ki_read_8(ea);
1052 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1054 FLAG_V = ~res; /* Undefined V behavior */
1058 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1059 FLAG_X = FLAG_C = (res > 0x99) << 8;
1063 FLAG_V &= res; /* Undefined V behavior part II */
1064 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1066 res = MASK_OUT_ABOVE_8(res);
1069 m68ki_write_8(ea, res);
1073 M68KMAKE_OP(add, 8, er, d)
1076 uint src = MASK_OUT_ABOVE_8(DY);
1077 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1078 uint res = src + dst;
1080 FLAG_N = NFLAG_8(res);
1081 FLAG_V = VFLAG_ADD_8(src, dst, res);
1082 FLAG_X = FLAG_C = CFLAG_8(res);
1083 FLAG_Z = MASK_OUT_ABOVE_8(res);
1085 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1089 M68KMAKE_OP(add, 8, er, .)
1092 uint src = M68KMAKE_GET_OPER_AY_8;
1093 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1094 uint res = src + dst;
1096 FLAG_N = NFLAG_8(res);
1097 FLAG_V = VFLAG_ADD_8(src, dst, res);
1098 FLAG_X = FLAG_C = CFLAG_8(res);
1099 FLAG_Z = MASK_OUT_ABOVE_8(res);
1101 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1105 M68KMAKE_OP(add, 16, er, d)
1108 uint src = MASK_OUT_ABOVE_16(DY);
1109 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1110 uint res = src + dst;
1112 FLAG_N = NFLAG_16(res);
1113 FLAG_V = VFLAG_ADD_16(src, dst, res);
1114 FLAG_X = FLAG_C = CFLAG_16(res);
1115 FLAG_Z = MASK_OUT_ABOVE_16(res);
1117 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1121 M68KMAKE_OP(add, 16, er, a)
1124 uint src = MASK_OUT_ABOVE_16(AY);
1125 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1126 uint res = src + dst;
1128 FLAG_N = NFLAG_16(res);
1129 FLAG_V = VFLAG_ADD_16(src, dst, res);
1130 FLAG_X = FLAG_C = CFLAG_16(res);
1131 FLAG_Z = MASK_OUT_ABOVE_16(res);
1133 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1137 M68KMAKE_OP(add, 16, er, .)
1140 uint src = M68KMAKE_GET_OPER_AY_16;
1141 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1142 uint res = src + dst;
1144 FLAG_N = NFLAG_16(res);
1145 FLAG_V = VFLAG_ADD_16(src, dst, res);
1146 FLAG_X = FLAG_C = CFLAG_16(res);
1147 FLAG_Z = MASK_OUT_ABOVE_16(res);
1149 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1153 M68KMAKE_OP(add, 32, er, d)
1158 uint res = src + dst;
1160 FLAG_N = NFLAG_32(res);
1161 FLAG_V = VFLAG_ADD_32(src, dst, res);
1162 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1163 FLAG_Z = MASK_OUT_ABOVE_32(res);
1169 M68KMAKE_OP(add, 32, er, a)
1174 uint res = src + dst;
1176 FLAG_N = NFLAG_32(res);
1177 FLAG_V = VFLAG_ADD_32(src, dst, res);
1178 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1179 FLAG_Z = MASK_OUT_ABOVE_32(res);
1185 M68KMAKE_OP(add, 32, er, .)
1188 uint src = M68KMAKE_GET_OPER_AY_32;
1190 uint res = src + dst;
1192 FLAG_N = NFLAG_32(res);
1193 FLAG_V = VFLAG_ADD_32(src, dst, res);
1194 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1195 FLAG_Z = MASK_OUT_ABOVE_32(res);
1201 M68KMAKE_OP(add, 8, re, .)
1203 uint ea = M68KMAKE_GET_EA_AY_8;
1204 uint src = MASK_OUT_ABOVE_8(DX);
1205 uint dst = m68ki_read_8(ea);
1206 uint res = src + dst;
1208 FLAG_N = NFLAG_8(res);
1209 FLAG_V = VFLAG_ADD_8(src, dst, res);
1210 FLAG_X = FLAG_C = CFLAG_8(res);
1211 FLAG_Z = MASK_OUT_ABOVE_8(res);
1213 m68ki_write_8(ea, FLAG_Z);
1217 M68KMAKE_OP(add, 16, re, .)
1219 uint ea = M68KMAKE_GET_EA_AY_16;
1220 uint src = MASK_OUT_ABOVE_16(DX);
1221 uint dst = m68ki_read_16(ea);
1222 uint res = src + dst;
1224 FLAG_N = NFLAG_16(res);
1225 FLAG_V = VFLAG_ADD_16(src, dst, res);
1226 FLAG_X = FLAG_C = CFLAG_16(res);
1227 FLAG_Z = MASK_OUT_ABOVE_16(res);
1229 m68ki_write_16(ea, FLAG_Z);
1233 M68KMAKE_OP(add, 32, re, .)
1235 uint ea = M68KMAKE_GET_EA_AY_32;
1237 uint dst = m68ki_read_32(ea);
1238 uint res = src + dst;
1240 FLAG_N = NFLAG_32(res);
1241 FLAG_V = VFLAG_ADD_32(src, dst, res);
1242 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1243 FLAG_Z = MASK_OUT_ABOVE_32(res);
1245 m68ki_write_32(ea, FLAG_Z);
1249 M68KMAKE_OP(adda, 16, ., d)
1253 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1257 M68KMAKE_OP(adda, 16, ., a)
1261 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1265 M68KMAKE_OP(adda, 16, ., .)
1268 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1270 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1274 M68KMAKE_OP(adda, 32, ., d)
1278 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1282 M68KMAKE_OP(adda, 32, ., a)
1286 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1290 M68KMAKE_OP(adda, 32, ., .)
1292 uint src = M68KMAKE_GET_OPER_AY_32;
1295 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1299 M68KMAKE_OP(addi, 8, ., d)
1302 uint src = OPER_I_8();
1303 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1304 uint res = src + dst;
1306 FLAG_N = NFLAG_8(res);
1307 FLAG_V = VFLAG_ADD_8(src, dst, res);
1308 FLAG_X = FLAG_C = CFLAG_8(res);
1309 FLAG_Z = MASK_OUT_ABOVE_8(res);
1311 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1315 M68KMAKE_OP(addi, 8, ., .)
1317 uint src = OPER_I_8();
1318 uint ea = M68KMAKE_GET_EA_AY_8;
1319 uint dst = m68ki_read_8(ea);
1320 uint res = src + dst;
1322 FLAG_N = NFLAG_8(res);
1323 FLAG_V = VFLAG_ADD_8(src, dst, res);
1324 FLAG_X = FLAG_C = CFLAG_8(res);
1325 FLAG_Z = MASK_OUT_ABOVE_8(res);
1327 m68ki_write_8(ea, FLAG_Z);
1331 M68KMAKE_OP(addi, 16, ., d)
1334 uint src = OPER_I_16();
1335 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1336 uint res = src + dst;
1338 FLAG_N = NFLAG_16(res);
1339 FLAG_V = VFLAG_ADD_16(src, dst, res);
1340 FLAG_X = FLAG_C = CFLAG_16(res);
1341 FLAG_Z = MASK_OUT_ABOVE_16(res);
1343 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1347 M68KMAKE_OP(addi, 16, ., .)
1349 uint src = OPER_I_16();
1350 uint ea = M68KMAKE_GET_EA_AY_16;
1351 uint dst = m68ki_read_16(ea);
1352 uint res = src + dst;
1354 FLAG_N = NFLAG_16(res);
1355 FLAG_V = VFLAG_ADD_16(src, dst, res);
1356 FLAG_X = FLAG_C = CFLAG_16(res);
1357 FLAG_Z = MASK_OUT_ABOVE_16(res);
1359 m68ki_write_16(ea, FLAG_Z);
1363 M68KMAKE_OP(addi, 32, ., d)
1366 uint src = OPER_I_32();
1368 uint res = src + dst;
1370 FLAG_N = NFLAG_32(res);
1371 FLAG_V = VFLAG_ADD_32(src, dst, res);
1372 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1373 FLAG_Z = MASK_OUT_ABOVE_32(res);
1379 M68KMAKE_OP(addi, 32, ., .)
1381 uint src = OPER_I_32();
1382 uint ea = M68KMAKE_GET_EA_AY_32;
1383 uint dst = m68ki_read_32(ea);
1384 uint res = src + dst;
1386 FLAG_N = NFLAG_32(res);
1387 FLAG_V = VFLAG_ADD_32(src, dst, res);
1388 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1389 FLAG_Z = MASK_OUT_ABOVE_32(res);
1391 m68ki_write_32(ea, FLAG_Z);
1395 M68KMAKE_OP(addq, 8, ., d)
1398 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1399 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1400 uint res = src + dst;
1402 FLAG_N = NFLAG_8(res);
1403 FLAG_V = VFLAG_ADD_8(src, dst, res);
1404 FLAG_X = FLAG_C = CFLAG_8(res);
1405 FLAG_Z = MASK_OUT_ABOVE_8(res);
1407 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1411 M68KMAKE_OP(addq, 8, ., .)
1413 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1414 uint ea = M68KMAKE_GET_EA_AY_8;
1415 uint dst = m68ki_read_8(ea);
1416 uint res = src + dst;
1418 FLAG_N = NFLAG_8(res);
1419 FLAG_V = VFLAG_ADD_8(src, dst, res);
1420 FLAG_X = FLAG_C = CFLAG_8(res);
1421 FLAG_Z = MASK_OUT_ABOVE_8(res);
1423 m68ki_write_8(ea, FLAG_Z);
1427 M68KMAKE_OP(addq, 16, ., d)
1430 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1431 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1432 uint res = src + dst;
1434 FLAG_N = NFLAG_16(res);
1435 FLAG_V = VFLAG_ADD_16(src, dst, res);
1436 FLAG_X = FLAG_C = CFLAG_16(res);
1437 FLAG_Z = MASK_OUT_ABOVE_16(res);
1439 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1443 M68KMAKE_OP(addq, 16, ., a)
1447 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1451 M68KMAKE_OP(addq, 16, ., .)
1453 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1454 uint ea = M68KMAKE_GET_EA_AY_16;
1455 uint dst = m68ki_read_16(ea);
1456 uint res = src + dst;
1458 FLAG_N = NFLAG_16(res);
1459 FLAG_V = VFLAG_ADD_16(src, dst, res);
1460 FLAG_X = FLAG_C = CFLAG_16(res);
1461 FLAG_Z = MASK_OUT_ABOVE_16(res);
1463 m68ki_write_16(ea, FLAG_Z);
1467 M68KMAKE_OP(addq, 32, ., d)
1470 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1472 uint res = src + dst;
1474 FLAG_N = NFLAG_32(res);
1475 FLAG_V = VFLAG_ADD_32(src, dst, res);
1476 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1477 FLAG_Z = MASK_OUT_ABOVE_32(res);
1483 M68KMAKE_OP(addq, 32, ., a)
1487 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1491 M68KMAKE_OP(addq, 32, ., .)
1493 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1494 uint ea = M68KMAKE_GET_EA_AY_32;
1495 uint dst = m68ki_read_32(ea);
1496 uint res = src + dst;
1499 FLAG_N = NFLAG_32(res);
1500 FLAG_V = VFLAG_ADD_32(src, dst, res);
1501 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1502 FLAG_Z = MASK_OUT_ABOVE_32(res);
1504 m68ki_write_32(ea, FLAG_Z);
1508 M68KMAKE_OP(addx, 8, rr, .)
1511 uint src = MASK_OUT_ABOVE_8(DY);
1512 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1513 uint res = src + dst + XFLAG_AS_1();
1515 FLAG_N = NFLAG_8(res);
1516 FLAG_V = VFLAG_ADD_8(src, dst, res);
1517 FLAG_X = FLAG_C = CFLAG_8(res);
1519 res = MASK_OUT_ABOVE_8(res);
1522 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1526 M68KMAKE_OP(addx, 16, rr, .)
1529 uint src = MASK_OUT_ABOVE_16(DY);
1530 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1531 uint res = src + dst + XFLAG_AS_1();
1533 FLAG_N = NFLAG_16(res);
1534 FLAG_V = VFLAG_ADD_16(src, dst, res);
1535 FLAG_X = FLAG_C = CFLAG_16(res);
1537 res = MASK_OUT_ABOVE_16(res);
1540 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1544 M68KMAKE_OP(addx, 32, rr, .)
1549 uint res = src + dst + XFLAG_AS_1();
1551 FLAG_N = NFLAG_32(res);
1552 FLAG_V = VFLAG_ADD_32(src, dst, res);
1553 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1555 res = MASK_OUT_ABOVE_32(res);
1562 M68KMAKE_OP(addx, 8, mm, ax7)
1564 uint src = OPER_AY_PD_8();
1565 uint ea = EA_A7_PD_8();
1566 uint dst = m68ki_read_8(ea);
1567 uint res = src + dst + XFLAG_AS_1();
1569 FLAG_N = NFLAG_8(res);
1570 FLAG_V = VFLAG_ADD_8(src, dst, res);
1571 FLAG_X = FLAG_C = CFLAG_8(res);
1573 res = MASK_OUT_ABOVE_8(res);
1576 m68ki_write_8(ea, res);
1580 M68KMAKE_OP(addx, 8, mm, ay7)
1582 uint src = OPER_A7_PD_8();
1583 uint ea = EA_AX_PD_8();
1584 uint dst = m68ki_read_8(ea);
1585 uint res = src + dst + XFLAG_AS_1();
1587 FLAG_N = NFLAG_8(res);
1588 FLAG_V = VFLAG_ADD_8(src, dst, res);
1589 FLAG_X = FLAG_C = CFLAG_8(res);
1591 res = MASK_OUT_ABOVE_8(res);
1594 m68ki_write_8(ea, res);
1598 M68KMAKE_OP(addx, 8, mm, axy7)
1600 uint src = OPER_A7_PD_8();
1601 uint ea = EA_A7_PD_8();
1602 uint dst = m68ki_read_8(ea);
1603 uint res = src + dst + XFLAG_AS_1();
1605 FLAG_N = NFLAG_8(res);
1606 FLAG_V = VFLAG_ADD_8(src, dst, res);
1607 FLAG_X = FLAG_C = CFLAG_8(res);
1609 res = MASK_OUT_ABOVE_8(res);
1612 m68ki_write_8(ea, res);
1616 M68KMAKE_OP(addx, 8, mm, .)
1618 uint src = OPER_AY_PD_8();
1619 uint ea = EA_AX_PD_8();
1620 uint dst = m68ki_read_8(ea);
1621 uint res = src + dst + XFLAG_AS_1();
1623 FLAG_N = NFLAG_8(res);
1624 FLAG_V = VFLAG_ADD_8(src, dst, res);
1625 FLAG_X = FLAG_C = CFLAG_8(res);
1627 res = MASK_OUT_ABOVE_8(res);
1630 m68ki_write_8(ea, res);
1634 M68KMAKE_OP(addx, 16, mm, .)
1636 uint src = OPER_AY_PD_16();
1637 uint ea = EA_AX_PD_16();
1638 uint dst = m68ki_read_16(ea);
1639 uint res = src + dst + XFLAG_AS_1();
1641 FLAG_N = NFLAG_16(res);
1642 FLAG_V = VFLAG_ADD_16(src, dst, res);
1643 FLAG_X = FLAG_C = CFLAG_16(res);
1645 res = MASK_OUT_ABOVE_16(res);
1648 m68ki_write_16(ea, res);
1652 M68KMAKE_OP(addx, 32, mm, .)
1654 uint src = OPER_AY_PD_32();
1655 uint ea = EA_AX_PD_32();
1656 uint dst = m68ki_read_32(ea);
1657 uint res = src + dst + XFLAG_AS_1();
1659 FLAG_N = NFLAG_32(res);
1660 FLAG_V = VFLAG_ADD_32(src, dst, res);
1661 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1663 res = MASK_OUT_ABOVE_32(res);
1666 m68ki_write_32(ea, res);
1670 M68KMAKE_OP(and, 8, er, d)
1672 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1674 FLAG_N = NFLAG_8(FLAG_Z);
1675 FLAG_C = CFLAG_CLEAR;
1676 FLAG_V = VFLAG_CLEAR;
1680 M68KMAKE_OP(and, 8, er, .)
1682 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1684 FLAG_N = NFLAG_8(FLAG_Z);
1685 FLAG_C = CFLAG_CLEAR;
1686 FLAG_V = VFLAG_CLEAR;
1690 M68KMAKE_OP(and, 16, er, d)
1692 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1694 FLAG_N = NFLAG_16(FLAG_Z);
1695 FLAG_C = CFLAG_CLEAR;
1696 FLAG_V = VFLAG_CLEAR;
1700 M68KMAKE_OP(and, 16, er, .)
1702 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1704 FLAG_N = NFLAG_16(FLAG_Z);
1705 FLAG_C = CFLAG_CLEAR;
1706 FLAG_V = VFLAG_CLEAR;
1710 M68KMAKE_OP(and, 32, er, d)
1714 FLAG_N = NFLAG_32(FLAG_Z);
1715 FLAG_C = CFLAG_CLEAR;
1716 FLAG_V = VFLAG_CLEAR;
1720 M68KMAKE_OP(and, 32, er, .)
1722 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1724 FLAG_N = NFLAG_32(FLAG_Z);
1725 FLAG_C = CFLAG_CLEAR;
1726 FLAG_V = VFLAG_CLEAR;
1730 M68KMAKE_OP(and, 8, re, .)
1732 uint ea = M68KMAKE_GET_EA_AY_8;
1733 uint res = DX & m68ki_read_8(ea);
1735 FLAG_N = NFLAG_8(res);
1736 FLAG_C = CFLAG_CLEAR;
1737 FLAG_V = VFLAG_CLEAR;
1738 FLAG_Z = MASK_OUT_ABOVE_8(res);
1740 m68ki_write_8(ea, FLAG_Z);
1744 M68KMAKE_OP(and, 16, re, .)
1746 uint ea = M68KMAKE_GET_EA_AY_16;
1747 uint res = DX & m68ki_read_16(ea);
1749 FLAG_N = NFLAG_16(res);
1750 FLAG_C = CFLAG_CLEAR;
1751 FLAG_V = VFLAG_CLEAR;
1752 FLAG_Z = MASK_OUT_ABOVE_16(res);
1754 m68ki_write_16(ea, FLAG_Z);
1758 M68KMAKE_OP(and, 32, re, .)
1760 uint ea = M68KMAKE_GET_EA_AY_32;
1761 uint res = DX & m68ki_read_32(ea);
1763 FLAG_N = NFLAG_32(res);
1765 FLAG_C = CFLAG_CLEAR;
1766 FLAG_V = VFLAG_CLEAR;
1768 m68ki_write_32(ea, res);
1772 M68KMAKE_OP(andi, 8, ., d)
1774 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1776 FLAG_N = NFLAG_8(FLAG_Z);
1777 FLAG_C = CFLAG_CLEAR;
1778 FLAG_V = VFLAG_CLEAR;
1782 M68KMAKE_OP(andi, 8, ., .)
1784 uint src = OPER_I_8();
1785 uint ea = M68KMAKE_GET_EA_AY_8;
1786 uint res = src & m68ki_read_8(ea);
1788 FLAG_N = NFLAG_8(res);
1790 FLAG_C = CFLAG_CLEAR;
1791 FLAG_V = VFLAG_CLEAR;
1793 m68ki_write_8(ea, res);
1797 M68KMAKE_OP(andi, 16, ., d)
1799 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1801 FLAG_N = NFLAG_16(FLAG_Z);
1802 FLAG_C = CFLAG_CLEAR;
1803 FLAG_V = VFLAG_CLEAR;
1807 M68KMAKE_OP(andi, 16, ., .)
1809 uint src = OPER_I_16();
1810 uint ea = M68KMAKE_GET_EA_AY_16;
1811 uint res = src & m68ki_read_16(ea);
1813 FLAG_N = NFLAG_16(res);
1815 FLAG_C = CFLAG_CLEAR;
1816 FLAG_V = VFLAG_CLEAR;
1818 m68ki_write_16(ea, res);
1822 M68KMAKE_OP(andi, 32, ., d)
1824 FLAG_Z = DY &= (OPER_I_32());
1826 FLAG_N = NFLAG_32(FLAG_Z);
1827 FLAG_C = CFLAG_CLEAR;
1828 FLAG_V = VFLAG_CLEAR;
1832 M68KMAKE_OP(andi, 32, ., .)
1834 uint src = OPER_I_32();
1835 uint ea = M68KMAKE_GET_EA_AY_32;
1836 uint res = src & m68ki_read_32(ea);
1838 FLAG_N = NFLAG_32(res);
1840 FLAG_C = CFLAG_CLEAR;
1841 FLAG_V = VFLAG_CLEAR;
1843 m68ki_write_32(ea, res);
1847 M68KMAKE_OP(andi, 16, toc, .)
1849 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_8());
1853 M68KMAKE_OP(andi, 16, tos, .)
1857 uint src = OPER_I_16();
1858 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1859 m68ki_set_sr(m68ki_get_sr() & src);
1862 m68ki_exception_privilege_violation();
1866 M68KMAKE_OP(asr, 8, s, .)
1869 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1870 uint src = MASK_OUT_ABOVE_8(*r_dst);
1871 uint res = src >> shift;
1874 USE_CYCLES(shift<<CYC_SHIFT);
1877 res |= m68ki_shift_8_table[shift];
1879 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1881 FLAG_N = NFLAG_8(res);
1883 FLAG_V = VFLAG_CLEAR;
1884 FLAG_X = FLAG_C = src << (9-shift);
1888 M68KMAKE_OP(asr, 16, s, .)
1891 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1892 uint src = MASK_OUT_ABOVE_16(*r_dst);
1893 uint res = src >> shift;
1896 USE_CYCLES(shift<<CYC_SHIFT);
1899 res |= m68ki_shift_16_table[shift];
1901 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1903 FLAG_N = NFLAG_16(res);
1905 FLAG_V = VFLAG_CLEAR;
1906 FLAG_X = FLAG_C = src << (9-shift);
1910 M68KMAKE_OP(asr, 32, s, .)
1913 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1915 uint res = src >> shift;
1918 USE_CYCLES(shift<<CYC_SHIFT);
1921 res |= m68ki_shift_32_table[shift];
1925 FLAG_N = NFLAG_32(res);
1927 FLAG_V = VFLAG_CLEAR;
1928 FLAG_X = FLAG_C = src << (9-shift);
1932 M68KMAKE_OP(asr, 8, r, .)
1935 uint shift = DX & 0x3f;
1936 uint src = MASK_OUT_ABOVE_8(*r_dst);
1937 uint res = src >> shift;
1941 USE_CYCLES(shift<<CYC_SHIFT);
1946 res |= m68ki_shift_8_table[shift];
1948 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1950 FLAG_X = FLAG_C = src << (9-shift);
1951 FLAG_N = NFLAG_8(res);
1953 FLAG_V = VFLAG_CLEAR;
1963 FLAG_Z = ZFLAG_CLEAR;
1964 FLAG_V = VFLAG_CLEAR;
1968 *r_dst &= 0xffffff00;
1969 FLAG_C = CFLAG_CLEAR;
1970 FLAG_X = XFLAG_CLEAR;
1971 FLAG_N = NFLAG_CLEAR;
1973 FLAG_V = VFLAG_CLEAR;
1977 FLAG_C = CFLAG_CLEAR;
1978 FLAG_N = NFLAG_8(src);
1980 FLAG_V = VFLAG_CLEAR;
1984 M68KMAKE_OP(asr, 16, r, .)
1987 uint shift = DX & 0x3f;
1988 uint src = MASK_OUT_ABOVE_16(*r_dst);
1989 uint res = src >> shift;
1993 USE_CYCLES(shift<<CYC_SHIFT);
1998 res |= m68ki_shift_16_table[shift];
2000 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2002 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2003 FLAG_N = NFLAG_16(res);
2005 FLAG_V = VFLAG_CLEAR;
2015 FLAG_Z = ZFLAG_CLEAR;
2016 FLAG_V = VFLAG_CLEAR;
2020 *r_dst &= 0xffff0000;
2021 FLAG_C = CFLAG_CLEAR;
2022 FLAG_X = XFLAG_CLEAR;
2023 FLAG_N = NFLAG_CLEAR;
2025 FLAG_V = VFLAG_CLEAR;
2029 FLAG_C = CFLAG_CLEAR;
2030 FLAG_N = NFLAG_16(src);
2032 FLAG_V = VFLAG_CLEAR;
2036 M68KMAKE_OP(asr, 32, r, .)
2039 uint shift = DX & 0x3f;
2041 uint res = src >> shift;
2045 USE_CYCLES(shift<<CYC_SHIFT);
2050 res |= m68ki_shift_32_table[shift];
2054 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2055 FLAG_N = NFLAG_32(res);
2057 FLAG_V = VFLAG_CLEAR;
2063 *r_dst = 0xffffffff;
2067 FLAG_Z = ZFLAG_CLEAR;
2068 FLAG_V = VFLAG_CLEAR;
2073 FLAG_C = CFLAG_CLEAR;
2074 FLAG_X = XFLAG_CLEAR;
2075 FLAG_N = NFLAG_CLEAR;
2077 FLAG_V = VFLAG_CLEAR;
2081 FLAG_C = CFLAG_CLEAR;
2082 FLAG_N = NFLAG_32(src);
2084 FLAG_V = VFLAG_CLEAR;
2088 M68KMAKE_OP(asr, 16, ., .)
2090 uint ea = M68KMAKE_GET_EA_AY_16;
2091 uint src = m68ki_read_16(ea);
2092 uint res = src >> 1;
2097 m68ki_write_16(ea, res);
2099 FLAG_N = NFLAG_16(res);
2101 FLAG_V = VFLAG_CLEAR;
2102 FLAG_C = FLAG_X = src << 8;
2106 M68KMAKE_OP(asl, 8, s, .)
2109 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2110 uint src = MASK_OUT_ABOVE_8(*r_dst);
2111 uint res = MASK_OUT_ABOVE_8(src << shift);
2114 USE_CYCLES(shift<<CYC_SHIFT);
2116 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2118 FLAG_X = FLAG_C = src << shift;
2119 FLAG_N = NFLAG_8(res);
2121 src &= m68ki_shift_8_table[shift + 1];
2122 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2126 M68KMAKE_OP(asl, 16, s, .)
2129 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2130 uint src = MASK_OUT_ABOVE_16(*r_dst);
2131 uint res = MASK_OUT_ABOVE_16(src << shift);
2134 USE_CYCLES(shift<<CYC_SHIFT);
2136 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2138 FLAG_N = NFLAG_16(res);
2140 FLAG_X = FLAG_C = src >> (8-shift);
2141 src &= m68ki_shift_16_table[shift + 1];
2142 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2146 M68KMAKE_OP(asl, 32, s, .)
2149 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2151 uint res = MASK_OUT_ABOVE_32(src << shift);
2154 USE_CYCLES(shift<<CYC_SHIFT);
2158 FLAG_N = NFLAG_32(res);
2160 FLAG_X = FLAG_C = src >> (24-shift);
2161 src &= m68ki_shift_32_table[shift + 1];
2162 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2166 M68KMAKE_OP(asl, 8, r, .)
2169 uint shift = DX & 0x3f;
2170 uint src = MASK_OUT_ABOVE_8(*r_dst);
2171 uint res = MASK_OUT_ABOVE_8(src << shift);
2175 USE_CYCLES(shift<<CYC_SHIFT);
2179 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2180 FLAG_X = FLAG_C = src << shift;
2181 FLAG_N = NFLAG_8(res);
2183 src &= m68ki_shift_8_table[shift + 1];
2184 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2188 *r_dst &= 0xffffff00;
2189 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2190 FLAG_N = NFLAG_CLEAR;
2192 FLAG_V = (!(src == 0))<<7;
2196 FLAG_C = CFLAG_CLEAR;
2197 FLAG_N = NFLAG_8(src);
2199 FLAG_V = VFLAG_CLEAR;
2203 M68KMAKE_OP(asl, 16, r, .)
2206 uint shift = DX & 0x3f;
2207 uint src = MASK_OUT_ABOVE_16(*r_dst);
2208 uint res = MASK_OUT_ABOVE_16(src << shift);
2212 USE_CYCLES(shift<<CYC_SHIFT);
2216 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2217 FLAG_X = FLAG_C = (src << shift) >> 8;
2218 FLAG_N = NFLAG_16(res);
2220 src &= m68ki_shift_16_table[shift + 1];
2221 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2225 *r_dst &= 0xffff0000;
2226 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2227 FLAG_N = NFLAG_CLEAR;
2229 FLAG_V = (!(src == 0))<<7;
2233 FLAG_C = CFLAG_CLEAR;
2234 FLAG_N = NFLAG_16(src);
2236 FLAG_V = VFLAG_CLEAR;
2240 M68KMAKE_OP(asl, 32, r, .)
2243 uint shift = DX & 0x3f;
2245 uint res = MASK_OUT_ABOVE_32(src << shift);
2249 USE_CYCLES(shift<<CYC_SHIFT);
2254 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2255 FLAG_N = NFLAG_32(res);
2257 src &= m68ki_shift_32_table[shift + 1];
2258 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2263 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2264 FLAG_N = NFLAG_CLEAR;
2266 FLAG_V = (!(src == 0))<<7;
2270 FLAG_C = CFLAG_CLEAR;
2271 FLAG_N = NFLAG_32(src);
2273 FLAG_V = VFLAG_CLEAR;
2277 M68KMAKE_OP(asl, 16, ., .)
2279 uint ea = M68KMAKE_GET_EA_AY_16;
2280 uint src = m68ki_read_16(ea);
2281 uint res = MASK_OUT_ABOVE_16(src << 1);
2283 m68ki_write_16(ea, res);
2285 FLAG_N = NFLAG_16(res);
2287 FLAG_X = FLAG_C = src >> 7;
2289 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2293 M68KMAKE_OP(bcc, 8, ., .)
2297 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2298 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2301 USE_CYCLES(CYC_BCC_NOTAKE_B);
2305 M68KMAKE_OP(bcc, 16, ., .)
2309 uint offset = OPER_I_16();
2311 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2312 m68ki_branch_16(offset);
2316 USE_CYCLES(CYC_BCC_NOTAKE_W);
2320 M68KMAKE_OP(bcc, 32, ., .)
2322 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2326 uint offset = OPER_I_32();
2328 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2329 m68ki_branch_32(offset);
2339 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2340 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2343 USE_CYCLES(CYC_BCC_NOTAKE_B);
2348 M68KMAKE_OP(bchg, 32, r, d)
2351 uint mask = 1 << (DX & 0x1f);
2353 FLAG_Z = *r_dst & mask;
2358 M68KMAKE_OP(bchg, 8, r, .)
2360 uint ea = M68KMAKE_GET_EA_AY_8;
2361 uint src = m68ki_read_8(ea);
2362 uint mask = 1 << (DX & 7);
2364 FLAG_Z = src & mask;
2365 m68ki_write_8(ea, src ^ mask);
2369 M68KMAKE_OP(bchg, 32, s, d)
2372 uint mask = 1 << (OPER_I_8() & 0x1f);
2374 FLAG_Z = *r_dst & mask;
2379 M68KMAKE_OP(bchg, 8, s, .)
2381 uint mask = 1 << (OPER_I_8() & 7);
2382 uint ea = M68KMAKE_GET_EA_AY_8;
2383 uint src = m68ki_read_8(ea);
2385 FLAG_Z = src & mask;
2386 m68ki_write_8(ea, src ^ mask);
2390 M68KMAKE_OP(bclr, 32, r, d)
2393 uint mask = 1 << (DX & 0x1f);
2395 FLAG_Z = *r_dst & mask;
2400 M68KMAKE_OP(bclr, 8, r, .)
2402 uint ea = M68KMAKE_GET_EA_AY_8;
2403 uint src = m68ki_read_8(ea);
2404 uint mask = 1 << (DX & 7);
2406 FLAG_Z = src & mask;
2407 m68ki_write_8(ea, src & ~mask);
2411 M68KMAKE_OP(bclr, 32, s, d)
2414 uint mask = 1 << (OPER_I_8() & 0x1f);
2416 FLAG_Z = *r_dst & mask;
2421 M68KMAKE_OP(bclr, 8, s, .)
2423 uint mask = 1 << (OPER_I_8() & 7);
2424 uint ea = M68KMAKE_GET_EA_AY_8;
2425 uint src = m68ki_read_8(ea);
2427 FLAG_Z = src & mask;
2428 m68ki_write_8(ea, src & ~mask);
2432 M68KMAKE_OP(bfchg, 32, ., d)
2434 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2436 uint word2 = OPER_I_16();
2437 uint offset = (word2>>6)&31;
2444 offset = REG_D[offset&7];
2446 width = REG_D[width&7];
2449 width = ((width-1) & 31) + 1;
2451 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2452 mask = ROR_32(mask, offset);
2454 FLAG_N = NFLAG_32(*data<<offset);
2455 FLAG_Z = *data & mask;
2456 FLAG_V = VFLAG_CLEAR;
2457 FLAG_C = CFLAG_CLEAR;
2463 m68ki_exception_illegal();
2467 M68KMAKE_OP(bfchg, 32, ., .)
2469 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2471 uint word2 = OPER_I_16();
2472 sint offset = (word2>>6)&31;
2479 uint ea = M68KMAKE_GET_EA_AY_8;
2483 offset = MAKE_INT_32(REG_D[offset&7]);
2485 width = REG_D[width&7];
2487 /* Offset is signed so we have to use ugly math =( */
2495 width = ((width-1) & 31) + 1;
2497 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2498 mask_long = mask_base >> offset;
2500 data_long = m68ki_read_32(ea);
2501 FLAG_N = NFLAG_32(data_long << offset);
2502 FLAG_Z = data_long & mask_long;
2503 FLAG_V = VFLAG_CLEAR;
2504 FLAG_C = CFLAG_CLEAR;
2506 m68ki_write_32(ea, data_long ^ mask_long);
2508 if((width + offset) > 32)
2510 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2511 data_byte = m68ki_read_8(ea+4);
2512 FLAG_Z |= (data_byte & mask_byte);
2513 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2517 m68ki_exception_illegal();
2521 M68KMAKE_OP(bfclr, 32, ., d)
2523 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2525 uint word2 = OPER_I_16();
2526 uint offset = (word2>>6)&31;
2533 offset = REG_D[offset&7];
2535 width = REG_D[width&7];
2539 width = ((width-1) & 31) + 1;
2542 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2543 mask = ROR_32(mask, offset);
2545 FLAG_N = NFLAG_32(*data<<offset);
2546 FLAG_Z = *data & mask;
2547 FLAG_V = VFLAG_CLEAR;
2548 FLAG_C = CFLAG_CLEAR;
2554 m68ki_exception_illegal();
2558 M68KMAKE_OP(bfclr, 32, ., .)
2560 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2562 uint word2 = OPER_I_16();
2563 sint offset = (word2>>6)&31;
2570 uint ea = M68KMAKE_GET_EA_AY_8;
2574 offset = MAKE_INT_32(REG_D[offset&7]);
2576 width = REG_D[width&7];
2578 /* Offset is signed so we have to use ugly math =( */
2586 width = ((width-1) & 31) + 1;
2588 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2589 mask_long = mask_base >> offset;
2591 data_long = m68ki_read_32(ea);
2592 FLAG_N = NFLAG_32(data_long << offset);
2593 FLAG_Z = data_long & mask_long;
2594 FLAG_V = VFLAG_CLEAR;
2595 FLAG_C = CFLAG_CLEAR;
2597 m68ki_write_32(ea, data_long & ~mask_long);
2599 if((width + offset) > 32)
2601 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2602 data_byte = m68ki_read_8(ea+4);
2603 FLAG_Z |= (data_byte & mask_byte);
2604 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2608 m68ki_exception_illegal();
2612 M68KMAKE_OP(bfexts, 32, ., d)
2614 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2616 uint word2 = OPER_I_16();
2617 uint offset = (word2>>6)&31;
2623 offset = REG_D[offset&7];
2625 width = REG_D[width&7];
2628 width = ((width-1) & 31) + 1;
2630 data = ROL_32(data, offset);
2631 FLAG_N = NFLAG_32(data);
2632 data = MAKE_INT_32(data) >> (32 - width);
2635 FLAG_V = VFLAG_CLEAR;
2636 FLAG_C = CFLAG_CLEAR;
2638 REG_D[(word2>>12)&7] = data;
2642 m68ki_exception_illegal();
2646 M68KMAKE_OP(bfexts, 32, ., .)
2648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2650 uint word2 = OPER_I_16();
2651 sint offset = (word2>>6)&31;
2654 uint ea = M68KMAKE_GET_EA_AY_8;
2658 offset = MAKE_INT_32(REG_D[offset&7]);
2660 width = REG_D[width&7];
2662 /* Offset is signed so we have to use ugly math =( */
2670 width = ((width-1) & 31) + 1;
2672 data = m68ki_read_32(ea);
2674 data = MASK_OUT_ABOVE_32(data<<offset);
2676 if((offset+width) > 32)
2677 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2679 FLAG_N = NFLAG_32(data);
2680 data = MAKE_INT_32(data) >> (32 - width);
2683 FLAG_V = VFLAG_CLEAR;
2684 FLAG_C = CFLAG_CLEAR;
2686 REG_D[(word2 >> 12) & 7] = data;
2690 m68ki_exception_illegal();
2694 M68KMAKE_OP(bfextu, 32, ., d)
2696 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2698 uint word2 = OPER_I_16();
2699 uint offset = (word2>>6)&31;
2705 offset = REG_D[offset&7];
2707 width = REG_D[width&7];
2710 width = ((width-1) & 31) + 1;
2712 data = ROL_32(data, offset);
2713 FLAG_N = NFLAG_32(data);
2714 data >>= 32 - width;
2717 FLAG_V = VFLAG_CLEAR;
2718 FLAG_C = CFLAG_CLEAR;
2720 REG_D[(word2>>12)&7] = data;
2724 m68ki_exception_illegal();
2728 M68KMAKE_OP(bfextu, 32, ., .)
2730 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2732 uint word2 = OPER_I_16();
2733 sint offset = (word2>>6)&31;
2736 uint ea = M68KMAKE_GET_EA_AY_8;
2740 offset = MAKE_INT_32(REG_D[offset&7]);
2742 width = REG_D[width&7];
2744 /* Offset is signed so we have to use ugly math =( */
2752 width = ((width-1) & 31) + 1;
2754 data = m68ki_read_32(ea);
2755 data = MASK_OUT_ABOVE_32(data<<offset);
2757 if((offset+width) > 32)
2758 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2760 FLAG_N = NFLAG_32(data);
2761 data >>= (32 - width);
2764 FLAG_V = VFLAG_CLEAR;
2765 FLAG_C = CFLAG_CLEAR;
2767 REG_D[(word2 >> 12) & 7] = data;
2771 m68ki_exception_illegal();
2775 M68KMAKE_OP(bfffo, 32, ., d)
2777 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2779 uint word2 = OPER_I_16();
2780 uint offset = (word2>>6)&31;
2787 offset = REG_D[offset&7];
2789 width = REG_D[width&7];
2792 width = ((width-1) & 31) + 1;
2794 data = ROL_32(data, offset);
2795 FLAG_N = NFLAG_32(data);
2796 data >>= 32 - width;
2799 FLAG_V = VFLAG_CLEAR;
2800 FLAG_C = CFLAG_CLEAR;
2802 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2805 REG_D[(word2>>12)&7] = offset;
2809 m68ki_exception_illegal();
2813 M68KMAKE_OP(bfffo, 32, ., .)
2815 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2817 uint word2 = OPER_I_16();
2818 sint offset = (word2>>6)&31;
2823 uint ea = M68KMAKE_GET_EA_AY_8;
2827 offset = MAKE_INT_32(REG_D[offset&7]);
2829 width = REG_D[width&7];
2831 /* Offset is signed so we have to use ugly math =( */
2833 local_offset = offset % 8;
2834 if(local_offset < 0)
2839 width = ((width-1) & 31) + 1;
2841 data = m68ki_read_32(ea);
2842 data = MASK_OUT_ABOVE_32(data<<local_offset);
2844 if((local_offset+width) > 32)
2845 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2847 FLAG_N = NFLAG_32(data);
2848 data >>= (32 - width);
2851 FLAG_V = VFLAG_CLEAR;
2852 FLAG_C = CFLAG_CLEAR;
2854 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2857 REG_D[(word2>>12)&7] = offset;
2861 m68ki_exception_illegal();
2865 M68KMAKE_OP(bfins, 32, ., d)
2867 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2869 uint word2 = OPER_I_16();
2870 uint offset = (word2>>6)&31;
2874 uint64 insert = REG_D[(word2>>12)&7];
2878 offset = REG_D[offset&7];
2880 width = REG_D[width&7];
2884 width = ((width-1) & 31) + 1;
2887 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2888 mask = ROR_32(mask, offset);
2890 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2891 FLAG_N = NFLAG_32(insert);
2893 insert = ROR_32(insert, offset);
2895 FLAG_V = VFLAG_CLEAR;
2896 FLAG_C = CFLAG_CLEAR;
2903 m68ki_exception_illegal();
2907 M68KMAKE_OP(bfins, 32, ., .)
2909 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2911 uint word2 = OPER_I_16();
2912 sint offset = (word2>>6)&31;
2914 uint insert_base = REG_D[(word2>>12)&7];
2922 uint ea = M68KMAKE_GET_EA_AY_8;
2926 offset = MAKE_INT_32(REG_D[offset&7]);
2928 width = REG_D[width&7];
2930 /* Offset is signed so we have to use ugly math =( */
2938 width = ((width-1) & 31) + 1;
2940 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2941 mask_long = mask_base >> offset;
2943 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2944 FLAG_N = NFLAG_32(insert_base);
2945 FLAG_Z = insert_base;
2946 insert_long = insert_base >> offset;
2948 data_long = m68ki_read_32(ea);
2949 FLAG_V = VFLAG_CLEAR;
2950 FLAG_C = CFLAG_CLEAR;
2952 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2954 if((width + offset) > 32)
2956 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2957 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2958 data_byte = m68ki_read_8(ea+4);
2959 FLAG_Z |= (data_byte & mask_byte);
2960 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2964 m68ki_exception_illegal();
2968 M68KMAKE_OP(bfset, 32, ., d)
2970 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2972 uint word2 = OPER_I_16();
2973 uint offset = (word2>>6)&31;
2980 offset = REG_D[offset&7];
2982 width = REG_D[width&7];
2986 width = ((width-1) & 31) + 1;
2989 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2990 mask = ROR_32(mask, offset);
2992 FLAG_N = NFLAG_32(*data<<offset);
2993 FLAG_Z = *data & mask;
2994 FLAG_V = VFLAG_CLEAR;
2995 FLAG_C = CFLAG_CLEAR;
3001 m68ki_exception_illegal();
3005 M68KMAKE_OP(bfset, 32, ., .)
3007 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3009 uint word2 = OPER_I_16();
3010 sint offset = (word2>>6)&31;
3017 uint ea = M68KMAKE_GET_EA_AY_8;
3021 offset = MAKE_INT_32(REG_D[offset&7]);
3023 width = REG_D[width&7];
3025 /* Offset is signed so we have to use ugly math =( */
3033 width = ((width-1) & 31) + 1;
3036 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3037 mask_long = mask_base >> offset;
3039 data_long = m68ki_read_32(ea);
3040 FLAG_N = NFLAG_32(data_long << offset);
3041 FLAG_Z = data_long & mask_long;
3042 FLAG_V = VFLAG_CLEAR;
3043 FLAG_C = CFLAG_CLEAR;
3045 m68ki_write_32(ea, data_long | mask_long);
3047 if((width + offset) > 32)
3049 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3050 data_byte = m68ki_read_8(ea+4);
3051 FLAG_Z |= (data_byte & mask_byte);
3052 m68ki_write_8(ea+4, data_byte | mask_byte);
3056 m68ki_exception_illegal();
3060 M68KMAKE_OP(bftst, 32, ., d)
3062 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3064 uint word2 = OPER_I_16();
3065 uint offset = (word2>>6)&31;
3072 offset = REG_D[offset&7];
3074 width = REG_D[width&7];
3078 width = ((width-1) & 31) + 1;
3081 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3082 mask = ROR_32(mask, offset);
3084 FLAG_N = NFLAG_32(*data<<offset);
3085 FLAG_Z = *data & mask;
3086 FLAG_V = VFLAG_CLEAR;
3087 FLAG_C = CFLAG_CLEAR;
3091 m68ki_exception_illegal();
3095 M68KMAKE_OP(bftst, 32, ., .)
3097 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3099 uint word2 = OPER_I_16();
3100 sint offset = (word2>>6)&31;
3107 uint ea = M68KMAKE_GET_EA_AY_8;
3110 offset = MAKE_INT_32(REG_D[offset&7]);
3112 width = REG_D[width&7];
3114 /* Offset is signed so we have to use ugly math =( */
3122 width = ((width-1) & 31) + 1;
3125 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3126 mask_long = mask_base >> offset;
3128 data_long = m68ki_read_32(ea);
3129 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3130 FLAG_Z = data_long & mask_long;
3131 FLAG_V = VFLAG_CLEAR;
3132 FLAG_C = CFLAG_CLEAR;
3134 if((width + offset) > 32)
3136 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3137 data_byte = m68ki_read_8(ea+4);
3138 FLAG_Z |= (data_byte & mask_byte);
3142 m68ki_exception_illegal();
3146 M68KMAKE_OP(bkpt, 0, ., .)
3148 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3150 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3152 m68ki_exception_illegal();
3156 M68KMAKE_OP(bra, 8, ., .)
3158 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3159 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3160 if(REG_PC == REG_PPC)
3165 M68KMAKE_OP(bra, 16, ., .)
3167 uint offset = OPER_I_16();
3169 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3170 m68ki_branch_16(offset);
3171 if(REG_PC == REG_PPC)
3176 M68KMAKE_OP(bra, 32, ., .)
3178 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3180 uint offset = OPER_I_32();
3182 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3183 m68ki_branch_32(offset);
3184 if(REG_PC == REG_PPC)
3190 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3191 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3192 if(REG_PC == REG_PPC)
3198 M68KMAKE_OP(bset, 32, r, d)
3201 uint mask = 1 << (DX & 0x1f);
3203 FLAG_Z = *r_dst & mask;
3208 M68KMAKE_OP(bset, 8, r, .)
3210 uint ea = M68KMAKE_GET_EA_AY_8;
3211 uint src = m68ki_read_8(ea);
3212 uint mask = 1 << (DX & 7);
3214 FLAG_Z = src & mask;
3215 m68ki_write_8(ea, src | mask);
3219 M68KMAKE_OP(bset, 32, s, d)
3222 uint mask = 1 << (OPER_I_8() & 0x1f);
3224 FLAG_Z = *r_dst & mask;
3229 M68KMAKE_OP(bset, 8, s, .)
3231 uint mask = 1 << (OPER_I_8() & 7);
3232 uint ea = M68KMAKE_GET_EA_AY_8;
3233 uint src = m68ki_read_8(ea);
3235 FLAG_Z = src & mask;
3236 m68ki_write_8(ea, src | mask);
3240 M68KMAKE_OP(bsr, 8, ., .)
3242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3243 m68ki_push_32(REG_PC);
3244 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3248 M68KMAKE_OP(bsr, 16, ., .)
3250 uint offset = OPER_I_16();
3251 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3252 m68ki_push_32(REG_PC);
3254 m68ki_branch_16(offset);
3258 M68KMAKE_OP(bsr, 32, ., .)
3260 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3262 uint offset = OPER_I_32();
3263 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3264 m68ki_push_32(REG_PC);
3266 m68ki_branch_32(offset);
3271 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3272 m68ki_push_32(REG_PC);
3273 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3278 M68KMAKE_OP(btst, 32, r, d)
3280 FLAG_Z = DY & (1 << (DX & 0x1f));
3284 M68KMAKE_OP(btst, 8, r, .)
3286 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3290 M68KMAKE_OP(btst, 32, s, d)
3292 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3296 M68KMAKE_OP(btst, 8, s, .)
3298 uint bit = OPER_I_8() & 7;
3300 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3304 M68KMAKE_OP(callm, 32, ., .)
3306 /* note: watch out for pcrelative modes */
3307 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3309 uint ea = M68KMAKE_GET_EA_AY_32;
3311 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3313 (void)ea; /* just to avoid an 'unused variable' warning */
3314 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3315 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3316 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
3319 m68ki_exception_illegal();
3323 M68KMAKE_OP(cas, 8, ., .)
3325 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3327 uint word2 = OPER_I_16();
3328 uint ea = M68KMAKE_GET_EA_AY_8;
3329 uint dest = m68ki_read_8(ea);
3330 uint* compare = ®_D[word2 & 7];
3331 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3333 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3334 FLAG_N = NFLAG_8(res);
3335 FLAG_Z = MASK_OUT_ABOVE_8(res);
3336 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3337 FLAG_C = CFLAG_8(res);
3340 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3344 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3348 m68ki_exception_illegal();
3352 M68KMAKE_OP(cas, 16, ., .)
3354 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3356 uint word2 = OPER_I_16();
3357 uint ea = M68KMAKE_GET_EA_AY_16;
3358 uint dest = m68ki_read_16(ea);
3359 uint* compare = ®_D[word2 & 7];
3360 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3363 FLAG_N = NFLAG_16(res);
3364 FLAG_Z = MASK_OUT_ABOVE_16(res);
3365 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3366 FLAG_C = CFLAG_16(res);
3369 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3373 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3377 m68ki_exception_illegal();
3381 M68KMAKE_OP(cas, 32, ., .)
3383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3385 uint word2 = OPER_I_16();
3386 uint ea = M68KMAKE_GET_EA_AY_32;
3387 uint dest = m68ki_read_32(ea);
3388 uint* compare = ®_D[word2 & 7];
3389 uint res = dest - *compare;
3391 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3392 FLAG_N = NFLAG_32(res);
3393 FLAG_Z = MASK_OUT_ABOVE_32(res);
3394 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3395 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3402 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3406 m68ki_exception_illegal();
3410 M68KMAKE_OP(cas2, 16, ., .)
3412 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3414 uint word2 = OPER_I_32();
3415 uint* compare1 = ®_D[(word2 >> 16) & 7];
3416 uint ea1 = REG_DA[(word2 >> 28) & 15];
3417 uint dest1 = m68ki_read_16(ea1);
3418 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3419 uint* compare2 = ®_D[word2 & 7];
3420 uint ea2 = REG_DA[(word2 >> 12) & 15];
3421 uint dest2 = m68ki_read_16(ea2);
3424 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3425 FLAG_N = NFLAG_16(res1);
3426 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3427 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3428 FLAG_C = CFLAG_16(res1);
3432 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3434 FLAG_N = NFLAG_16(res2);
3435 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3436 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3437 FLAG_C = CFLAG_16(res2);
3442 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3443 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3447 *compare1 = BIT_1F(word2) ? (uint)MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3448 *compare2 = BIT_F(word2) ? (uint)MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3451 m68ki_exception_illegal();
3455 M68KMAKE_OP(cas2, 32, ., .)
3457 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3459 uint word2 = OPER_I_32();
3460 uint* compare1 = ®_D[(word2 >> 16) & 7];
3461 uint ea1 = REG_DA[(word2 >> 28) & 15];
3462 uint dest1 = m68ki_read_32(ea1);
3463 uint res1 = dest1 - *compare1;
3464 uint* compare2 = ®_D[word2 & 7];
3465 uint ea2 = REG_DA[(word2 >> 12) & 15];
3466 uint dest2 = m68ki_read_32(ea2);
3469 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3470 FLAG_N = NFLAG_32(res1);
3471 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3472 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3473 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3477 res2 = dest2 - *compare2;
3479 FLAG_N = NFLAG_32(res2);
3480 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3481 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3482 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3487 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3488 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3496 m68ki_exception_illegal();
3500 M68KMAKE_OP(chk, 16, ., d)
3502 sint src = MAKE_INT_16(DX);
3503 sint bound = MAKE_INT_16(DY);
3505 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3506 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3507 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3509 if(src >= 0 && src <= bound)
3513 FLAG_N = (src < 0)<<7;
3514 m68ki_exception_trap(EXCEPTION_CHK);
3518 M68KMAKE_OP(chk, 16, ., .)
3520 sint src = MAKE_INT_16(DX);
3521 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3523 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3524 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3525 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3527 if(src >= 0 && src <= bound)
3531 FLAG_N = (src < 0)<<7;
3532 m68ki_exception_trap(EXCEPTION_CHK);
3536 M68KMAKE_OP(chk, 32, ., d)
3538 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3540 sint src = MAKE_INT_32(DX);
3541 sint bound = MAKE_INT_32(DY);
3543 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3544 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3545 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3547 if(src >= 0 && src <= bound)
3551 FLAG_N = (src < 0)<<7;
3552 m68ki_exception_trap(EXCEPTION_CHK);
3555 m68ki_exception_illegal();
3559 M68KMAKE_OP(chk, 32, ., .)
3561 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3563 sint src = MAKE_INT_32(DX);
3564 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3566 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3567 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3568 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3570 if(src >= 0 && src <= bound)
3574 FLAG_N = (src < 0)<<7;
3575 m68ki_exception_trap(EXCEPTION_CHK);
3578 m68ki_exception_illegal();
3582 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3584 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3586 uint word2 = OPER_I_16();
3587 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3588 uint ea = EA_PCDI_8();
3589 sint lower_bound = m68ki_read_pcrel_8(ea);
3590 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3593 compare = (int32)(int8)compare;
3595 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3597 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3599 if(COND_CS() && BIT_B(word2))
3600 m68ki_exception_trap(EXCEPTION_CHK);
3605 m68ki_exception_illegal();
3609 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3613 uint word2 = OPER_I_16();
3614 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3615 uint ea = EA_PCIX_8();
3616 sint lower_bound = m68ki_read_pcrel_8(ea);
3617 sint upper_bound = m68ki_read_pcrel_8(ea + 1);
3620 compare = (int32)(int8)compare;
3621 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||, faster operation short circuits
3623 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3625 if(COND_CS() && BIT_B(word2))
3626 m68ki_exception_trap(EXCEPTION_CHK);
3630 m68ki_exception_illegal();
3634 M68KMAKE_OP(chk2cmp2, 8, ., .)
3636 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3638 uint word2 = OPER_I_16();
3639 sint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3640 uint ea = M68KMAKE_GET_EA_AY_8;
3641 sint lower_bound = (int8)m68ki_read_8(ea);
3642 sint upper_bound = (int8)m68ki_read_8(ea + 1);
3645 compare = (int32)(int8)compare;
3647 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3649 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3651 if(COND_CS() && BIT_B(word2))
3652 m68ki_exception_trap(EXCEPTION_CHK);
3655 m68ki_exception_illegal();
3659 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3661 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3663 uint word2 = OPER_I_16();
3664 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3665 uint ea = EA_PCDI_16();
3666 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3667 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3670 compare = (int32)(int16)compare;
3671 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3673 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3675 if(COND_CS() && BIT_B(word2))
3676 m68ki_exception_trap(EXCEPTION_CHK);
3679 m68ki_exception_illegal();
3683 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3687 uint word2 = OPER_I_16();
3688 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3689 uint ea = EA_PCIX_16();
3690 sint lower_bound = (int16)m68ki_read_pcrel_16(ea);
3691 sint upper_bound = (int16)m68ki_read_pcrel_16(ea + 2);
3694 compare = (int32)(int16)compare;
3695 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3697 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3699 if(COND_CS() && BIT_B(word2))
3700 m68ki_exception_trap(EXCEPTION_CHK);
3703 m68ki_exception_illegal();
3707 M68KMAKE_OP(chk2cmp2, 16, ., .)
3709 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3711 uint word2 = OPER_I_16();
3712 sint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3713 uint ea = M68KMAKE_GET_EA_AY_16;
3714 sint lower_bound = (int16)m68ki_read_16(ea);
3715 sint upper_bound = (int16)m68ki_read_16(ea + 2);
3718 compare = (int32)(int16)compare;
3719 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3721 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3723 if(COND_CS() && BIT_B(word2))
3724 m68ki_exception_trap(EXCEPTION_CHK);
3727 m68ki_exception_illegal();
3731 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3733 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3735 uint word2 = OPER_I_16();
3736 sint compare = REG_DA[(word2 >> 12) & 15];
3737 uint ea = EA_PCDI_32();
3738 sint lower_bound = m68ki_read_pcrel_32(ea);
3739 sint upper_bound = m68ki_read_pcrel_32(ea + 4);
3741 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3743 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3745 if(COND_CS() && BIT_B(word2))
3746 m68ki_exception_trap(EXCEPTION_CHK);
3749 m68ki_exception_illegal();
3753 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3755 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3757 uint word2 = OPER_I_16();
3758 sint compare = REG_DA[(word2 >> 12) & 15];
3759 uint ea = EA_PCIX_32();
3760 sint lower_bound = m68ki_read_32(ea);
3761 sint upper_bound = m68ki_read_32(ea + 4);
3763 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3765 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3767 if(COND_CS() && BIT_B(word2))
3768 m68ki_exception_trap(EXCEPTION_CHK);
3771 m68ki_exception_illegal();
3775 M68KMAKE_OP(chk2cmp2, 32, ., .)
3777 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3779 uint word2 = OPER_I_16();
3780 // JFF changed the logic. chk2/cmp2 uses signed values, not unsigned
3781 sint compare = REG_DA[(word2 >> 12) & 15];
3782 uint ea = M68KMAKE_GET_EA_AY_32;
3783 sint lower_bound = m68ki_read_32(ea);
3784 sint upper_bound = m68ki_read_32(ea + 4);
3786 FLAG_Z = !((upper_bound==compare) || (lower_bound==compare)); // JFF: | => ||
3788 FLAG_C = (lower_bound <= upper_bound ? compare < lower_bound || compare > upper_bound : compare > upper_bound || compare < lower_bound) << 8;
3790 if(COND_CS() && BIT_B(word2))
3791 m68ki_exception_trap(EXCEPTION_CHK);
3794 m68ki_exception_illegal();
3798 M68KMAKE_OP(clr, 8, ., d)
3802 FLAG_N = NFLAG_CLEAR;
3803 FLAG_V = VFLAG_CLEAR;
3804 FLAG_C = CFLAG_CLEAR;
3809 M68KMAKE_OP(clr, 8, ., .)
3811 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
3813 FLAG_N = NFLAG_CLEAR;
3814 FLAG_V = VFLAG_CLEAR;
3815 FLAG_C = CFLAG_CLEAR;
3820 M68KMAKE_OP(clr, 16, ., d)
3824 FLAG_N = NFLAG_CLEAR;
3825 FLAG_V = VFLAG_CLEAR;
3826 FLAG_C = CFLAG_CLEAR;
3831 M68KMAKE_OP(clr, 16, ., .)
3833 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
3835 FLAG_N = NFLAG_CLEAR;
3836 FLAG_V = VFLAG_CLEAR;
3837 FLAG_C = CFLAG_CLEAR;
3842 M68KMAKE_OP(clr, 32, ., d)
3846 FLAG_N = NFLAG_CLEAR;
3847 FLAG_V = VFLAG_CLEAR;
3848 FLAG_C = CFLAG_CLEAR;
3853 M68KMAKE_OP(clr, 32, ., .)
3855 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
3857 FLAG_N = NFLAG_CLEAR;
3858 FLAG_V = VFLAG_CLEAR;
3859 FLAG_C = CFLAG_CLEAR;
3864 M68KMAKE_OP(cmp, 8, ., d)
3866 uint src = MASK_OUT_ABOVE_8(DY);
3867 uint dst = MASK_OUT_ABOVE_8(DX);
3868 uint res = dst - src;
3870 FLAG_N = NFLAG_8(res);
3871 FLAG_Z = MASK_OUT_ABOVE_8(res);
3872 FLAG_V = VFLAG_SUB_8(src, dst, res);
3873 FLAG_C = CFLAG_8(res);
3877 M68KMAKE_OP(cmp, 8, ., .)
3879 uint src = M68KMAKE_GET_OPER_AY_8;
3880 uint dst = MASK_OUT_ABOVE_8(DX);
3881 uint res = dst - src;
3883 FLAG_N = NFLAG_8(res);
3884 FLAG_Z = MASK_OUT_ABOVE_8(res);
3885 FLAG_V = VFLAG_SUB_8(src, dst, res);
3886 FLAG_C = CFLAG_8(res);
3890 M68KMAKE_OP(cmp, 16, ., d)
3892 uint src = MASK_OUT_ABOVE_16(DY);
3893 uint dst = MASK_OUT_ABOVE_16(DX);
3894 uint res = dst - src;
3896 FLAG_N = NFLAG_16(res);
3897 FLAG_Z = MASK_OUT_ABOVE_16(res);
3898 FLAG_V = VFLAG_SUB_16(src, dst, res);
3899 FLAG_C = CFLAG_16(res);
3903 M68KMAKE_OP(cmp, 16, ., a)
3905 uint src = MASK_OUT_ABOVE_16(AY);
3906 uint dst = MASK_OUT_ABOVE_16(DX);
3907 uint res = dst - src;
3909 FLAG_N = NFLAG_16(res);
3910 FLAG_Z = MASK_OUT_ABOVE_16(res);
3911 FLAG_V = VFLAG_SUB_16(src, dst, res);
3912 FLAG_C = CFLAG_16(res);
3916 M68KMAKE_OP(cmp, 16, ., .)
3918 uint src = M68KMAKE_GET_OPER_AY_16;
3919 uint dst = MASK_OUT_ABOVE_16(DX);
3920 uint res = dst - src;
3922 FLAG_N = NFLAG_16(res);
3923 FLAG_Z = MASK_OUT_ABOVE_16(res);
3924 FLAG_V = VFLAG_SUB_16(src, dst, res);
3925 FLAG_C = CFLAG_16(res);
3929 M68KMAKE_OP(cmp, 32, ., d)
3933 uint res = dst - src;
3935 FLAG_N = NFLAG_32(res);
3936 FLAG_Z = MASK_OUT_ABOVE_32(res);
3937 FLAG_V = VFLAG_SUB_32(src, dst, res);
3938 FLAG_C = CFLAG_SUB_32(src, dst, res);
3942 M68KMAKE_OP(cmp, 32, ., a)
3946 uint res = dst - src;
3948 FLAG_N = NFLAG_32(res);
3949 FLAG_Z = MASK_OUT_ABOVE_32(res);
3950 FLAG_V = VFLAG_SUB_32(src, dst, res);
3951 FLAG_C = CFLAG_SUB_32(src, dst, res);
3955 M68KMAKE_OP(cmp, 32, ., .)
3957 uint src = M68KMAKE_GET_OPER_AY_32;
3959 uint res = dst - src;
3961 FLAG_N = NFLAG_32(res);
3962 FLAG_Z = MASK_OUT_ABOVE_32(res);
3963 FLAG_V = VFLAG_SUB_32(src, dst, res);
3964 FLAG_C = CFLAG_SUB_32(src, dst, res);
3968 M68KMAKE_OP(cmpa, 16, ., d)
3970 uint src = MAKE_INT_16(DY);
3972 uint res = dst - src;
3974 FLAG_N = NFLAG_32(res);
3975 FLAG_Z = MASK_OUT_ABOVE_32(res);
3976 FLAG_V = VFLAG_SUB_32(src, dst, res);
3977 FLAG_C = CFLAG_SUB_32(src, dst, res);
3981 M68KMAKE_OP(cmpa, 16, ., a)
3983 uint src = MAKE_INT_16(AY);
3985 uint res = dst - src;
3987 FLAG_N = NFLAG_32(res);
3988 FLAG_Z = MASK_OUT_ABOVE_32(res);
3989 FLAG_V = VFLAG_SUB_32(src, dst, res);
3990 FLAG_C = CFLAG_SUB_32(src, dst, res);
3994 M68KMAKE_OP(cmpa, 16, ., .)
3996 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3998 uint res = dst - src;
4000 FLAG_N = NFLAG_32(res);
4001 FLAG_Z = MASK_OUT_ABOVE_32(res);
4002 FLAG_V = VFLAG_SUB_32(src, dst, res);
4003 FLAG_C = CFLAG_SUB_32(src, dst, res);
4007 M68KMAKE_OP(cmpa, 32, ., d)
4011 uint res = dst - src;
4013 FLAG_N = NFLAG_32(res);
4014 FLAG_Z = MASK_OUT_ABOVE_32(res);
4015 FLAG_V = VFLAG_SUB_32(src, dst, res);
4016 FLAG_C = CFLAG_SUB_32(src, dst, res);
4020 M68KMAKE_OP(cmpa, 32, ., a)
4024 uint res = dst - src;
4026 FLAG_N = NFLAG_32(res);
4027 FLAG_Z = MASK_OUT_ABOVE_32(res);
4028 FLAG_V = VFLAG_SUB_32(src, dst, res);
4029 FLAG_C = CFLAG_SUB_32(src, dst, res);
4033 M68KMAKE_OP(cmpa, 32, ., .)
4035 uint src = M68KMAKE_GET_OPER_AY_32;
4037 uint res = dst - src;
4039 FLAG_N = NFLAG_32(res);
4040 FLAG_Z = MASK_OUT_ABOVE_32(res);
4041 FLAG_V = VFLAG_SUB_32(src, dst, res);
4042 FLAG_C = CFLAG_SUB_32(src, dst, res);
4046 M68KMAKE_OP(cmpi, 8, ., d)
4048 uint src = OPER_I_8();
4049 uint dst = MASK_OUT_ABOVE_8(DY);
4050 uint res = dst - src;
4052 FLAG_N = NFLAG_8(res);
4053 FLAG_Z = MASK_OUT_ABOVE_8(res);
4054 FLAG_V = VFLAG_SUB_8(src, dst, res);
4055 FLAG_C = CFLAG_8(res);
4059 M68KMAKE_OP(cmpi, 8, ., .)
4061 uint src = OPER_I_8();
4062 uint dst = M68KMAKE_GET_OPER_AY_8;
4063 uint res = dst - src;
4065 FLAG_N = NFLAG_8(res);
4066 FLAG_Z = MASK_OUT_ABOVE_8(res);
4067 FLAG_V = VFLAG_SUB_8(src, dst, res);
4068 FLAG_C = CFLAG_8(res);
4072 M68KMAKE_OP(cmpi, 8, ., pcdi)
4074 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4076 uint src = OPER_I_8();
4077 uint dst = OPER_PCDI_8();
4078 uint res = dst - src;
4080 FLAG_N = NFLAG_8(res);
4081 FLAG_Z = MASK_OUT_ABOVE_8(res);
4082 FLAG_V = VFLAG_SUB_8(src, dst, res);
4083 FLAG_C = CFLAG_8(res);
4086 m68ki_exception_illegal();
4090 M68KMAKE_OP(cmpi, 8, ., pcix)
4092 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4094 uint src = OPER_I_8();
4095 uint dst = OPER_PCIX_8();
4096 uint res = dst - src;
4098 FLAG_N = NFLAG_8(res);
4099 FLAG_Z = MASK_OUT_ABOVE_8(res);
4100 FLAG_V = VFLAG_SUB_8(src, dst, res);
4101 FLAG_C = CFLAG_8(res);
4104 m68ki_exception_illegal();
4108 M68KMAKE_OP(cmpi, 16, ., d)
4110 uint src = OPER_I_16();
4111 uint dst = MASK_OUT_ABOVE_16(DY);
4112 uint res = dst - src;
4114 FLAG_N = NFLAG_16(res);
4115 FLAG_Z = MASK_OUT_ABOVE_16(res);
4116 FLAG_V = VFLAG_SUB_16(src, dst, res);
4117 FLAG_C = CFLAG_16(res);
4121 M68KMAKE_OP(cmpi, 16, ., .)
4123 uint src = OPER_I_16();
4124 uint dst = M68KMAKE_GET_OPER_AY_16;
4125 uint res = dst - src;
4127 FLAG_N = NFLAG_16(res);
4128 FLAG_Z = MASK_OUT_ABOVE_16(res);
4129 FLAG_V = VFLAG_SUB_16(src, dst, res);
4130 FLAG_C = CFLAG_16(res);
4134 M68KMAKE_OP(cmpi, 16, ., pcdi)
4136 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4138 uint src = OPER_I_16();
4139 uint dst = OPER_PCDI_16();
4140 uint res = dst - src;
4142 FLAG_N = NFLAG_16(res);
4143 FLAG_Z = MASK_OUT_ABOVE_16(res);
4144 FLAG_V = VFLAG_SUB_16(src, dst, res);
4145 FLAG_C = CFLAG_16(res);
4148 m68ki_exception_illegal();
4152 M68KMAKE_OP(cmpi, 16, ., pcix)
4154 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4156 uint src = OPER_I_16();
4157 uint dst = OPER_PCIX_16();
4158 uint res = dst - src;
4160 FLAG_N = NFLAG_16(res);
4161 FLAG_Z = MASK_OUT_ABOVE_16(res);
4162 FLAG_V = VFLAG_SUB_16(src, dst, res);
4163 FLAG_C = CFLAG_16(res);
4166 m68ki_exception_illegal();
4170 M68KMAKE_OP(cmpi, 32, ., d)
4172 uint src = OPER_I_32();
4174 uint res = dst - src;
4176 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4177 FLAG_N = NFLAG_32(res);
4178 FLAG_Z = MASK_OUT_ABOVE_32(res);
4179 FLAG_V = VFLAG_SUB_32(src, dst, res);
4180 FLAG_C = CFLAG_SUB_32(src, dst, res);
4184 M68KMAKE_OP(cmpi, 32, ., .)
4186 uint src = OPER_I_32();
4187 uint dst = M68KMAKE_GET_OPER_AY_32;
4188 uint res = dst - src;
4190 FLAG_N = NFLAG_32(res);
4191 FLAG_Z = MASK_OUT_ABOVE_32(res);
4192 FLAG_V = VFLAG_SUB_32(src, dst, res);
4193 FLAG_C = CFLAG_SUB_32(src, dst, res);
4197 M68KMAKE_OP(cmpi, 32, ., pcdi)
4199 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4201 uint src = OPER_I_32();
4202 uint dst = OPER_PCDI_32();
4203 uint res = dst - src;
4205 FLAG_N = NFLAG_32(res);
4206 FLAG_Z = MASK_OUT_ABOVE_32(res);
4207 FLAG_V = VFLAG_SUB_32(src, dst, res);
4208 FLAG_C = CFLAG_SUB_32(src, dst, res);
4211 m68ki_exception_illegal();
4215 M68KMAKE_OP(cmpi, 32, ., pcix)
4217 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4219 uint src = OPER_I_32();
4220 uint dst = OPER_PCIX_32();
4221 uint res = dst - src;
4223 FLAG_N = NFLAG_32(res);
4224 FLAG_Z = MASK_OUT_ABOVE_32(res);
4225 FLAG_V = VFLAG_SUB_32(src, dst, res);
4226 FLAG_C = CFLAG_SUB_32(src, dst, res);
4229 m68ki_exception_illegal();
4233 M68KMAKE_OP(cmpm, 8, ., ax7)
4235 uint src = OPER_AY_PI_8();
4236 uint dst = OPER_A7_PI_8();
4237 uint res = dst - src;
4239 FLAG_N = NFLAG_8(res);
4240 FLAG_Z = MASK_OUT_ABOVE_8(res);
4241 FLAG_V = VFLAG_SUB_8(src, dst, res);
4242 FLAG_C = CFLAG_8(res);
4246 M68KMAKE_OP(cmpm, 8, ., ay7)
4248 uint src = OPER_A7_PI_8();
4249 uint dst = OPER_AX_PI_8();
4250 uint res = dst - src;
4252 FLAG_N = NFLAG_8(res);
4253 FLAG_Z = MASK_OUT_ABOVE_8(res);
4254 FLAG_V = VFLAG_SUB_8(src, dst, res);
4255 FLAG_C = CFLAG_8(res);
4259 M68KMAKE_OP(cmpm, 8, ., axy7)
4261 uint src = OPER_A7_PI_8();
4262 uint dst = OPER_A7_PI_8();
4263 uint res = dst - src;
4265 FLAG_N = NFLAG_8(res);
4266 FLAG_Z = MASK_OUT_ABOVE_8(res);
4267 FLAG_V = VFLAG_SUB_8(src, dst, res);
4268 FLAG_C = CFLAG_8(res);
4272 M68KMAKE_OP(cmpm, 8, ., .)
4274 uint src = OPER_AY_PI_8();
4275 uint dst = OPER_AX_PI_8();
4276 uint res = dst - src;
4278 FLAG_N = NFLAG_8(res);
4279 FLAG_Z = MASK_OUT_ABOVE_8(res);
4280 FLAG_V = VFLAG_SUB_8(src, dst, res);
4281 FLAG_C = CFLAG_8(res);
4285 M68KMAKE_OP(cmpm, 16, ., .)
4287 uint src = OPER_AY_PI_16();
4288 uint dst = OPER_AX_PI_16();
4289 uint res = dst - src;
4291 FLAG_N = NFLAG_16(res);
4292 FLAG_Z = MASK_OUT_ABOVE_16(res);
4293 FLAG_V = VFLAG_SUB_16(src, dst, res);
4294 FLAG_C = CFLAG_16(res);
4298 M68KMAKE_OP(cmpm, 32, ., .)
4300 uint src = OPER_AY_PI_32();
4301 uint dst = OPER_AX_PI_32();
4302 uint res = dst - src;
4304 FLAG_N = NFLAG_32(res);
4305 FLAG_Z = MASK_OUT_ABOVE_32(res);
4306 FLAG_V = VFLAG_SUB_32(src, dst, res);
4307 FLAG_C = CFLAG_SUB_32(src, dst, res);
4311 M68KMAKE_OP(cpbcc, 32, ., .)
4313 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4315 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4316 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4317 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4320 m68ki_exception_1111();
4324 M68KMAKE_OP(cpdbcc, 32, ., .)
4326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4328 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4329 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4330 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4333 m68ki_exception_1111();
4337 M68KMAKE_OP(cpgen, 32, ., .)
4339 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4341 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4342 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4343 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4346 m68ki_exception_1111();
4350 M68KMAKE_OP(cpscc, 32, ., .)
4352 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4354 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4355 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4356 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4359 m68ki_exception_1111();
4363 M68KMAKE_OP(cptrapcc, 32, ., .)
4365 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4367 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4368 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4369 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4370 // JFF: unsupported, but at least if the trap doesn't occur, app should still work, so at least PC increase is correct
4374 m68ki_exception_1111();
4377 M68KMAKE_OP(ftrapcc,32, ., .)
4383 m68ki_exception_1111();
4387 M68KMAKE_OP(dbt, 16, ., .)
4393 M68KMAKE_OP(dbf, 16, ., .)
4396 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4398 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4401 uint offset = OPER_I_16();
4403 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4404 m68ki_branch_16(offset);
4405 USE_CYCLES(CYC_DBCC_F_NOEXP);
4409 USE_CYCLES(CYC_DBCC_F_EXP);
4413 M68KMAKE_OP(dbcc, 16, ., .)
4418 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4420 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4423 uint offset = OPER_I_16();
4425 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4426 m68ki_branch_16(offset);
4427 USE_CYCLES(CYC_DBCC_F_NOEXP);
4431 USE_CYCLES(CYC_DBCC_F_EXP);
4438 M68KMAKE_OP(divs, 16, ., d)
4441 sint src = MAKE_INT_16(DY);
4447 if((uint32)*r_dst == 0x80000000 && src == -1)
4450 FLAG_N = NFLAG_CLEAR;
4451 FLAG_V = VFLAG_CLEAR;
4452 FLAG_C = CFLAG_CLEAR;
4457 quotient = MAKE_INT_32(*r_dst) / src;
4458 remainder = MAKE_INT_32(*r_dst) % src;
4460 if(quotient == MAKE_INT_16(quotient))
4463 FLAG_N = NFLAG_16(quotient);
4464 FLAG_V = VFLAG_CLEAR;
4465 FLAG_C = CFLAG_CLEAR;
4466 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4472 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4476 M68KMAKE_OP(divs, 16, ., .)
4479 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4485 if((uint32)*r_dst == 0x80000000 && src == -1)
4488 FLAG_N = NFLAG_CLEAR;
4489 FLAG_V = VFLAG_CLEAR;
4490 FLAG_C = CFLAG_CLEAR;
4495 quotient = MAKE_INT_32(*r_dst) / src;
4496 remainder = MAKE_INT_32(*r_dst) % src;
4498 if(quotient == MAKE_INT_16(quotient))
4501 FLAG_N = NFLAG_16(quotient);
4502 FLAG_V = VFLAG_CLEAR;
4503 FLAG_C = CFLAG_CLEAR;
4504 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4510 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4514 M68KMAKE_OP(divu, 16, ., d)
4517 uint src = MASK_OUT_ABOVE_16(DY);
4521 uint quotient = *r_dst / src;
4522 uint remainder = *r_dst % src;
4524 if(quotient < 0x10000)
4527 FLAG_N = NFLAG_16(quotient);
4528 FLAG_V = VFLAG_CLEAR;
4529 FLAG_C = CFLAG_CLEAR;
4530 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4536 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4540 M68KMAKE_OP(divu, 16, ., .)
4543 uint src = M68KMAKE_GET_OPER_AY_16;
4547 uint quotient = *r_dst / src;
4548 uint remainder = *r_dst % src;
4550 if(quotient < 0x10000)
4553 FLAG_N = NFLAG_16(quotient);
4554 FLAG_V = VFLAG_CLEAR;
4555 FLAG_C = CFLAG_CLEAR;
4556 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4562 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4566 M68KMAKE_OP(divl, 32, ., d)
4570 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4572 uint word2 = OPER_I_16();
4573 uint64 divisor = DY;
4574 uint64 dividend = 0;
4575 uint64 quotient = 0;
4576 uint64 remainder = 0;
4580 if(BIT_A(word2)) /* 64 bit */
4582 dividend = REG_D[word2 & 7];
4584 dividend |= REG_D[(word2 >> 12) & 7];
4586 if(BIT_B(word2)) /* signed */
4588 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4589 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4590 if((sint64)quotient != (sint64)((sint32)quotient))
4598 quotient = dividend / divisor;
4599 if(quotient > 0xffffffff)
4604 remainder = dividend % divisor;
4609 dividend = REG_D[(word2 >> 12) & 7];
4610 if(BIT_B(word2)) /* signed */
4612 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4613 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4617 quotient = dividend / divisor;
4618 remainder = dividend % divisor;
4622 REG_D[word2 & 7] = remainder;
4623 REG_D[(word2 >> 12) & 7] = quotient;
4625 FLAG_N = NFLAG_32(quotient);
4627 FLAG_V = VFLAG_CLEAR;
4628 FLAG_C = CFLAG_CLEAR;
4631 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4634 m68ki_exception_illegal();
4638 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4640 uint word2 = OPER_I_16();
4642 uint dividend_hi = REG_D[word2 & 7];
4643 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4646 uint dividend_neg = 0;
4647 uint divisor_neg = 0;
4653 /* quad / long : long quotient, long remainder */
4656 if(BIT_B(word2)) /* signed */
4658 /* special case in signed divide */
4659 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4661 REG_D[word2 & 7] = 0;
4662 REG_D[(word2 >> 12) & 7] = 0x80000000;
4665 FLAG_Z = ZFLAG_CLEAR;
4666 FLAG_V = VFLAG_CLEAR;
4667 FLAG_C = CFLAG_CLEAR;
4670 if(GET_MSB_32(dividend_hi))
4673 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4674 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4676 if(GET_MSB_32(divisor))
4679 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4684 /* if the upper long is greater than the divisor, we're overflowing. */
4685 if(dividend_hi >= divisor)
4691 for(i = 31; i >= 0; i--)
4694 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4695 if(remainder >= divisor)
4697 remainder -= divisor;
4701 for(i = 31; i >= 0; i--)
4704 overflow = GET_MSB_32(remainder);
4705 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4706 if(remainder >= divisor || overflow)
4708 remainder -= divisor;
4713 if(BIT_B(word2)) /* signed */
4715 if(quotient > 0x7fffffff)
4722 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4723 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4726 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4729 REG_D[word2 & 7] = remainder;
4730 REG_D[(word2 >> 12) & 7] = quotient;
4732 FLAG_N = NFLAG_32(quotient);
4734 FLAG_V = VFLAG_CLEAR;
4735 FLAG_C = CFLAG_CLEAR;
4739 /* long / long: long quotient, maybe long remainder */
4740 if(BIT_B(word2)) /* signed */
4742 /* Special case in divide */
4743 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4746 FLAG_Z = ZFLAG_CLEAR;
4747 FLAG_V = VFLAG_CLEAR;
4748 FLAG_C = CFLAG_CLEAR;
4749 REG_D[(word2 >> 12) & 7] = 0x80000000;
4750 REG_D[word2 & 7] = 0;
4753 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4754 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4758 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4759 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4762 FLAG_N = NFLAG_32(quotient);
4764 FLAG_V = VFLAG_CLEAR;
4765 FLAG_C = CFLAG_CLEAR;
4768 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4771 m68ki_exception_illegal();
4777 M68KMAKE_OP(divl, 32, ., .)
4781 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4783 uint word2 = OPER_I_16();
4784 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4785 uint64 dividend = 0;
4786 uint64 quotient = 0;
4787 uint64 remainder = 0;
4791 if(BIT_A(word2)) /* 64 bit */
4793 dividend = REG_D[word2 & 7];
4795 dividend |= REG_D[(word2 >> 12) & 7];
4797 if(BIT_B(word2)) /* signed */
4799 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4800 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4801 if((sint64)quotient != (sint64)((sint32)quotient))
4809 quotient = dividend / divisor;
4810 if(quotient > 0xffffffff)
4815 remainder = dividend % divisor;
4820 dividend = REG_D[(word2 >> 12) & 7];
4821 if(BIT_B(word2)) /* signed */
4823 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4824 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4828 quotient = dividend / divisor;
4829 remainder = dividend % divisor;
4833 REG_D[word2 & 7] = remainder;
4834 REG_D[(word2 >> 12) & 7] = quotient;
4836 FLAG_N = NFLAG_32(quotient);
4838 FLAG_V = VFLAG_CLEAR;
4839 FLAG_C = CFLAG_CLEAR;
4842 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4845 m68ki_exception_illegal();
4849 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4851 uint word2 = OPER_I_16();
4852 uint divisor = M68KMAKE_GET_OPER_AY_32;
4853 uint dividend_hi = REG_D[word2 & 7];
4854 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4857 uint dividend_neg = 0;
4858 uint divisor_neg = 0;
4864 /* quad / long : long quotient, long remainder */
4867 if(BIT_B(word2)) /* signed */
4869 /* special case in signed divide */
4870 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4872 REG_D[word2 & 7] = 0;
4873 REG_D[(word2 >> 12) & 7] = 0x80000000;
4876 FLAG_Z = ZFLAG_CLEAR;
4877 FLAG_V = VFLAG_CLEAR;
4878 FLAG_C = CFLAG_CLEAR;
4881 if(GET_MSB_32(dividend_hi))
4884 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4885 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4887 if(GET_MSB_32(divisor))
4890 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4895 /* if the upper long is greater than the divisor, we're overflowing. */
4896 if(dividend_hi >= divisor)
4902 for(i = 31; i >= 0; i--)
4905 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4906 if(remainder >= divisor)
4908 remainder -= divisor;
4912 for(i = 31; i >= 0; i--)
4915 overflow = GET_MSB_32(remainder);
4916 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4917 if(remainder >= divisor || overflow)
4919 remainder -= divisor;
4924 if(BIT_B(word2)) /* signed */
4926 if(quotient > 0x7fffffff)
4933 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4934 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4937 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4940 REG_D[word2 & 7] = remainder;
4941 REG_D[(word2 >> 12) & 7] = quotient;
4943 FLAG_N = NFLAG_32(quotient);
4945 FLAG_V = VFLAG_CLEAR;
4946 FLAG_C = CFLAG_CLEAR;
4950 /* long / long: long quotient, maybe long remainder */
4951 if(BIT_B(word2)) /* signed */
4953 /* Special case in divide */
4954 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4957 FLAG_Z = ZFLAG_CLEAR;
4958 FLAG_V = VFLAG_CLEAR;
4959 FLAG_C = CFLAG_CLEAR;
4960 REG_D[(word2 >> 12) & 7] = 0x80000000;
4961 REG_D[word2 & 7] = 0;
4964 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4965 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4969 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4970 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4973 FLAG_N = NFLAG_32(quotient);
4975 FLAG_V = VFLAG_CLEAR;
4976 FLAG_C = CFLAG_CLEAR;
4979 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4982 m68ki_exception_illegal();
4988 M68KMAKE_OP(eor, 8, ., d)
4990 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
4992 FLAG_N = NFLAG_8(res);
4994 FLAG_C = CFLAG_CLEAR;
4995 FLAG_V = VFLAG_CLEAR;
4999 M68KMAKE_OP(eor, 8, ., .)
5001 uint ea = M68KMAKE_GET_EA_AY_8;
5002 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
5004 m68ki_write_8(ea, res);
5006 FLAG_N = NFLAG_8(res);
5008 FLAG_C = CFLAG_CLEAR;
5009 FLAG_V = VFLAG_CLEAR;
5013 M68KMAKE_OP(eor, 16, ., d)
5015 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5017 FLAG_N = NFLAG_16(res);
5019 FLAG_C = CFLAG_CLEAR;
5020 FLAG_V = VFLAG_CLEAR;
5024 M68KMAKE_OP(eor, 16, ., .)
5026 uint ea = M68KMAKE_GET_EA_AY_16;
5027 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
5029 m68ki_write_16(ea, res);
5031 FLAG_N = NFLAG_16(res);
5033 FLAG_C = CFLAG_CLEAR;
5034 FLAG_V = VFLAG_CLEAR;
5038 M68KMAKE_OP(eor, 32, ., d)
5040 uint res = DY ^= DX;
5042 FLAG_N = NFLAG_32(res);
5044 FLAG_C = CFLAG_CLEAR;
5045 FLAG_V = VFLAG_CLEAR;
5049 M68KMAKE_OP(eor, 32, ., .)
5051 uint ea = M68KMAKE_GET_EA_AY_32;
5052 uint res = DX ^ m68ki_read_32(ea);
5054 m68ki_write_32(ea, res);
5056 FLAG_N = NFLAG_32(res);
5058 FLAG_C = CFLAG_CLEAR;
5059 FLAG_V = VFLAG_CLEAR;
5063 M68KMAKE_OP(eori, 8, ., d)
5065 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
5067 FLAG_N = NFLAG_8(res);
5069 FLAG_C = CFLAG_CLEAR;
5070 FLAG_V = VFLAG_CLEAR;
5074 M68KMAKE_OP(eori, 8, ., .)
5076 uint src = OPER_I_8();
5077 uint ea = M68KMAKE_GET_EA_AY_8;
5078 uint res = src ^ m68ki_read_8(ea);
5080 m68ki_write_8(ea, res);
5082 FLAG_N = NFLAG_8(res);
5084 FLAG_C = CFLAG_CLEAR;
5085 FLAG_V = VFLAG_CLEAR;
5089 M68KMAKE_OP(eori, 16, ., d)
5091 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
5093 FLAG_N = NFLAG_16(res);
5095 FLAG_C = CFLAG_CLEAR;
5096 FLAG_V = VFLAG_CLEAR;
5100 M68KMAKE_OP(eori, 16, ., .)
5102 uint src = OPER_I_16();
5103 uint ea = M68KMAKE_GET_EA_AY_16;
5104 uint res = src ^ m68ki_read_16(ea);
5106 m68ki_write_16(ea, res);
5108 FLAG_N = NFLAG_16(res);
5110 FLAG_C = CFLAG_CLEAR;
5111 FLAG_V = VFLAG_CLEAR;
5115 M68KMAKE_OP(eori, 32, ., d)
5117 uint res = DY ^= OPER_I_32();
5119 FLAG_N = NFLAG_32(res);
5121 FLAG_C = CFLAG_CLEAR;
5122 FLAG_V = VFLAG_CLEAR;
5126 M68KMAKE_OP(eori, 32, ., .)
5128 uint src = OPER_I_32();
5129 uint ea = M68KMAKE_GET_EA_AY_32;
5130 uint res = src ^ m68ki_read_32(ea);
5132 m68ki_write_32(ea, res);
5134 FLAG_N = NFLAG_32(res);
5136 FLAG_C = CFLAG_CLEAR;
5137 FLAG_V = VFLAG_CLEAR;
5141 M68KMAKE_OP(eori, 16, toc, .)
5143 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_8());
5147 M68KMAKE_OP(eori, 16, tos, .)
5151 uint src = OPER_I_16();
5152 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5153 m68ki_set_sr(m68ki_get_sr() ^ src);
5156 m68ki_exception_privilege_violation();
5160 M68KMAKE_OP(exg, 32, dd, .)
5170 M68KMAKE_OP(exg, 32, aa, .)
5180 M68KMAKE_OP(exg, 32, da, .)
5190 M68KMAKE_OP(ext, 16, ., .)
5194 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5196 FLAG_N = NFLAG_16(*r_dst);
5197 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5198 FLAG_V = VFLAG_CLEAR;
5199 FLAG_C = CFLAG_CLEAR;
5203 M68KMAKE_OP(ext, 32, ., .)
5207 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5209 FLAG_N = NFLAG_32(*r_dst);
5211 FLAG_V = VFLAG_CLEAR;
5212 FLAG_C = CFLAG_CLEAR;
5216 M68KMAKE_OP(extb, 32, ., .)
5218 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5222 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5224 FLAG_N = NFLAG_32(*r_dst);
5226 FLAG_V = VFLAG_CLEAR;
5227 FLAG_C = CFLAG_CLEAR;
5230 m68ki_exception_illegal();
5234 M68KMAKE_OP(illegal, 0, ., .)
5236 m68ki_exception_illegal();
5239 M68KMAKE_OP(jmp, 32, ., .)
5241 m68ki_jump(M68KMAKE_GET_EA_AY_32);
5242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5243 if(REG_PC == REG_PPC)
5248 M68KMAKE_OP(jsr, 32, ., .)
5250 uint ea = M68KMAKE_GET_EA_AY_32;
5251 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5252 m68ki_push_32(REG_PC);
5257 M68KMAKE_OP(lea, 32, ., .)
5259 AX = M68KMAKE_GET_EA_AY_32;
5263 M68KMAKE_OP(link, 16, ., a7)
5266 m68ki_write_32(REG_A[7], REG_A[7]);
5267 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5271 M68KMAKE_OP(link, 16, ., .)
5275 m68ki_push_32(*r_dst);
5277 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5281 M68KMAKE_OP(link, 32, ., a7)
5283 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5286 m68ki_write_32(REG_A[7], REG_A[7]);
5287 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5290 m68ki_exception_illegal();
5294 M68KMAKE_OP(link, 32, ., .)
5296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5300 m68ki_push_32(*r_dst);
5302 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5305 m68ki_exception_illegal();
5309 M68KMAKE_OP(lsr, 8, s, .)
5312 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5313 uint src = MASK_OUT_ABOVE_8(*r_dst);
5314 uint res = src >> shift;
5317 USE_CYCLES(shift<<CYC_SHIFT);
5319 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5321 FLAG_N = NFLAG_CLEAR;
5323 FLAG_X = FLAG_C = src << (9-shift);
5324 FLAG_V = VFLAG_CLEAR;
5328 M68KMAKE_OP(lsr, 16, s, .)
5331 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5332 uint src = MASK_OUT_ABOVE_16(*r_dst);
5333 uint res = src >> shift;
5336 USE_CYCLES(shift<<CYC_SHIFT);
5338 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5340 FLAG_N = NFLAG_CLEAR;
5342 FLAG_X = FLAG_C = src << (9-shift);
5343 FLAG_V = VFLAG_CLEAR;
5347 M68KMAKE_OP(lsr, 32, s, .)
5350 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5352 uint res = src >> shift;
5355 USE_CYCLES(shift<<CYC_SHIFT);
5359 FLAG_N = NFLAG_CLEAR;
5361 FLAG_X = FLAG_C = src << (9-shift);
5362 FLAG_V = VFLAG_CLEAR;
5366 M68KMAKE_OP(lsr, 8, r, .)
5369 uint shift = DX & 0x3f;
5370 uint src = MASK_OUT_ABOVE_8(*r_dst);
5371 uint res = src >> shift;
5375 USE_CYCLES(shift<<CYC_SHIFT);
5379 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5380 FLAG_X = FLAG_C = src << (9-shift);
5381 FLAG_N = NFLAG_CLEAR;
5383 FLAG_V = VFLAG_CLEAR;
5387 *r_dst &= 0xffffff00;
5388 FLAG_X = XFLAG_CLEAR;
5389 FLAG_C = CFLAG_CLEAR;
5390 FLAG_N = NFLAG_CLEAR;
5392 FLAG_V = VFLAG_CLEAR;
5396 FLAG_C = CFLAG_CLEAR;
5397 FLAG_N = NFLAG_8(src);
5399 FLAG_V = VFLAG_CLEAR;
5403 M68KMAKE_OP(lsr, 16, r, .)
5406 uint shift = DX & 0x3f;
5407 uint src = MASK_OUT_ABOVE_16(*r_dst);
5408 uint res = src >> shift;
5412 USE_CYCLES(shift<<CYC_SHIFT);
5416 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5417 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5418 FLAG_N = NFLAG_CLEAR;
5420 FLAG_V = VFLAG_CLEAR;
5424 *r_dst &= 0xffff0000;
5425 FLAG_X = XFLAG_CLEAR;
5426 FLAG_C = CFLAG_CLEAR;
5427 FLAG_N = NFLAG_CLEAR;
5429 FLAG_V = VFLAG_CLEAR;
5433 FLAG_C = CFLAG_CLEAR;
5434 FLAG_N = NFLAG_16(src);
5436 FLAG_V = VFLAG_CLEAR;
5440 M68KMAKE_OP(lsr, 32, r, .)
5443 uint shift = DX & 0x3f;
5445 uint res = src >> shift;
5449 USE_CYCLES(shift<<CYC_SHIFT);
5454 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5455 FLAG_N = NFLAG_CLEAR;
5457 FLAG_V = VFLAG_CLEAR;
5462 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5463 FLAG_N = NFLAG_CLEAR;
5465 FLAG_V = VFLAG_CLEAR;
5469 FLAG_C = CFLAG_CLEAR;
5470 FLAG_N = NFLAG_32(src);
5472 FLAG_V = VFLAG_CLEAR;
5476 M68KMAKE_OP(lsr, 16, ., .)
5478 uint ea = M68KMAKE_GET_EA_AY_16;
5479 uint src = m68ki_read_16(ea);
5480 uint res = src >> 1;
5482 m68ki_write_16(ea, res);
5484 FLAG_N = NFLAG_CLEAR;
5486 FLAG_C = FLAG_X = src << 8;
5487 FLAG_V = VFLAG_CLEAR;
5491 M68KMAKE_OP(lsl, 8, s, .)
5494 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5495 uint src = MASK_OUT_ABOVE_8(*r_dst);
5496 uint res = MASK_OUT_ABOVE_8(src << shift);
5499 USE_CYCLES(shift<<CYC_SHIFT);
5501 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5503 FLAG_N = NFLAG_8(res);
5505 FLAG_X = FLAG_C = src << shift;
5506 FLAG_V = VFLAG_CLEAR;
5510 M68KMAKE_OP(lsl, 16, s, .)
5513 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5514 uint src = MASK_OUT_ABOVE_16(*r_dst);
5515 uint res = MASK_OUT_ABOVE_16(src << shift);
5518 USE_CYCLES(shift<<CYC_SHIFT);
5520 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5522 FLAG_N = NFLAG_16(res);
5524 FLAG_X = FLAG_C = src >> (8-shift);
5525 FLAG_V = VFLAG_CLEAR;
5529 M68KMAKE_OP(lsl, 32, s, .)
5532 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5534 uint res = MASK_OUT_ABOVE_32(src << shift);
5537 USE_CYCLES(shift<<CYC_SHIFT);
5541 FLAG_N = NFLAG_32(res);
5543 FLAG_X = FLAG_C = src >> (24-shift);
5544 FLAG_V = VFLAG_CLEAR;
5548 M68KMAKE_OP(lsl, 8, r, .)
5551 uint shift = DX & 0x3f;
5552 uint src = MASK_OUT_ABOVE_8(*r_dst);
5553 uint res = MASK_OUT_ABOVE_8(src << shift);
5557 USE_CYCLES(shift<<CYC_SHIFT);
5561 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5562 FLAG_X = FLAG_C = src << shift;
5563 FLAG_N = NFLAG_8(res);
5565 FLAG_V = VFLAG_CLEAR;
5569 *r_dst &= 0xffffff00;
5570 FLAG_X = XFLAG_CLEAR;
5571 FLAG_C = CFLAG_CLEAR;
5572 FLAG_N = NFLAG_CLEAR;
5574 FLAG_V = VFLAG_CLEAR;
5578 FLAG_C = CFLAG_CLEAR;
5579 FLAG_N = NFLAG_8(src);
5581 FLAG_V = VFLAG_CLEAR;
5585 M68KMAKE_OP(lsl, 16, r, .)
5588 uint shift = DX & 0x3f;
5589 uint src = MASK_OUT_ABOVE_16(*r_dst);
5590 uint res = MASK_OUT_ABOVE_16(src << shift);
5594 USE_CYCLES(shift<<CYC_SHIFT);
5598 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5599 FLAG_X = FLAG_C = (src << shift) >> 8;
5600 FLAG_N = NFLAG_16(res);
5602 FLAG_V = VFLAG_CLEAR;
5606 *r_dst &= 0xffff0000;
5607 FLAG_X = XFLAG_CLEAR;
5608 FLAG_C = CFLAG_CLEAR;
5609 FLAG_N = NFLAG_CLEAR;
5611 FLAG_V = VFLAG_CLEAR;
5615 FLAG_C = CFLAG_CLEAR;
5616 FLAG_N = NFLAG_16(src);
5618 FLAG_V = VFLAG_CLEAR;
5622 M68KMAKE_OP(lsl, 32, r, .)
5625 uint shift = DX & 0x3f;
5627 uint res = MASK_OUT_ABOVE_32(src << shift);
5631 USE_CYCLES(shift<<CYC_SHIFT);
5636 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5637 FLAG_N = NFLAG_32(res);
5639 FLAG_V = VFLAG_CLEAR;
5644 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5645 FLAG_N = NFLAG_CLEAR;
5647 FLAG_V = VFLAG_CLEAR;
5651 FLAG_C = CFLAG_CLEAR;
5652 FLAG_N = NFLAG_32(src);
5654 FLAG_V = VFLAG_CLEAR;
5658 M68KMAKE_OP(lsl, 16, ., .)
5660 uint ea = M68KMAKE_GET_EA_AY_16;
5661 uint src = m68ki_read_16(ea);
5662 uint res = MASK_OUT_ABOVE_16(src << 1);
5664 m68ki_write_16(ea, res);
5666 FLAG_N = NFLAG_16(res);
5668 FLAG_X = FLAG_C = src >> 7;
5669 FLAG_V = VFLAG_CLEAR;
5673 M68KMAKE_OP(move, 8, d, d)
5675 uint res = MASK_OUT_ABOVE_8(DY);
5678 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5680 FLAG_N = NFLAG_8(res);
5682 FLAG_V = VFLAG_CLEAR;
5683 FLAG_C = CFLAG_CLEAR;
5687 M68KMAKE_OP(move, 8, d, .)
5689 uint res = M68KMAKE_GET_OPER_AY_8;
5692 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5694 FLAG_N = NFLAG_8(res);
5696 FLAG_V = VFLAG_CLEAR;
5697 FLAG_C = CFLAG_CLEAR;
5701 M68KMAKE_OP(move, 8, ai, d)
5703 uint res = MASK_OUT_ABOVE_8(DY);
5704 uint ea = EA_AX_AI_8();
5706 m68ki_write_8(ea, res);
5708 FLAG_N = NFLAG_8(res);
5710 FLAG_V = VFLAG_CLEAR;
5711 FLAG_C = CFLAG_CLEAR;
5715 M68KMAKE_OP(move, 8, ai, .)
5717 uint res = M68KMAKE_GET_OPER_AY_8;
5718 uint ea = EA_AX_AI_8();
5720 m68ki_write_8(ea, res);
5722 FLAG_N = NFLAG_8(res);
5724 FLAG_V = VFLAG_CLEAR;
5725 FLAG_C = CFLAG_CLEAR;
5729 M68KMAKE_OP(move, 8, pi7, d)
5731 uint res = MASK_OUT_ABOVE_8(DY);
5732 uint ea = EA_A7_PI_8();
5734 m68ki_write_8(ea, res);
5736 FLAG_N = NFLAG_8(res);
5738 FLAG_V = VFLAG_CLEAR;
5739 FLAG_C = CFLAG_CLEAR;
5743 M68KMAKE_OP(move, 8, pi, d)
5745 uint res = MASK_OUT_ABOVE_8(DY);
5746 uint ea = EA_AX_PI_8();
5748 m68ki_write_8(ea, res);
5750 FLAG_N = NFLAG_8(res);
5752 FLAG_V = VFLAG_CLEAR;
5753 FLAG_C = CFLAG_CLEAR;
5757 M68KMAKE_OP(move, 8, pi7, .)
5759 uint res = M68KMAKE_GET_OPER_AY_8;
5760 uint ea = EA_A7_PI_8();
5762 m68ki_write_8(ea, res);
5764 FLAG_N = NFLAG_8(res);
5766 FLAG_V = VFLAG_CLEAR;
5767 FLAG_C = CFLAG_CLEAR;
5771 M68KMAKE_OP(move, 8, pi, .)
5773 uint res = M68KMAKE_GET_OPER_AY_8;
5774 uint ea = EA_AX_PI_8();
5776 m68ki_write_8(ea, res);
5778 FLAG_N = NFLAG_8(res);
5780 FLAG_V = VFLAG_CLEAR;
5781 FLAG_C = CFLAG_CLEAR;
5785 M68KMAKE_OP(move, 8, pd7, d)
5787 uint res = MASK_OUT_ABOVE_8(DY);
5788 uint ea = EA_A7_PD_8();
5790 m68ki_write_8(ea, res);
5792 FLAG_N = NFLAG_8(res);
5794 FLAG_V = VFLAG_CLEAR;
5795 FLAG_C = CFLAG_CLEAR;
5799 M68KMAKE_OP(move, 8, pd, d)
5801 uint res = MASK_OUT_ABOVE_8(DY);
5802 uint ea = EA_AX_PD_8();
5804 m68ki_write_8(ea, res);
5806 FLAG_N = NFLAG_8(res);
5808 FLAG_V = VFLAG_CLEAR;
5809 FLAG_C = CFLAG_CLEAR;
5813 M68KMAKE_OP(move, 8, pd7, .)
5815 uint res = M68KMAKE_GET_OPER_AY_8;
5816 uint ea = EA_A7_PD_8();
5818 m68ki_write_8(ea, res);
5820 FLAG_N = NFLAG_8(res);
5822 FLAG_V = VFLAG_CLEAR;
5823 FLAG_C = CFLAG_CLEAR;
5827 M68KMAKE_OP(move, 8, pd, .)
5829 uint res = M68KMAKE_GET_OPER_AY_8;
5830 uint ea = EA_AX_PD_8();
5832 m68ki_write_8(ea, res);
5834 FLAG_N = NFLAG_8(res);
5836 FLAG_V = VFLAG_CLEAR;
5837 FLAG_C = CFLAG_CLEAR;
5841 M68KMAKE_OP(move, 8, di, d)
5843 uint res = MASK_OUT_ABOVE_8(DY);
5844 uint ea = EA_AX_DI_8();
5846 m68ki_write_8(ea, res);
5848 FLAG_N = NFLAG_8(res);
5850 FLAG_V = VFLAG_CLEAR;
5851 FLAG_C = CFLAG_CLEAR;
5855 M68KMAKE_OP(move, 8, di, .)
5857 uint res = M68KMAKE_GET_OPER_AY_8;
5858 uint ea = EA_AX_DI_8();
5860 m68ki_write_8(ea, res);
5862 FLAG_N = NFLAG_8(res);
5864 FLAG_V = VFLAG_CLEAR;
5865 FLAG_C = CFLAG_CLEAR;
5869 M68KMAKE_OP(move, 8, ix, d)
5871 uint res = MASK_OUT_ABOVE_8(DY);
5872 uint ea = EA_AX_IX_8();
5874 m68ki_write_8(ea, res);
5876 FLAG_N = NFLAG_8(res);
5878 FLAG_V = VFLAG_CLEAR;
5879 FLAG_C = CFLAG_CLEAR;
5883 M68KMAKE_OP(move, 8, ix, .)
5885 uint res = M68KMAKE_GET_OPER_AY_8;
5886 uint ea = EA_AX_IX_8();
5888 m68ki_write_8(ea, res);
5890 FLAG_N = NFLAG_8(res);
5892 FLAG_V = VFLAG_CLEAR;
5893 FLAG_C = CFLAG_CLEAR;
5897 M68KMAKE_OP(move, 8, aw, d)
5899 uint res = MASK_OUT_ABOVE_8(DY);
5900 uint ea = EA_AW_8();
5902 m68ki_write_8(ea, res);
5904 FLAG_N = NFLAG_8(res);
5906 FLAG_V = VFLAG_CLEAR;
5907 FLAG_C = CFLAG_CLEAR;
5911 M68KMAKE_OP(move, 8, aw, .)
5913 uint res = M68KMAKE_GET_OPER_AY_8;
5914 uint ea = EA_AW_8();
5916 m68ki_write_8(ea, res);
5918 FLAG_N = NFLAG_8(res);
5920 FLAG_V = VFLAG_CLEAR;
5921 FLAG_C = CFLAG_CLEAR;
5925 M68KMAKE_OP(move, 8, al, d)
5927 uint res = MASK_OUT_ABOVE_8(DY);
5928 uint ea = EA_AL_8();
5930 m68ki_write_8(ea, res);
5932 FLAG_N = NFLAG_8(res);
5934 FLAG_V = VFLAG_CLEAR;
5935 FLAG_C = CFLAG_CLEAR;
5939 M68KMAKE_OP(move, 8, al, .)
5941 uint res = M68KMAKE_GET_OPER_AY_8;
5942 uint ea = EA_AL_8();
5944 m68ki_write_8(ea, res);
5946 FLAG_N = NFLAG_8(res);
5948 FLAG_V = VFLAG_CLEAR;
5949 FLAG_C = CFLAG_CLEAR;
5953 M68KMAKE_OP(move, 16, d, d)
5955 uint res = MASK_OUT_ABOVE_16(DY);
5958 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5960 FLAG_N = NFLAG_16(res);
5962 FLAG_V = VFLAG_CLEAR;
5963 FLAG_C = CFLAG_CLEAR;
5967 M68KMAKE_OP(move, 16, d, a)
5969 uint res = MASK_OUT_ABOVE_16(AY);
5972 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5974 FLAG_N = NFLAG_16(res);
5976 FLAG_V = VFLAG_CLEAR;
5977 FLAG_C = CFLAG_CLEAR;
5981 M68KMAKE_OP(move, 16, d, .)
5983 uint res = M68KMAKE_GET_OPER_AY_16;
5986 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5988 FLAG_N = NFLAG_16(res);
5990 FLAG_V = VFLAG_CLEAR;
5991 FLAG_C = CFLAG_CLEAR;
5995 M68KMAKE_OP(move, 16, ai, d)
5997 uint res = MASK_OUT_ABOVE_16(DY);
5998 uint ea = EA_AX_AI_16();
6000 m68ki_write_16(ea, res);
6002 FLAG_N = NFLAG_16(res);
6004 FLAG_V = VFLAG_CLEAR;
6005 FLAG_C = CFLAG_CLEAR;
6009 M68KMAKE_OP(move, 16, ai, a)
6011 uint res = MASK_OUT_ABOVE_16(AY);
6012 uint ea = EA_AX_AI_16();
6014 m68ki_write_16(ea, res);
6016 FLAG_N = NFLAG_16(res);
6018 FLAG_V = VFLAG_CLEAR;
6019 FLAG_C = CFLAG_CLEAR;
6023 M68KMAKE_OP(move, 16, ai, .)
6025 uint res = M68KMAKE_GET_OPER_AY_16;
6026 uint ea = EA_AX_AI_16();
6028 m68ki_write_16(ea, res);
6030 FLAG_N = NFLAG_16(res);
6032 FLAG_V = VFLAG_CLEAR;
6033 FLAG_C = CFLAG_CLEAR;
6037 M68KMAKE_OP(move, 16, pi, d)
6039 uint res = MASK_OUT_ABOVE_16(DY);
6040 uint ea = EA_AX_PI_16();
6042 m68ki_write_16(ea, res);
6044 FLAG_N = NFLAG_16(res);
6046 FLAG_V = VFLAG_CLEAR;
6047 FLAG_C = CFLAG_CLEAR;
6051 M68KMAKE_OP(move, 16, pi, a)
6053 uint res = MASK_OUT_ABOVE_16(AY);
6054 uint ea = EA_AX_PI_16();
6056 m68ki_write_16(ea, res);
6058 FLAG_N = NFLAG_16(res);
6060 FLAG_V = VFLAG_CLEAR;
6061 FLAG_C = CFLAG_CLEAR;
6065 M68KMAKE_OP(move, 16, pi, .)
6067 uint res = M68KMAKE_GET_OPER_AY_16;
6068 uint ea = EA_AX_PI_16();
6070 m68ki_write_16(ea, res);
6072 FLAG_N = NFLAG_16(res);
6074 FLAG_V = VFLAG_CLEAR;
6075 FLAG_C = CFLAG_CLEAR;
6079 M68KMAKE_OP(move, 16, pd, d)
6081 uint res = MASK_OUT_ABOVE_16(DY);
6082 uint ea = EA_AX_PD_16();
6084 m68ki_write_16(ea, res);
6086 FLAG_N = NFLAG_16(res);
6088 FLAG_V = VFLAG_CLEAR;
6089 FLAG_C = CFLAG_CLEAR;
6093 M68KMAKE_OP(move, 16, pd, a)
6095 uint res = MASK_OUT_ABOVE_16(AY);
6096 uint ea = EA_AX_PD_16();
6098 m68ki_write_16(ea, res);
6100 FLAG_N = NFLAG_16(res);
6102 FLAG_V = VFLAG_CLEAR;
6103 FLAG_C = CFLAG_CLEAR;
6107 M68KMAKE_OP(move, 16, pd, .)
6109 uint res = M68KMAKE_GET_OPER_AY_16;
6110 uint ea = EA_AX_PD_16();
6112 m68ki_write_16(ea, res);
6114 FLAG_N = NFLAG_16(res);
6116 FLAG_V = VFLAG_CLEAR;
6117 FLAG_C = CFLAG_CLEAR;
6121 M68KMAKE_OP(move, 16, di, d)
6123 uint res = MASK_OUT_ABOVE_16(DY);
6124 uint ea = EA_AX_DI_16();
6126 m68ki_write_16(ea, res);
6128 FLAG_N = NFLAG_16(res);
6130 FLAG_V = VFLAG_CLEAR;
6131 FLAG_C = CFLAG_CLEAR;
6135 M68KMAKE_OP(move, 16, di, a)
6137 uint res = MASK_OUT_ABOVE_16(AY);
6138 uint ea = EA_AX_DI_16();
6140 m68ki_write_16(ea, res);
6142 FLAG_N = NFLAG_16(res);
6144 FLAG_V = VFLAG_CLEAR;
6145 FLAG_C = CFLAG_CLEAR;
6149 M68KMAKE_OP(move, 16, di, .)
6151 uint res = M68KMAKE_GET_OPER_AY_16;
6152 uint ea = EA_AX_DI_16();
6154 m68ki_write_16(ea, res);
6156 FLAG_N = NFLAG_16(res);
6158 FLAG_V = VFLAG_CLEAR;
6159 FLAG_C = CFLAG_CLEAR;
6163 M68KMAKE_OP(move, 16, ix, d)
6165 uint res = MASK_OUT_ABOVE_16(DY);
6166 uint ea = EA_AX_IX_16();
6168 m68ki_write_16(ea, res);
6170 FLAG_N = NFLAG_16(res);
6172 FLAG_V = VFLAG_CLEAR;
6173 FLAG_C = CFLAG_CLEAR;
6177 M68KMAKE_OP(move, 16, ix, a)
6179 uint res = MASK_OUT_ABOVE_16(AY);
6180 uint ea = EA_AX_IX_16();
6182 m68ki_write_16(ea, res);
6184 FLAG_N = NFLAG_16(res);
6186 FLAG_V = VFLAG_CLEAR;
6187 FLAG_C = CFLAG_CLEAR;
6191 M68KMAKE_OP(move, 16, ix, .)
6193 uint res = M68KMAKE_GET_OPER_AY_16;
6194 uint ea = EA_AX_IX_16();
6196 m68ki_write_16(ea, res);
6198 FLAG_N = NFLAG_16(res);
6200 FLAG_V = VFLAG_CLEAR;
6201 FLAG_C = CFLAG_CLEAR;
6205 M68KMAKE_OP(move, 16, aw, d)
6207 uint res = MASK_OUT_ABOVE_16(DY);
6208 uint ea = EA_AW_16();
6210 m68ki_write_16(ea, res);
6212 FLAG_N = NFLAG_16(res);
6214 FLAG_V = VFLAG_CLEAR;
6215 FLAG_C = CFLAG_CLEAR;
6219 M68KMAKE_OP(move, 16, aw, a)
6221 uint res = MASK_OUT_ABOVE_16(AY);
6222 uint ea = EA_AW_16();
6224 m68ki_write_16(ea, res);
6226 FLAG_N = NFLAG_16(res);
6228 FLAG_V = VFLAG_CLEAR;
6229 FLAG_C = CFLAG_CLEAR;
6233 M68KMAKE_OP(move, 16, aw, .)
6235 uint res = M68KMAKE_GET_OPER_AY_16;
6236 uint ea = EA_AW_16();
6238 m68ki_write_16(ea, res);
6240 FLAG_N = NFLAG_16(res);
6242 FLAG_V = VFLAG_CLEAR;
6243 FLAG_C = CFLAG_CLEAR;
6247 M68KMAKE_OP(move, 16, al, d)
6249 uint res = MASK_OUT_ABOVE_16(DY);
6250 uint ea = EA_AL_16();
6252 m68ki_write_16(ea, res);
6254 FLAG_N = NFLAG_16(res);
6256 FLAG_V = VFLAG_CLEAR;
6257 FLAG_C = CFLAG_CLEAR;
6261 M68KMAKE_OP(move, 16, al, a)
6263 uint res = MASK_OUT_ABOVE_16(AY);
6264 uint ea = EA_AL_16();
6266 m68ki_write_16(ea, res);
6268 FLAG_N = NFLAG_16(res);
6270 FLAG_V = VFLAG_CLEAR;
6271 FLAG_C = CFLAG_CLEAR;
6275 M68KMAKE_OP(move, 16, al, .)
6277 uint res = M68KMAKE_GET_OPER_AY_16;
6278 uint ea = EA_AL_16();
6280 m68ki_write_16(ea, res);
6282 FLAG_N = NFLAG_16(res);
6284 FLAG_V = VFLAG_CLEAR;
6285 FLAG_C = CFLAG_CLEAR;
6289 M68KMAKE_OP(move, 32, d, d)
6296 FLAG_N = NFLAG_32(res);
6298 FLAG_V = VFLAG_CLEAR;
6299 FLAG_C = CFLAG_CLEAR;
6303 M68KMAKE_OP(move, 32, d, a)
6310 FLAG_N = NFLAG_32(res);
6312 FLAG_V = VFLAG_CLEAR;
6313 FLAG_C = CFLAG_CLEAR;
6317 M68KMAKE_OP(move, 32, d, .)
6319 uint res = M68KMAKE_GET_OPER_AY_32;
6324 FLAG_N = NFLAG_32(res);
6326 FLAG_V = VFLAG_CLEAR;
6327 FLAG_C = CFLAG_CLEAR;
6331 M68KMAKE_OP(move, 32, ai, d)
6334 uint ea = EA_AX_AI_32();
6336 m68ki_write_32(ea, res);
6338 FLAG_N = NFLAG_32(res);
6340 FLAG_V = VFLAG_CLEAR;
6341 FLAG_C = CFLAG_CLEAR;
6345 M68KMAKE_OP(move, 32, ai, a)
6348 uint ea = EA_AX_AI_32();
6350 m68ki_write_32(ea, res);
6352 FLAG_N = NFLAG_32(res);
6354 FLAG_V = VFLAG_CLEAR;
6355 FLAG_C = CFLAG_CLEAR;
6359 M68KMAKE_OP(move, 32, ai, .)
6361 uint res = M68KMAKE_GET_OPER_AY_32;
6362 uint ea = EA_AX_AI_32();
6364 m68ki_write_32(ea, res);
6366 FLAG_N = NFLAG_32(res);
6368 FLAG_V = VFLAG_CLEAR;
6369 FLAG_C = CFLAG_CLEAR;
6373 M68KMAKE_OP(move, 32, pi, d)
6376 uint ea = EA_AX_PI_32();
6378 m68ki_write_32(ea, res);
6380 FLAG_N = NFLAG_32(res);
6382 FLAG_V = VFLAG_CLEAR;
6383 FLAG_C = CFLAG_CLEAR;
6387 M68KMAKE_OP(move, 32, pi, a)
6390 uint ea = EA_AX_PI_32();
6392 m68ki_write_32(ea, res);
6394 FLAG_N = NFLAG_32(res);
6396 FLAG_V = VFLAG_CLEAR;
6397 FLAG_C = CFLAG_CLEAR;
6401 M68KMAKE_OP(move, 32, pi, .)
6403 uint res = M68KMAKE_GET_OPER_AY_32;
6404 uint ea = EA_AX_PI_32();
6406 m68ki_write_32(ea, res);
6408 FLAG_N = NFLAG_32(res);
6410 FLAG_V = VFLAG_CLEAR;
6411 FLAG_C = CFLAG_CLEAR;
6415 M68KMAKE_OP(move, 32, pd, d)
6418 uint ea = EA_AX_PD_32();
6420 m68ki_write_16(ea+2, res & 0xFFFF );
6421 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6423 FLAG_N = NFLAG_32(res);
6425 FLAG_V = VFLAG_CLEAR;
6426 FLAG_C = CFLAG_CLEAR;
6430 M68KMAKE_OP(move, 32, pd, a)
6433 uint ea = EA_AX_PD_32();
6435 m68ki_write_16(ea+2, res & 0xFFFF );
6436 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6438 FLAG_N = NFLAG_32(res);
6440 FLAG_V = VFLAG_CLEAR;
6441 FLAG_C = CFLAG_CLEAR;
6445 M68KMAKE_OP(move, 32, pd, .)
6447 uint res = M68KMAKE_GET_OPER_AY_32;
6448 uint ea = EA_AX_PD_32();
6450 m68ki_write_16(ea+2, res & 0xFFFF );
6451 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6453 FLAG_N = NFLAG_32(res);
6455 FLAG_V = VFLAG_CLEAR;
6456 FLAG_C = CFLAG_CLEAR;
6460 M68KMAKE_OP(move, 32, di, d)
6463 uint ea = EA_AX_DI_32();
6465 m68ki_write_32(ea, res);
6467 FLAG_N = NFLAG_32(res);
6469 FLAG_V = VFLAG_CLEAR;
6470 FLAG_C = CFLAG_CLEAR;
6474 M68KMAKE_OP(move, 32, di, a)
6477 uint ea = EA_AX_DI_32();
6479 m68ki_write_32(ea, res);
6481 FLAG_N = NFLAG_32(res);
6483 FLAG_V = VFLAG_CLEAR;
6484 FLAG_C = CFLAG_CLEAR;
6488 M68KMAKE_OP(move, 32, di, .)
6490 uint res = M68KMAKE_GET_OPER_AY_32;
6491 uint ea = EA_AX_DI_32();
6493 m68ki_write_32(ea, res);
6495 FLAG_N = NFLAG_32(res);
6497 FLAG_V = VFLAG_CLEAR;
6498 FLAG_C = CFLAG_CLEAR;
6502 M68KMAKE_OP(move, 32, ix, d)
6505 uint ea = EA_AX_IX_32();
6507 m68ki_write_32(ea, res);
6509 FLAG_N = NFLAG_32(res);
6511 FLAG_V = VFLAG_CLEAR;
6512 FLAG_C = CFLAG_CLEAR;
6516 M68KMAKE_OP(move, 32, ix, a)
6519 uint ea = EA_AX_IX_32();
6521 m68ki_write_32(ea, res);
6523 FLAG_N = NFLAG_32(res);
6525 FLAG_V = VFLAG_CLEAR;
6526 FLAG_C = CFLAG_CLEAR;
6530 M68KMAKE_OP(move, 32, ix, .)
6532 uint res = M68KMAKE_GET_OPER_AY_32;
6533 uint ea = EA_AX_IX_32();
6535 m68ki_write_32(ea, res);
6537 FLAG_N = NFLAG_32(res);
6539 FLAG_V = VFLAG_CLEAR;
6540 FLAG_C = CFLAG_CLEAR;
6544 M68KMAKE_OP(move, 32, aw, d)
6547 uint ea = EA_AW_32();
6549 m68ki_write_32(ea, res);
6551 FLAG_N = NFLAG_32(res);
6553 FLAG_V = VFLAG_CLEAR;
6554 FLAG_C = CFLAG_CLEAR;
6558 M68KMAKE_OP(move, 32, aw, a)
6561 uint ea = EA_AW_32();
6563 m68ki_write_32(ea, res);
6565 FLAG_N = NFLAG_32(res);
6567 FLAG_V = VFLAG_CLEAR;
6568 FLAG_C = CFLAG_CLEAR;
6572 M68KMAKE_OP(move, 32, aw, .)
6574 uint res = M68KMAKE_GET_OPER_AY_32;
6575 uint ea = EA_AW_32();
6577 m68ki_write_32(ea, res);
6579 FLAG_N = NFLAG_32(res);
6581 FLAG_V = VFLAG_CLEAR;
6582 FLAG_C = CFLAG_CLEAR;
6586 M68KMAKE_OP(move, 32, al, d)
6589 uint ea = EA_AL_32();
6591 m68ki_write_32(ea, res);
6593 FLAG_N = NFLAG_32(res);
6595 FLAG_V = VFLAG_CLEAR;
6596 FLAG_C = CFLAG_CLEAR;
6600 M68KMAKE_OP(move, 32, al, a)
6603 uint ea = EA_AL_32();
6605 m68ki_write_32(ea, res);
6607 FLAG_N = NFLAG_32(res);
6609 FLAG_V = VFLAG_CLEAR;
6610 FLAG_C = CFLAG_CLEAR;
6614 M68KMAKE_OP(move, 32, al, .)
6616 uint res = M68KMAKE_GET_OPER_AY_32;
6617 uint ea = EA_AL_32();
6619 m68ki_write_32(ea, res);
6621 FLAG_N = NFLAG_32(res);
6623 FLAG_V = VFLAG_CLEAR;
6624 FLAG_C = CFLAG_CLEAR;
6628 M68KMAKE_OP(movea, 16, ., d)
6630 AX = MAKE_INT_16(DY);
6634 M68KMAKE_OP(movea, 16, ., a)
6636 AX = MAKE_INT_16(AY);
6640 M68KMAKE_OP(movea, 16, ., .)
6642 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6646 M68KMAKE_OP(movea, 32, ., d)
6652 M68KMAKE_OP(movea, 32, ., a)
6658 M68KMAKE_OP(movea, 32, ., .)
6660 AX = M68KMAKE_GET_OPER_AY_32;
6664 M68KMAKE_OP(move, 16, frc, d)
6666 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6668 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6671 m68ki_exception_illegal();
6675 M68KMAKE_OP(move, 16, frc, .)
6677 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6679 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6682 m68ki_exception_illegal();
6686 M68KMAKE_OP(move, 16, toc, d)
6692 M68KMAKE_OP(move, 16, toc, .)
6694 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6698 M68KMAKE_OP(move, 16, frs, d)
6700 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6702 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6705 m68ki_exception_privilege_violation();
6709 M68KMAKE_OP(move, 16, frs, .)
6711 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6713 uint ea = M68KMAKE_GET_EA_AY_16;
6714 m68ki_write_16(ea, m68ki_get_sr());
6717 m68ki_exception_privilege_violation();
6721 M68KMAKE_OP(move, 16, tos, d)
6728 m68ki_exception_privilege_violation();
6732 M68KMAKE_OP(move, 16, tos, .)
6736 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6737 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6738 m68ki_set_sr(new_sr);
6741 m68ki_exception_privilege_violation();
6745 M68KMAKE_OP(move, 32, fru, .)
6752 m68ki_exception_privilege_violation();
6756 M68KMAKE_OP(move, 32, tou, .)
6760 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6764 m68ki_exception_privilege_violation();
6768 M68KMAKE_OP(movec, 32, cr, .)
6770 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6774 uint word2 = OPER_I_16();
6776 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6777 switch (word2 & 0xfff)
6779 case 0x000: /* SFC */
6780 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6782 case 0x001: /* DFC */
6783 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6785 case 0x002: /* CACR */
6786 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6788 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6792 case 0x800: /* USP */
6793 REG_DA[(word2 >> 12) & 15] = REG_USP;
6795 case 0x801: /* VBR */
6796 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6798 case 0x802: /* CAAR */
6799 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6801 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6804 m68ki_exception_illegal();
6806 case 0x803: /* MSP */
6807 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6809 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6812 m68ki_exception_illegal();
6814 case 0x804: /* ISP */
6815 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6817 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6820 m68ki_exception_illegal();
6822 case 0x003: /* TC */
6823 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6828 m68ki_exception_illegal();
6830 case 0x004: /* ITT0 */
6831 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6836 m68ki_exception_illegal();
6838 case 0x005: /* ITT1 */
6839 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6844 m68ki_exception_illegal();
6846 case 0x006: /* DTT0 */
6847 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6852 m68ki_exception_illegal();
6854 case 0x007: /* DTT1 */
6855 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6860 m68ki_exception_illegal();
6862 case 0x805: /* MMUSR */
6863 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6868 m68ki_exception_illegal();
6870 case 0x806: /* URP */
6871 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6876 m68ki_exception_illegal();
6878 case 0x807: /* SRP */
6879 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6884 m68ki_exception_illegal();
6887 m68ki_exception_illegal();
6891 m68ki_exception_privilege_violation();
6894 m68ki_exception_illegal();
6898 M68KMAKE_OP(movec, 32, rc, .)
6900 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6904 uint word2 = OPER_I_16();
6906 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6907 switch (word2 & 0xfff)
6909 case 0x000: /* SFC */
6910 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
6912 case 0x001: /* DFC */
6913 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
6915 case 0x002: /* CACR */
6916 /* Only EC020 and later have CACR */
6917 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6919 /* 68030 can write all bits except 5-7, 040 can write all */
6920 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6922 REG_CACR = REG_DA[(word2 >> 12) & 15];
6924 else if (CPU_TYPE_IS_030_PLUS(CPU_TYPE))
6926 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0xff1f;
6930 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
6934 m68ki_exception_illegal();
6936 case 0x800: /* USP */
6937 REG_USP = REG_DA[(word2 >> 12) & 15];
6939 case 0x801: /* VBR */
6940 REG_VBR = REG_DA[(word2 >> 12) & 15];
6942 case 0x802: /* CAAR */
6943 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6945 REG_CAAR = REG_DA[(word2 >> 12) & 15];
6948 m68ki_exception_illegal();
6950 case 0x803: /* MSP */
6951 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6953 /* we are in supervisor mode so just check for M flag */
6956 REG_MSP = REG_DA[(word2 >> 12) & 15];
6959 REG_SP = REG_DA[(word2 >> 12) & 15];
6962 m68ki_exception_illegal();
6964 case 0x804: /* ISP */
6965 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6969 REG_SP = REG_DA[(word2 >> 12) & 15];
6972 REG_ISP = REG_DA[(word2 >> 12) & 15];
6975 m68ki_exception_illegal();
6977 case 0x003: /* TC */
6978 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6983 m68ki_exception_illegal();
6985 case 0x004: /* ITT0 */
6986 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6991 m68ki_exception_illegal();
6993 case 0x005: /* ITT1 */
6994 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6999 m68ki_exception_illegal();
7001 case 0x006: /* DTT0 */
7002 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7007 m68ki_exception_illegal();
7009 case 0x007: /* DTT1 */
7010 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7015 m68ki_exception_illegal();
7017 case 0x805: /* MMUSR */
7018 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7023 m68ki_exception_illegal();
7025 case 0x806: /* URP */
7026 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7031 m68ki_exception_illegal();
7033 case 0x807: /* SRP */
7034 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7039 m68ki_exception_illegal();
7042 m68ki_exception_illegal();
7046 m68ki_exception_privilege_violation();
7049 m68ki_exception_illegal();
7053 M68KMAKE_OP(movem, 16, re, pd)
7056 uint register_list = OPER_I_16();
7061 if(register_list & (1 << i))
7064 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7069 USE_CYCLES(count<<CYC_MOVEM_W);
7073 M68KMAKE_OP(movem, 16, re, .)
7076 uint register_list = OPER_I_16();
7077 uint ea = M68KMAKE_GET_EA_AY_16;
7081 if(register_list & (1 << i))
7083 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7088 USE_CYCLES(count<<CYC_MOVEM_W);
7092 M68KMAKE_OP(movem, 32, re, pd)
7095 uint register_list = OPER_I_16();
7100 if(register_list & (1 << i))
7103 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
7104 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7109 USE_CYCLES(count<<CYC_MOVEM_L);
7113 M68KMAKE_OP(movem, 32, re, .)
7116 uint register_list = OPER_I_16();
7117 uint ea = M68KMAKE_GET_EA_AY_32;
7121 if(register_list & (1 << i))
7123 m68ki_write_32(ea, REG_DA[i]);
7128 USE_CYCLES(count<<CYC_MOVEM_L);
7132 M68KMAKE_OP(movem, 16, er, pi)
7135 uint register_list = OPER_I_16();
7140 if(register_list & (1 << i))
7142 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7148 USE_CYCLES(count<<CYC_MOVEM_W);
7152 M68KMAKE_OP(movem, 16, er, pcdi)
7155 uint register_list = OPER_I_16();
7156 uint ea = EA_PCDI_16();
7160 if(register_list & (1 << i))
7162 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7167 USE_CYCLES(count<<CYC_MOVEM_W);
7171 M68KMAKE_OP(movem, 16, er, pcix)
7174 uint register_list = OPER_I_16();
7175 uint ea = EA_PCIX_16();
7179 if(register_list & (1 << i))
7181 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7186 USE_CYCLES(count<<CYC_MOVEM_W);
7190 M68KMAKE_OP(movem, 16, er, .)
7193 uint register_list = OPER_I_16();
7194 uint ea = M68KMAKE_GET_EA_AY_16;
7198 if(register_list & (1 << i))
7200 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7205 USE_CYCLES(count<<CYC_MOVEM_W);
7209 M68KMAKE_OP(movem, 32, er, pi)
7212 uint register_list = OPER_I_16();
7217 if(register_list & (1 << i))
7219 REG_DA[i] = m68ki_read_32(ea);
7225 USE_CYCLES(count<<CYC_MOVEM_L);
7229 M68KMAKE_OP(movem, 32, er, pcdi)
7232 uint register_list = OPER_I_16();
7233 uint ea = EA_PCDI_32();
7237 if(register_list & (1 << i))
7239 REG_DA[i] = m68ki_read_pcrel_32(ea);
7244 USE_CYCLES(count<<CYC_MOVEM_L);
7248 M68KMAKE_OP(movem, 32, er, pcix)
7251 uint register_list = OPER_I_16();
7252 uint ea = EA_PCIX_32();
7256 if(register_list & (1 << i))
7258 REG_DA[i] = m68ki_read_pcrel_32(ea);
7263 USE_CYCLES(count<<CYC_MOVEM_L);
7267 M68KMAKE_OP(movem, 32, er, .)
7270 uint register_list = OPER_I_16();
7271 uint ea = M68KMAKE_GET_EA_AY_32;
7275 if(register_list & (1 << i))
7277 REG_DA[i] = m68ki_read_32(ea);
7282 USE_CYCLES(count<<CYC_MOVEM_L);
7286 M68KMAKE_OP(movep, 16, re, .)
7288 uint ea = EA_AY_DI_16();
7291 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
7292 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7296 M68KMAKE_OP(movep, 32, re, .)
7298 uint ea = EA_AY_DI_32();
7301 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
7302 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7303 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7304 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7308 M68KMAKE_OP(movep, 16, er, .)
7310 uint ea = EA_AY_DI_16();
7313 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
7317 M68KMAKE_OP(movep, 32, er, .)
7319 uint ea = EA_AY_DI_32();
7321 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
7322 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
7326 M68KMAKE_OP(moves, 8, ., .)
7328 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7332 uint word2 = OPER_I_16();
7333 uint ea = M68KMAKE_GET_EA_AY_8;
7335 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7336 if(BIT_B(word2)) /* Register to memory */
7338 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7341 if(BIT_F(word2)) /* Memory to address register */
7343 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
7344 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7348 /* Memory to data register */
7349 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
7350 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7354 m68ki_exception_privilege_violation();
7357 m68ki_exception_illegal();
7361 M68KMAKE_OP(moves, 16, ., .)
7363 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7367 uint word2 = OPER_I_16();
7368 uint ea = M68KMAKE_GET_EA_AY_16;
7370 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7371 if(BIT_B(word2)) /* Register to memory */
7373 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7376 if(BIT_F(word2)) /* Memory to address register */
7378 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
7379 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7383 /* Memory to data register */
7384 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
7385 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7389 m68ki_exception_privilege_violation();
7392 m68ki_exception_illegal();
7396 M68KMAKE_OP(moves, 32, ., .)
7398 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7402 uint word2 = OPER_I_16();
7403 uint ea = M68KMAKE_GET_EA_AY_32;
7405 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7406 if(BIT_B(word2)) /* Register to memory */
7408 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7409 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7413 /* Memory to register */
7414 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
7415 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7419 m68ki_exception_privilege_violation();
7422 m68ki_exception_illegal();
7426 M68KMAKE_OP(moveq, 32, ., .)
7428 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7430 FLAG_N = NFLAG_32(res);
7432 FLAG_V = VFLAG_CLEAR;
7433 FLAG_C = CFLAG_CLEAR;
7437 M68KMAKE_OP(move16, 32, ., .)
7439 uint16 w2 = OPER_I_16();
7440 int ax = REG_IR & 7;
7441 int ay = (w2 >> 12) & 7;
7443 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
7444 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
7445 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
7446 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
7453 M68KMAKE_OP(muls, 16, ., d)
7456 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7461 FLAG_N = NFLAG_32(res);
7462 FLAG_V = VFLAG_CLEAR;
7463 FLAG_C = CFLAG_CLEAR;
7467 M68KMAKE_OP(muls, 16, ., .)
7470 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7475 FLAG_N = NFLAG_32(res);
7476 FLAG_V = VFLAG_CLEAR;
7477 FLAG_C = CFLAG_CLEAR;
7481 M68KMAKE_OP(mulu, 16, ., d)
7484 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7489 FLAG_N = NFLAG_32(res);
7490 FLAG_V = VFLAG_CLEAR;
7491 FLAG_C = CFLAG_CLEAR;
7495 M68KMAKE_OP(mulu, 16, ., .)
7498 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7503 FLAG_N = NFLAG_32(res);
7504 FLAG_V = VFLAG_CLEAR;
7505 FLAG_C = CFLAG_CLEAR;
7509 M68KMAKE_OP(mull, 32, ., d)
7513 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7515 uint word2 = OPER_I_16();
7517 uint64 dst = REG_D[(word2 >> 12) & 7];
7520 FLAG_C = CFLAG_CLEAR;
7522 if(BIT_B(word2)) /* signed */
7524 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7527 FLAG_Z = MASK_OUT_ABOVE_32(res);
7528 FLAG_N = NFLAG_32(res);
7529 FLAG_V = ((sint64)res != (sint32)res)<<7;
7530 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7533 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7534 FLAG_N = NFLAG_64(res);
7535 FLAG_V = VFLAG_CLEAR;
7536 REG_D[word2 & 7] = (res >> 32);
7537 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7544 FLAG_Z = MASK_OUT_ABOVE_32(res);
7545 FLAG_N = NFLAG_32(res);
7546 FLAG_V = (res > 0xffffffff)<<7;
7547 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7550 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7551 FLAG_N = NFLAG_64(res);
7552 FLAG_V = VFLAG_CLEAR;
7553 REG_D[word2 & 7] = (res >> 32);
7554 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7557 m68ki_exception_illegal();
7561 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7563 uint word2 = OPER_I_16();
7565 uint dst = REG_D[(word2 >> 12) & 7];
7566 uint neg = GET_MSB_32(src ^ dst);
7578 FLAG_C = CFLAG_CLEAR;
7580 if(BIT_B(word2)) /* signed */
7583 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7585 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7588 src1 = MASK_OUT_ABOVE_16(src);
7590 dst1 = MASK_OUT_ABOVE_16(dst);
7599 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7600 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7602 if(BIT_B(word2) && neg)
7604 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7605 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7610 REG_D[word2 & 7] = hi;
7611 REG_D[(word2 >> 12) & 7] = lo;
7612 FLAG_N = NFLAG_32(hi);
7614 FLAG_V = VFLAG_CLEAR;
7618 REG_D[(word2 >> 12) & 7] = lo;
7619 FLAG_N = NFLAG_32(lo);
7622 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7624 FLAG_V = (hi != 0) << 7;
7627 m68ki_exception_illegal();
7633 M68KMAKE_OP(mull, 32, ., .)
7637 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7639 uint word2 = OPER_I_16();
7640 uint64 src = M68KMAKE_GET_OPER_AY_32;
7641 uint64 dst = REG_D[(word2 >> 12) & 7];
7644 FLAG_C = CFLAG_CLEAR;
7646 if(BIT_B(word2)) /* signed */
7648 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7651 FLAG_Z = MASK_OUT_ABOVE_32(res);
7652 FLAG_N = NFLAG_32(res);
7653 FLAG_V = ((sint64)res != (sint32)res)<<7;
7654 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7657 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7658 FLAG_N = NFLAG_64(res);
7659 FLAG_V = VFLAG_CLEAR;
7660 REG_D[word2 & 7] = (res >> 32);
7661 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7668 FLAG_Z = MASK_OUT_ABOVE_32(res);
7669 FLAG_N = NFLAG_32(res);
7670 FLAG_V = (res > 0xffffffff)<<7;
7671 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7674 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7675 FLAG_N = NFLAG_64(res);
7676 FLAG_V = VFLAG_CLEAR;
7677 REG_D[word2 & 7] = (res >> 32);
7678 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7681 m68ki_exception_illegal();
7685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7687 uint word2 = OPER_I_16();
7688 uint src = M68KMAKE_GET_OPER_AY_32;
7689 uint dst = REG_D[(word2 >> 12) & 7];
7690 uint neg = GET_MSB_32(src ^ dst);
7702 FLAG_C = CFLAG_CLEAR;
7704 if(BIT_B(word2)) /* signed */
7707 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7709 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7712 src1 = MASK_OUT_ABOVE_16(src);
7714 dst1 = MASK_OUT_ABOVE_16(dst);
7723 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7724 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7726 if(BIT_B(word2) && neg)
7728 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7729 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7734 REG_D[word2 & 7] = hi;
7735 REG_D[(word2 >> 12) & 7] = lo;
7736 FLAG_N = NFLAG_32(hi);
7738 FLAG_V = VFLAG_CLEAR;
7742 REG_D[(word2 >> 12) & 7] = lo;
7743 FLAG_N = NFLAG_32(lo);
7746 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7748 FLAG_V = (hi != 0) << 7;
7751 m68ki_exception_illegal();
7757 M68KMAKE_OP(nbcd, 8, ., d)
7761 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7765 FLAG_V = ~res; /* Undefined V behavior */
7767 if((res & 0x0f) == 0xa)
7768 res = (res & 0xf0) + 0x10;
7770 res = MASK_OUT_ABOVE_8(res);
7772 FLAG_V &= res; /* Undefined V behavior part II */
7774 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7782 FLAG_V = VFLAG_CLEAR;
7783 FLAG_C = CFLAG_CLEAR;
7784 FLAG_X = XFLAG_CLEAR;
7786 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7790 M68KMAKE_OP(nbcd, 8, ., .)
7792 uint ea = M68KMAKE_GET_EA_AY_8;
7793 uint dst = m68ki_read_8(ea);
7794 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7798 FLAG_V = ~res; /* Undefined V behavior */
7800 if((res & 0x0f) == 0xa)
7801 res = (res & 0xf0) + 0x10;
7803 res = MASK_OUT_ABOVE_8(res);
7805 FLAG_V &= res; /* Undefined V behavior part II */
7807 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7815 FLAG_V = VFLAG_CLEAR;
7816 FLAG_C = CFLAG_CLEAR;
7817 FLAG_X = XFLAG_CLEAR;
7819 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7823 M68KMAKE_OP(neg, 8, ., d)
7826 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7828 FLAG_N = NFLAG_8(res);
7829 FLAG_C = FLAG_X = CFLAG_8(res);
7830 FLAG_V = *r_dst & res;
7831 FLAG_Z = MASK_OUT_ABOVE_8(res);
7833 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7837 M68KMAKE_OP(neg, 8, ., .)
7839 uint ea = M68KMAKE_GET_EA_AY_8;
7840 uint src = m68ki_read_8(ea);
7843 FLAG_N = NFLAG_8(res);
7844 FLAG_C = FLAG_X = CFLAG_8(res);
7846 FLAG_Z = MASK_OUT_ABOVE_8(res);
7848 m68ki_write_8(ea, FLAG_Z);
7852 M68KMAKE_OP(neg, 16, ., d)
7855 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7857 FLAG_N = NFLAG_16(res);
7858 FLAG_C = FLAG_X = CFLAG_16(res);
7859 FLAG_V = (*r_dst & res)>>8;
7860 FLAG_Z = MASK_OUT_ABOVE_16(res);
7862 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7866 M68KMAKE_OP(neg, 16, ., .)
7868 uint ea = M68KMAKE_GET_EA_AY_16;
7869 uint src = m68ki_read_16(ea);
7872 FLAG_N = NFLAG_16(res);
7873 FLAG_C = FLAG_X = CFLAG_16(res);
7874 FLAG_V = (src & res)>>8;
7875 FLAG_Z = MASK_OUT_ABOVE_16(res);
7877 m68ki_write_16(ea, FLAG_Z);
7881 M68KMAKE_OP(neg, 32, ., d)
7884 uint res = 0 - *r_dst;
7886 FLAG_N = NFLAG_32(res);
7887 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
7888 FLAG_V = (*r_dst & res)>>24;
7889 FLAG_Z = MASK_OUT_ABOVE_32(res);
7895 M68KMAKE_OP(neg, 32, ., .)
7897 uint ea = M68KMAKE_GET_EA_AY_32;
7898 uint src = m68ki_read_32(ea);
7901 FLAG_N = NFLAG_32(res);
7902 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
7903 FLAG_V = (src & res)>>24;
7904 FLAG_Z = MASK_OUT_ABOVE_32(res);
7906 m68ki_write_32(ea, FLAG_Z);
7910 M68KMAKE_OP(negx, 8, ., d)
7913 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
7915 FLAG_N = NFLAG_8(res);
7916 FLAG_X = FLAG_C = CFLAG_8(res);
7917 FLAG_V = *r_dst & res;
7919 res = MASK_OUT_ABOVE_8(res);
7922 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7926 M68KMAKE_OP(negx, 8, ., .)
7928 uint ea = M68KMAKE_GET_EA_AY_8;
7929 uint src = m68ki_read_8(ea);
7930 uint res = 0 - src - XFLAG_AS_1();
7932 FLAG_N = NFLAG_8(res);
7933 FLAG_X = FLAG_C = CFLAG_8(res);
7936 res = MASK_OUT_ABOVE_8(res);
7939 m68ki_write_8(ea, res);
7943 M68KMAKE_OP(negx, 16, ., d)
7946 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
7948 FLAG_N = NFLAG_16(res);
7949 FLAG_X = FLAG_C = CFLAG_16(res);
7950 FLAG_V = (*r_dst & res)>>8;
7952 res = MASK_OUT_ABOVE_16(res);
7955 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7959 M68KMAKE_OP(negx, 16, ., .)
7961 uint ea = M68KMAKE_GET_EA_AY_16;
7962 uint src = m68ki_read_16(ea);
7963 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
7965 FLAG_N = NFLAG_16(res);
7966 FLAG_X = FLAG_C = CFLAG_16(res);
7967 FLAG_V = (src & res)>>8;
7969 res = MASK_OUT_ABOVE_16(res);
7972 m68ki_write_16(ea, res);
7976 M68KMAKE_OP(negx, 32, ., d)
7979 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
7981 FLAG_N = NFLAG_32(res);
7982 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
7983 FLAG_V = (*r_dst & res)>>24;
7985 res = MASK_OUT_ABOVE_32(res);
7992 M68KMAKE_OP(negx, 32, ., .)
7994 uint ea = M68KMAKE_GET_EA_AY_32;
7995 uint src = m68ki_read_32(ea);
7996 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
7998 FLAG_N = NFLAG_32(res);
7999 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
8000 FLAG_V = (src & res)>>24;
8002 res = MASK_OUT_ABOVE_32(res);
8005 m68ki_write_32(ea, res);
8009 M68KMAKE_OP(nop, 0, ., .)
8011 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8015 M68KMAKE_OP(not, 8, ., d)
8018 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8020 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8022 FLAG_N = NFLAG_8(res);
8024 FLAG_C = CFLAG_CLEAR;
8025 FLAG_V = VFLAG_CLEAR;
8029 M68KMAKE_OP(not, 8, ., .)
8031 uint ea = M68KMAKE_GET_EA_AY_8;
8032 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
8034 m68ki_write_8(ea, res);
8036 FLAG_N = NFLAG_8(res);
8038 FLAG_C = CFLAG_CLEAR;
8039 FLAG_V = VFLAG_CLEAR;
8043 M68KMAKE_OP(not, 16, ., d)
8046 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8048 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8050 FLAG_N = NFLAG_16(res);
8052 FLAG_C = CFLAG_CLEAR;
8053 FLAG_V = VFLAG_CLEAR;
8057 M68KMAKE_OP(not, 16, ., .)
8059 uint ea = M68KMAKE_GET_EA_AY_16;
8060 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
8062 m68ki_write_16(ea, res);
8064 FLAG_N = NFLAG_16(res);
8066 FLAG_C = CFLAG_CLEAR;
8067 FLAG_V = VFLAG_CLEAR;
8071 M68KMAKE_OP(not, 32, ., d)
8074 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8076 FLAG_N = NFLAG_32(res);
8078 FLAG_C = CFLAG_CLEAR;
8079 FLAG_V = VFLAG_CLEAR;
8083 M68KMAKE_OP(not, 32, ., .)
8085 uint ea = M68KMAKE_GET_EA_AY_32;
8086 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
8088 m68ki_write_32(ea, res);
8090 FLAG_N = NFLAG_32(res);
8092 FLAG_C = CFLAG_CLEAR;
8093 FLAG_V = VFLAG_CLEAR;
8097 M68KMAKE_OP(or, 8, er, d)
8099 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8101 FLAG_N = NFLAG_8(res);
8103 FLAG_C = CFLAG_CLEAR;
8104 FLAG_V = VFLAG_CLEAR;
8108 M68KMAKE_OP(or, 8, er, .)
8110 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8112 FLAG_N = NFLAG_8(res);
8114 FLAG_C = CFLAG_CLEAR;
8115 FLAG_V = VFLAG_CLEAR;
8119 M68KMAKE_OP(or, 16, er, d)
8121 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8123 FLAG_N = NFLAG_16(res);
8125 FLAG_C = CFLAG_CLEAR;
8126 FLAG_V = VFLAG_CLEAR;
8130 M68KMAKE_OP(or, 16, er, .)
8132 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8134 FLAG_N = NFLAG_16(res);
8136 FLAG_C = CFLAG_CLEAR;
8137 FLAG_V = VFLAG_CLEAR;
8141 M68KMAKE_OP(or, 32, er, d)
8143 uint res = DX |= DY;
8145 FLAG_N = NFLAG_32(res);
8147 FLAG_C = CFLAG_CLEAR;
8148 FLAG_V = VFLAG_CLEAR;
8152 M68KMAKE_OP(or, 32, er, .)
8154 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8156 FLAG_N = NFLAG_32(res);
8158 FLAG_C = CFLAG_CLEAR;
8159 FLAG_V = VFLAG_CLEAR;
8163 M68KMAKE_OP(or, 8, re, .)
8165 uint ea = M68KMAKE_GET_EA_AY_8;
8166 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
8168 m68ki_write_8(ea, res);
8170 FLAG_N = NFLAG_8(res);
8172 FLAG_C = CFLAG_CLEAR;
8173 FLAG_V = VFLAG_CLEAR;
8177 M68KMAKE_OP(or, 16, re, .)
8179 uint ea = M68KMAKE_GET_EA_AY_16;
8180 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
8182 m68ki_write_16(ea, res);
8184 FLAG_N = NFLAG_16(res);
8186 FLAG_C = CFLAG_CLEAR;
8187 FLAG_V = VFLAG_CLEAR;
8191 M68KMAKE_OP(or, 32, re, .)
8193 uint ea = M68KMAKE_GET_EA_AY_32;
8194 uint res = DX | m68ki_read_32(ea);
8196 m68ki_write_32(ea, res);
8198 FLAG_N = NFLAG_32(res);
8200 FLAG_C = CFLAG_CLEAR;
8201 FLAG_V = VFLAG_CLEAR;
8205 M68KMAKE_OP(ori, 8, ., d)
8207 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
8209 FLAG_N = NFLAG_8(res);
8211 FLAG_C = CFLAG_CLEAR;
8212 FLAG_V = VFLAG_CLEAR;
8216 M68KMAKE_OP(ori, 8, ., .)
8218 uint src = OPER_I_8();
8219 uint ea = M68KMAKE_GET_EA_AY_8;
8220 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
8222 m68ki_write_8(ea, res);
8224 FLAG_N = NFLAG_8(res);
8226 FLAG_C = CFLAG_CLEAR;
8227 FLAG_V = VFLAG_CLEAR;
8231 M68KMAKE_OP(ori, 16, ., d)
8233 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
8235 FLAG_N = NFLAG_16(res);
8237 FLAG_C = CFLAG_CLEAR;
8238 FLAG_V = VFLAG_CLEAR;
8242 M68KMAKE_OP(ori, 16, ., .)
8244 uint src = OPER_I_16();
8245 uint ea = M68KMAKE_GET_EA_AY_16;
8246 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
8248 m68ki_write_16(ea, res);
8250 FLAG_N = NFLAG_16(res);
8252 FLAG_C = CFLAG_CLEAR;
8253 FLAG_V = VFLAG_CLEAR;
8257 M68KMAKE_OP(ori, 32, ., d)
8259 uint res = DY |= OPER_I_32();
8261 FLAG_N = NFLAG_32(res);
8263 FLAG_C = CFLAG_CLEAR;
8264 FLAG_V = VFLAG_CLEAR;
8268 M68KMAKE_OP(ori, 32, ., .)
8270 uint src = OPER_I_32();
8271 uint ea = M68KMAKE_GET_EA_AY_32;
8272 uint res = src | m68ki_read_32(ea);
8274 m68ki_write_32(ea, res);
8276 FLAG_N = NFLAG_32(res);
8278 FLAG_C = CFLAG_CLEAR;
8279 FLAG_V = VFLAG_CLEAR;
8283 M68KMAKE_OP(ori, 16, toc, .)
8285 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_8());
8289 M68KMAKE_OP(ori, 16, tos, .)
8293 uint src = OPER_I_16();
8294 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8295 m68ki_set_sr(m68ki_get_sr() | src);
8298 m68ki_exception_privilege_violation();
8302 M68KMAKE_OP(pack, 16, rr, .)
8304 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8306 /* Note: DX and DY are reversed in Motorola's docs */
8307 uint src = DY + OPER_I_16();
8310 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8313 m68ki_exception_illegal();
8317 M68KMAKE_OP(pack, 16, mm, ax7)
8319 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8321 /* Note: AX and AY are reversed in Motorola's docs */
8322 uint ea_src = EA_AY_PD_8();
8323 uint src = m68ki_read_8(ea_src);
8324 ea_src = EA_AY_PD_8();
8325 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8327 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8330 m68ki_exception_illegal();
8334 M68KMAKE_OP(pack, 16, mm, ay7)
8336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8338 /* Note: AX and AY are reversed in Motorola's docs */
8339 uint ea_src = EA_A7_PD_8();
8340 uint src = m68ki_read_8(ea_src);
8341 ea_src = EA_A7_PD_8();
8342 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8344 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8347 m68ki_exception_illegal();
8351 M68KMAKE_OP(pack, 16, mm, axy7)
8353 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8355 uint ea_src = EA_A7_PD_8();
8356 uint src = m68ki_read_8(ea_src);
8357 ea_src = EA_A7_PD_8();
8358 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8360 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8363 m68ki_exception_illegal();
8367 M68KMAKE_OP(pack, 16, mm, .)
8369 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8371 /* Note: AX and AY are reversed in Motorola's docs */
8372 uint ea_src = EA_AY_PD_8();
8373 uint src = m68ki_read_8(ea_src);
8374 ea_src = EA_AY_PD_8();
8375 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8377 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8380 m68ki_exception_illegal();
8384 M68KMAKE_OP(pea, 32, ., .)
8386 uint ea = M68KMAKE_GET_EA_AY_32;
8391 M68KMAKE_OP(pflush, 32, ., .)
8393 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8395 fprintf(stderr,"68040: unhandled PFLUSH\n");
8398 m68ki_exception_1111();
8401 M68KMAKE_OP(pmmu, 32, ., .)
8403 if ((CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) && (HAS_PMMU))
8409 m68ki_exception_1111();
8413 M68KMAKE_OP(reset, 0, ., .)
8417 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8418 USE_CYCLES(CYC_RESET);
8421 m68ki_exception_privilege_violation();
8425 M68KMAKE_OP(ror, 8, s, .)
8428 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8429 uint shift = orig_shift & 7;
8430 uint src = MASK_OUT_ABOVE_8(*r_dst);
8431 uint res = ROR_8(src, shift);
8434 USE_CYCLES(orig_shift<<CYC_SHIFT);
8436 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8438 FLAG_N = NFLAG_8(res);
8440 FLAG_C = src << (9-orig_shift);
8441 FLAG_V = VFLAG_CLEAR;
8445 M68KMAKE_OP(ror, 16, s, .)
8448 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8449 uint src = MASK_OUT_ABOVE_16(*r_dst);
8450 uint res = ROR_16(src, shift);
8453 USE_CYCLES(shift<<CYC_SHIFT);
8455 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8457 FLAG_N = NFLAG_16(res);
8459 FLAG_C = src << (9-shift);
8460 FLAG_V = VFLAG_CLEAR;
8464 M68KMAKE_OP(ror, 32, s, .)
8467 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8468 uint64 src = *r_dst;
8469 uint res = ROR_32(src, shift);
8472 USE_CYCLES(shift<<CYC_SHIFT);
8476 FLAG_N = NFLAG_32(res);
8478 FLAG_C = src << (9-shift);
8479 FLAG_V = VFLAG_CLEAR;
8483 M68KMAKE_OP(ror, 8, r, .)
8486 uint orig_shift = DX & 0x3f;
8487 uint shift = orig_shift & 7;
8488 uint src = MASK_OUT_ABOVE_8(*r_dst);
8489 uint res = ROR_8(src, shift);
8493 USE_CYCLES(orig_shift<<CYC_SHIFT);
8495 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8496 FLAG_C = src << (8-((shift-1)&7));
8497 FLAG_N = NFLAG_8(res);
8499 FLAG_V = VFLAG_CLEAR;
8503 FLAG_C = CFLAG_CLEAR;
8504 FLAG_N = NFLAG_8(src);
8506 FLAG_V = VFLAG_CLEAR;
8510 M68KMAKE_OP(ror, 16, r, .)
8513 uint orig_shift = DX & 0x3f;
8514 uint shift = orig_shift & 15;
8515 uint src = MASK_OUT_ABOVE_16(*r_dst);
8516 uint res = ROR_16(src, shift);
8520 USE_CYCLES(orig_shift<<CYC_SHIFT);
8522 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8523 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8524 FLAG_N = NFLAG_16(res);
8526 FLAG_V = VFLAG_CLEAR;
8530 FLAG_C = CFLAG_CLEAR;
8531 FLAG_N = NFLAG_16(src);
8533 FLAG_V = VFLAG_CLEAR;
8537 M68KMAKE_OP(ror, 32, r, .)
8540 uint orig_shift = DX & 0x3f;
8541 uint shift = orig_shift & 31;
8542 uint64 src = *r_dst;
8543 uint res = ROR_32(src, shift);
8547 USE_CYCLES(orig_shift<<CYC_SHIFT);
8550 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8551 FLAG_N = NFLAG_32(res);
8553 FLAG_V = VFLAG_CLEAR;
8557 FLAG_C = CFLAG_CLEAR;
8558 FLAG_N = NFLAG_32(src);
8560 FLAG_V = VFLAG_CLEAR;
8564 M68KMAKE_OP(ror, 16, ., .)
8566 uint ea = M68KMAKE_GET_EA_AY_16;
8567 uint src = m68ki_read_16(ea);
8568 uint res = ROR_16(src, 1);
8570 m68ki_write_16(ea, res);
8572 FLAG_N = NFLAG_16(res);
8575 FLAG_V = VFLAG_CLEAR;
8579 M68KMAKE_OP(rol, 8, s, .)
8582 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8583 uint shift = orig_shift & 7;
8584 uint src = MASK_OUT_ABOVE_8(*r_dst);
8585 uint res = ROL_8(src, shift);
8588 USE_CYCLES(orig_shift<<CYC_SHIFT);
8590 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8592 FLAG_N = NFLAG_8(res);
8594 FLAG_C = src << orig_shift;
8595 FLAG_V = VFLAG_CLEAR;
8599 M68KMAKE_OP(rol, 16, s, .)
8602 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8603 uint src = MASK_OUT_ABOVE_16(*r_dst);
8604 uint res = ROL_16(src, shift);
8607 USE_CYCLES(shift<<CYC_SHIFT);
8609 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8611 FLAG_N = NFLAG_16(res);
8613 FLAG_C = src >> (8-shift);
8614 FLAG_V = VFLAG_CLEAR;
8618 M68KMAKE_OP(rol, 32, s, .)
8621 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8622 uint64 src = *r_dst;
8623 uint res = ROL_32(src, shift);
8626 USE_CYCLES(shift<<CYC_SHIFT);
8630 FLAG_N = NFLAG_32(res);
8632 FLAG_C = src >> (24-shift);
8633 FLAG_V = VFLAG_CLEAR;
8637 M68KMAKE_OP(rol, 8, r, .)
8640 uint orig_shift = DX & 0x3f;
8641 uint shift = orig_shift & 7;
8642 uint src = MASK_OUT_ABOVE_8(*r_dst);
8643 uint res = ROL_8(src, shift);
8647 USE_CYCLES(orig_shift<<CYC_SHIFT);
8651 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8652 FLAG_C = src << shift;
8653 FLAG_N = NFLAG_8(res);
8655 FLAG_V = VFLAG_CLEAR;
8658 FLAG_C = (src & 1)<<8;
8659 FLAG_N = NFLAG_8(src);
8661 FLAG_V = VFLAG_CLEAR;
8665 FLAG_C = CFLAG_CLEAR;
8666 FLAG_N = NFLAG_8(src);
8668 FLAG_V = VFLAG_CLEAR;
8672 M68KMAKE_OP(rol, 16, r, .)
8675 uint orig_shift = DX & 0x3f;
8676 uint shift = orig_shift & 15;
8677 uint src = MASK_OUT_ABOVE_16(*r_dst);
8678 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8682 USE_CYCLES(orig_shift<<CYC_SHIFT);
8686 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8687 FLAG_C = (src << shift) >> 8;
8688 FLAG_N = NFLAG_16(res);
8690 FLAG_V = VFLAG_CLEAR;
8693 FLAG_C = (src & 1)<<8;
8694 FLAG_N = NFLAG_16(src);
8696 FLAG_V = VFLAG_CLEAR;
8700 FLAG_C = CFLAG_CLEAR;
8701 FLAG_N = NFLAG_16(src);
8703 FLAG_V = VFLAG_CLEAR;
8707 M68KMAKE_OP(rol, 32, r, .)
8710 uint orig_shift = DX & 0x3f;
8711 uint shift = orig_shift & 31;
8712 uint64 src = *r_dst;
8713 uint res = ROL_32(src, shift);
8717 USE_CYCLES(orig_shift<<CYC_SHIFT);
8721 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8722 FLAG_N = NFLAG_32(res);
8724 FLAG_V = VFLAG_CLEAR;
8728 FLAG_C = CFLAG_CLEAR;
8729 FLAG_N = NFLAG_32(src);
8731 FLAG_V = VFLAG_CLEAR;
8735 M68KMAKE_OP(rol, 16, ., .)
8737 uint ea = M68KMAKE_GET_EA_AY_16;
8738 uint src = m68ki_read_16(ea);
8739 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8741 m68ki_write_16(ea, res);
8743 FLAG_N = NFLAG_16(res);
8746 FLAG_V = VFLAG_CLEAR;
8750 M68KMAKE_OP(roxr, 8, s, .)
8753 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8754 uint src = MASK_OUT_ABOVE_8(*r_dst);
8755 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8758 USE_CYCLES(shift<<CYC_SHIFT);
8760 FLAG_C = FLAG_X = res;
8761 res = MASK_OUT_ABOVE_8(res);
8763 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8765 FLAG_N = NFLAG_8(res);
8767 FLAG_V = VFLAG_CLEAR;
8771 M68KMAKE_OP(roxr, 16, s, .)
8774 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8775 uint src = MASK_OUT_ABOVE_16(*r_dst);
8776 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8779 USE_CYCLES(shift<<CYC_SHIFT);
8781 FLAG_C = FLAG_X = res >> 8;
8782 res = MASK_OUT_ABOVE_16(res);
8784 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8786 FLAG_N = NFLAG_16(res);
8788 FLAG_V = VFLAG_CLEAR;
8792 M68KMAKE_OP(roxr, 32, s, .)
8797 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8798 uint64 src = *r_dst;
8799 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8802 USE_CYCLES(shift<<CYC_SHIFT);
8804 res = ROR_33_64(res, shift);
8806 FLAG_C = FLAG_X = res >> 24;
8807 res = MASK_OUT_ABOVE_32(res);
8811 FLAG_N = NFLAG_32(res);
8813 FLAG_V = VFLAG_CLEAR;
8818 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8820 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8821 uint new_x_flag = src & (1 << (shift - 1));
8824 USE_CYCLES(shift<<CYC_SHIFT);
8828 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8829 FLAG_N = NFLAG_32(res);
8831 FLAG_V = VFLAG_CLEAR;
8837 M68KMAKE_OP(roxr, 8, r, .)
8840 uint orig_shift = DX & 0x3f;
8844 uint shift = orig_shift % 9;
8845 uint src = MASK_OUT_ABOVE_8(*r_dst);
8846 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8848 USE_CYCLES(orig_shift<<CYC_SHIFT);
8850 FLAG_C = FLAG_X = res;
8851 res = MASK_OUT_ABOVE_8(res);
8853 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8854 FLAG_N = NFLAG_8(res);
8856 FLAG_V = VFLAG_CLEAR;
8861 FLAG_N = NFLAG_8(*r_dst);
8862 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8863 FLAG_V = VFLAG_CLEAR;
8867 M68KMAKE_OP(roxr, 16, r, .)
8870 uint orig_shift = DX & 0x3f;
8874 uint shift = orig_shift % 17;
8875 uint src = MASK_OUT_ABOVE_16(*r_dst);
8876 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8878 USE_CYCLES(orig_shift<<CYC_SHIFT);
8880 FLAG_C = FLAG_X = res >> 8;
8881 res = MASK_OUT_ABOVE_16(res);
8883 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8884 FLAG_N = NFLAG_16(res);
8886 FLAG_V = VFLAG_CLEAR;
8891 FLAG_N = NFLAG_16(*r_dst);
8892 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8893 FLAG_V = VFLAG_CLEAR;
8897 M68KMAKE_OP(roxr, 32, r, .)
8902 uint orig_shift = DX & 0x3f;
8906 uint shift = orig_shift % 33;
8907 uint64 src = *r_dst;
8908 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8910 res = ROR_33_64(res, shift);
8912 USE_CYCLES(orig_shift<<CYC_SHIFT);
8914 FLAG_C = FLAG_X = res >> 24;
8915 res = MASK_OUT_ABOVE_32(res);
8918 FLAG_N = NFLAG_32(res);
8920 FLAG_V = VFLAG_CLEAR;
8925 FLAG_N = NFLAG_32(*r_dst);
8927 FLAG_V = VFLAG_CLEAR;
8932 uint orig_shift = DX & 0x3f;
8933 uint shift = orig_shift % 33;
8935 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8936 uint new_x_flag = src & (1 << (shift - 1));
8939 USE_CYCLES(orig_shift<<CYC_SHIFT);
8944 FLAG_X = (new_x_flag != 0)<<8;
8949 FLAG_N = NFLAG_32(res);
8951 FLAG_V = VFLAG_CLEAR;
8957 M68KMAKE_OP(roxr, 16, ., .)
8959 uint ea = M68KMAKE_GET_EA_AY_16;
8960 uint src = m68ki_read_16(ea);
8961 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
8963 FLAG_C = FLAG_X = res >> 8;
8964 res = MASK_OUT_ABOVE_16(res);
8966 m68ki_write_16(ea, res);
8968 FLAG_N = NFLAG_16(res);
8970 FLAG_V = VFLAG_CLEAR;
8974 M68KMAKE_OP(roxl, 8, s, .)
8977 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8978 uint src = MASK_OUT_ABOVE_8(*r_dst);
8979 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
8982 USE_CYCLES(shift<<CYC_SHIFT);
8984 FLAG_C = FLAG_X = res;
8985 res = MASK_OUT_ABOVE_8(res);
8987 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8989 FLAG_N = NFLAG_8(res);
8991 FLAG_V = VFLAG_CLEAR;
8995 M68KMAKE_OP(roxl, 16, s, .)
8998 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8999 uint src = MASK_OUT_ABOVE_16(*r_dst);
9000 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9003 USE_CYCLES(shift<<CYC_SHIFT);
9005 FLAG_C = FLAG_X = res >> 8;
9006 res = MASK_OUT_ABOVE_16(res);
9008 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9010 FLAG_N = NFLAG_16(res);
9012 FLAG_V = VFLAG_CLEAR;
9016 M68KMAKE_OP(roxl, 32, s, .)
9021 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9022 uint64 src = *r_dst;
9023 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9026 USE_CYCLES(shift<<CYC_SHIFT);
9028 res = ROL_33_64(res, shift);
9030 FLAG_C = FLAG_X = res >> 24;
9031 res = MASK_OUT_ABOVE_32(res);
9035 FLAG_N = NFLAG_32(res);
9037 FLAG_V = VFLAG_CLEAR;
9042 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9044 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9045 uint new_x_flag = src & (1 << (32 - shift));
9048 USE_CYCLES(shift<<CYC_SHIFT);
9052 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9053 FLAG_N = NFLAG_32(res);
9055 FLAG_V = VFLAG_CLEAR;
9061 M68KMAKE_OP(roxl, 8, r, .)
9064 uint orig_shift = DX & 0x3f;
9069 uint shift = orig_shift % 9;
9070 uint src = MASK_OUT_ABOVE_8(*r_dst);
9071 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9073 USE_CYCLES(orig_shift<<CYC_SHIFT);
9075 FLAG_C = FLAG_X = res;
9076 res = MASK_OUT_ABOVE_8(res);
9078 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9079 FLAG_N = NFLAG_8(res);
9081 FLAG_V = VFLAG_CLEAR;
9086 FLAG_N = NFLAG_8(*r_dst);
9087 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9088 FLAG_V = VFLAG_CLEAR;
9092 M68KMAKE_OP(roxl, 16, r, .)
9095 uint orig_shift = DX & 0x3f;
9099 uint shift = orig_shift % 17;
9100 uint src = MASK_OUT_ABOVE_16(*r_dst);
9101 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9103 USE_CYCLES(orig_shift<<CYC_SHIFT);
9105 FLAG_C = FLAG_X = res >> 8;
9106 res = MASK_OUT_ABOVE_16(res);
9108 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9109 FLAG_N = NFLAG_16(res);
9111 FLAG_V = VFLAG_CLEAR;
9116 FLAG_N = NFLAG_16(*r_dst);
9117 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9118 FLAG_V = VFLAG_CLEAR;
9122 M68KMAKE_OP(roxl, 32, r, .)
9127 uint orig_shift = DX & 0x3f;
9131 uint shift = orig_shift % 33;
9132 uint64 src = *r_dst;
9133 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9135 res = ROL_33_64(res, shift);
9137 USE_CYCLES(orig_shift<<CYC_SHIFT);
9139 FLAG_C = FLAG_X = res >> 24;
9140 res = MASK_OUT_ABOVE_32(res);
9143 FLAG_N = NFLAG_32(res);
9145 FLAG_V = VFLAG_CLEAR;
9150 FLAG_N = NFLAG_32(*r_dst);
9152 FLAG_V = VFLAG_CLEAR;
9157 uint orig_shift = DX & 0x3f;
9158 uint shift = orig_shift % 33;
9160 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9161 uint new_x_flag = src & (1 << (32 - shift));
9164 USE_CYCLES(orig_shift<<CYC_SHIFT);
9169 FLAG_X = (new_x_flag != 0)<<8;
9174 FLAG_N = NFLAG_32(res);
9176 FLAG_V = VFLAG_CLEAR;
9182 M68KMAKE_OP(roxl, 16, ., .)
9184 uint ea = M68KMAKE_GET_EA_AY_16;
9185 uint src = m68ki_read_16(ea);
9186 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9188 FLAG_C = FLAG_X = res >> 8;
9189 res = MASK_OUT_ABOVE_16(res);
9191 m68ki_write_16(ea, res);
9193 FLAG_N = NFLAG_16(res);
9195 FLAG_V = VFLAG_CLEAR;
9199 M68KMAKE_OP(rtd, 32, ., .)
9201 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9203 uint new_pc = m68ki_pull_32();
9205 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9206 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
9210 m68ki_exception_illegal();
9214 M68KMAKE_OP(rte, 32, ., .)
9222 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9223 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9225 if(CPU_TYPE_IS_000(CPU_TYPE))
9227 new_sr = m68ki_pull_16();
9228 new_pc = m68ki_pull_32();
9230 m68ki_set_sr(new_sr);
9232 CPU_INSTR_MODE = INSTRUCTION_YES;
9233 CPU_RUN_MODE = RUN_MODE_NORMAL;
9238 if(CPU_TYPE_IS_010(CPU_TYPE))
9240 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9241 if(format_word == 0)
9243 new_sr = m68ki_pull_16();
9244 new_pc = m68ki_pull_32();
9245 m68ki_fake_pull_16(); /* format word */
9247 m68ki_set_sr(new_sr);
9248 CPU_INSTR_MODE = INSTRUCTION_YES;
9249 CPU_RUN_MODE = RUN_MODE_NORMAL;
9251 } else if (format_word == 8) {
9252 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
9253 new_sr = m68ki_pull_16();
9254 new_pc = m68ki_pull_32();
9255 m68ki_fake_pull_16(); /* format word */
9256 m68ki_fake_pull_16(); /* special status word */
9257 m68ki_fake_pull_32(); /* fault address */
9258 m68ki_fake_pull_16(); /* unused/reserved */
9259 m68ki_fake_pull_16(); /* data output buffer */
9260 m68ki_fake_pull_16(); /* unused/reserved */
9261 m68ki_fake_pull_16(); /* data input buffer */
9262 m68ki_fake_pull_16(); /* unused/reserved */
9263 m68ki_fake_pull_16(); /* instruction input buffer */
9264 m68ki_fake_pull_32(); /* internal information, 16 words */
9265 m68ki_fake_pull_32(); /* (actually, we use 8 DWORDs) */
9266 m68ki_fake_pull_32();
9267 m68ki_fake_pull_32();
9268 m68ki_fake_pull_32();
9269 m68ki_fake_pull_32();
9270 m68ki_fake_pull_32();
9271 m68ki_fake_pull_32();
9273 m68ki_set_sr(new_sr);
9274 CPU_INSTR_MODE = INSTRUCTION_YES;
9275 CPU_RUN_MODE = RUN_MODE_NORMAL;
9278 CPU_INSTR_MODE = INSTRUCTION_YES;
9279 CPU_RUN_MODE = RUN_MODE_NORMAL;
9280 /* Not handling other exception types (9) */
9281 m68ki_exception_format_error();
9285 /* Otherwise it's 020 */
9287 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9290 case 0: /* Normal */
9291 new_sr = m68ki_pull_16();
9292 new_pc = m68ki_pull_32();
9293 m68ki_fake_pull_16(); /* format word */
9295 m68ki_set_sr(new_sr);
9296 CPU_INSTR_MODE = INSTRUCTION_YES;
9297 CPU_RUN_MODE = RUN_MODE_NORMAL;
9299 case 1: /* Throwaway */
9300 new_sr = m68ki_pull_16();
9301 m68ki_fake_pull_32(); /* program counter */
9302 m68ki_fake_pull_16(); /* format word */
9303 m68ki_set_sr_noint(new_sr);
9306 new_sr = m68ki_pull_16();
9307 new_pc = m68ki_pull_32();
9308 m68ki_fake_pull_16(); /* format word */
9309 m68ki_fake_pull_32(); /* address */
9311 m68ki_set_sr(new_sr);
9312 CPU_INSTR_MODE = INSTRUCTION_YES;
9313 CPU_RUN_MODE = RUN_MODE_NORMAL;
9316 /* Not handling long or short bus fault */
9317 CPU_INSTR_MODE = INSTRUCTION_YES;
9318 CPU_RUN_MODE = RUN_MODE_NORMAL;
9319 m68ki_exception_format_error();
9322 m68ki_exception_privilege_violation();
9326 M68KMAKE_OP(rtm, 32, ., .)
9328 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9330 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9331 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9332 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9333 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
9336 m68ki_exception_illegal();
9340 M68KMAKE_OP(rtr, 32, ., .)
9342 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9343 m68ki_set_ccr(m68ki_pull_16());
9344 m68ki_jump(m68ki_pull_32());
9348 M68KMAKE_OP(rts, 32, ., .)
9350 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9351 m68ki_jump(m68ki_pull_32());
9355 M68KMAKE_OP(sbcd, 8, rr, .)
9360 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9362 FLAG_V = ~res; /* Undefined V behavior */
9366 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9367 FLAG_X = FLAG_C = (res > 0x99) << 8;
9371 res = MASK_OUT_ABOVE_8(res);
9373 FLAG_V &= res; /* Undefined V behavior part II */
9374 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9377 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9381 M68KMAKE_OP(sbcd, 8, mm, ax7)
9383 uint src = OPER_AY_PD_8();
9384 uint ea = EA_A7_PD_8();
9385 uint dst = m68ki_read_8(ea);
9386 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9388 FLAG_V = ~res; /* Undefined V behavior */
9392 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9393 FLAG_X = FLAG_C = (res > 0x99) << 8;
9397 res = MASK_OUT_ABOVE_8(res);
9399 FLAG_V &= res; /* Undefined V behavior part II */
9400 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9403 m68ki_write_8(ea, res);
9407 M68KMAKE_OP(sbcd, 8, mm, ay7)
9409 uint src = OPER_A7_PD_8();
9410 uint ea = EA_AX_PD_8();
9411 uint dst = m68ki_read_8(ea);
9412 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9414 FLAG_V = ~res; /* Undefined V behavior */
9418 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9419 FLAG_X = FLAG_C = (res > 0x99) << 8;
9423 res = MASK_OUT_ABOVE_8(res);
9425 FLAG_V &= res; /* Undefined V behavior part II */
9426 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9429 m68ki_write_8(ea, res);
9433 M68KMAKE_OP(sbcd, 8, mm, axy7)
9435 uint src = OPER_A7_PD_8();
9436 uint ea = EA_A7_PD_8();
9437 uint dst = m68ki_read_8(ea);
9438 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9440 FLAG_V = ~res; /* Undefined V behavior */
9444 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9445 FLAG_X = FLAG_C = (res > 0x99) << 8;
9449 res = MASK_OUT_ABOVE_8(res);
9451 FLAG_V &= res; /* Undefined V behavior part II */
9452 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9455 m68ki_write_8(ea, res);
9459 M68KMAKE_OP(sbcd, 8, mm, .)
9461 uint src = OPER_AY_PD_8();
9462 uint ea = EA_AX_PD_8();
9463 uint dst = m68ki_read_8(ea);
9464 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9466 FLAG_V = ~res; /* Undefined V behavior */
9470 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9471 FLAG_X = FLAG_C = (res > 0x99) << 8;
9475 res = MASK_OUT_ABOVE_8(res);
9477 FLAG_V &= res; /* Undefined V behavior part II */
9478 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9481 m68ki_write_8(ea, res);
9485 M68KMAKE_OP(st, 8, ., d)
9491 M68KMAKE_OP(st, 8, ., .)
9493 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
9497 M68KMAKE_OP(sf, 8, ., d)
9503 M68KMAKE_OP(sf, 8, ., .)
9505 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
9509 M68KMAKE_OP(scc, 8, ., d)
9514 USE_CYCLES(CYC_SCC_R_TRUE);
9521 M68KMAKE_OP(scc, 8, ., .)
9523 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9527 M68KMAKE_OP(stop, 0, ., .)
9531 uint new_sr = OPER_I_16();
9532 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9533 CPU_STOPPED |= STOP_LEVEL_STOP;
9534 m68ki_set_sr(new_sr);
9535 if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR])
9536 m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR];
9541 m68ki_exception_privilege_violation();
9545 M68KMAKE_OP(sub, 8, er, d)
9548 uint src = MASK_OUT_ABOVE_8(DY);
9549 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9550 uint res = dst - src;
9552 FLAG_N = NFLAG_8(res);
9553 FLAG_X = FLAG_C = CFLAG_8(res);
9554 FLAG_V = VFLAG_SUB_8(src, dst, res);
9555 FLAG_Z = MASK_OUT_ABOVE_8(res);
9557 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9561 M68KMAKE_OP(sub, 8, er, .)
9564 uint src = M68KMAKE_GET_OPER_AY_8;
9565 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9566 uint res = dst - src;
9568 FLAG_N = NFLAG_8(res);
9569 FLAG_X = FLAG_C = CFLAG_8(res);
9570 FLAG_V = VFLAG_SUB_8(src, dst, res);
9571 FLAG_Z = MASK_OUT_ABOVE_8(res);
9573 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9577 M68KMAKE_OP(sub, 16, er, d)
9580 uint src = MASK_OUT_ABOVE_16(DY);
9581 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9582 uint res = dst - src;
9584 FLAG_N = NFLAG_16(res);
9585 FLAG_X = FLAG_C = CFLAG_16(res);
9586 FLAG_V = VFLAG_SUB_16(src, dst, res);
9587 FLAG_Z = MASK_OUT_ABOVE_16(res);
9589 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9593 M68KMAKE_OP(sub, 16, er, a)
9596 uint src = MASK_OUT_ABOVE_16(AY);
9597 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9598 uint res = dst - src;
9600 FLAG_N = NFLAG_16(res);
9601 FLAG_X = FLAG_C = CFLAG_16(res);
9602 FLAG_V = VFLAG_SUB_16(src, dst, res);
9603 FLAG_Z = MASK_OUT_ABOVE_16(res);
9605 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9609 M68KMAKE_OP(sub, 16, er, .)
9612 uint src = M68KMAKE_GET_OPER_AY_16;
9613 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9614 uint res = dst - src;
9616 FLAG_N = NFLAG_16(res);
9617 FLAG_X = FLAG_C = CFLAG_16(res);
9618 FLAG_V = VFLAG_SUB_16(src, dst, res);
9619 FLAG_Z = MASK_OUT_ABOVE_16(res);
9621 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9625 M68KMAKE_OP(sub, 32, er, d)
9630 uint res = dst - src;
9632 FLAG_N = NFLAG_32(res);
9633 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9634 FLAG_V = VFLAG_SUB_32(src, dst, res);
9635 FLAG_Z = MASK_OUT_ABOVE_32(res);
9641 M68KMAKE_OP(sub, 32, er, a)
9646 uint res = dst - src;
9648 FLAG_N = NFLAG_32(res);
9649 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9650 FLAG_V = VFLAG_SUB_32(src, dst, res);
9651 FLAG_Z = MASK_OUT_ABOVE_32(res);
9657 M68KMAKE_OP(sub, 32, er, .)
9660 uint src = M68KMAKE_GET_OPER_AY_32;
9662 uint res = dst - src;
9664 FLAG_N = NFLAG_32(res);
9665 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9666 FLAG_V = VFLAG_SUB_32(src, dst, res);
9667 FLAG_Z = MASK_OUT_ABOVE_32(res);
9673 M68KMAKE_OP(sub, 8, re, .)
9675 uint ea = M68KMAKE_GET_EA_AY_8;
9676 uint src = MASK_OUT_ABOVE_8(DX);
9677 uint dst = m68ki_read_8(ea);
9678 uint res = dst - src;
9680 FLAG_N = NFLAG_8(res);
9681 FLAG_Z = MASK_OUT_ABOVE_8(res);
9682 FLAG_X = FLAG_C = CFLAG_8(res);
9683 FLAG_V = VFLAG_SUB_8(src, dst, res);
9685 m68ki_write_8(ea, FLAG_Z);
9689 M68KMAKE_OP(sub, 16, re, .)
9691 uint ea = M68KMAKE_GET_EA_AY_16;
9692 uint src = MASK_OUT_ABOVE_16(DX);
9693 uint dst = m68ki_read_16(ea);
9694 uint res = dst - src;
9696 FLAG_N = NFLAG_16(res);
9697 FLAG_Z = MASK_OUT_ABOVE_16(res);
9698 FLAG_X = FLAG_C = CFLAG_16(res);
9699 FLAG_V = VFLAG_SUB_16(src, dst, res);
9701 m68ki_write_16(ea, FLAG_Z);
9705 M68KMAKE_OP(sub, 32, re, .)
9707 uint ea = M68KMAKE_GET_EA_AY_32;
9709 uint dst = m68ki_read_32(ea);
9710 uint res = dst - src;
9712 FLAG_N = NFLAG_32(res);
9713 FLAG_Z = MASK_OUT_ABOVE_32(res);
9714 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9715 FLAG_V = VFLAG_SUB_32(src, dst, res);
9717 m68ki_write_32(ea, FLAG_Z);
9721 M68KMAKE_OP(suba, 16, ., d)
9725 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9729 M68KMAKE_OP(suba, 16, ., a)
9733 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9737 M68KMAKE_OP(suba, 16, ., .)
9740 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9742 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9746 M68KMAKE_OP(suba, 32, ., d)
9750 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9754 M68KMAKE_OP(suba, 32, ., a)
9758 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9762 M68KMAKE_OP(suba, 32, ., .)
9764 uint src = M68KMAKE_GET_OPER_AY_32;
9767 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9771 M68KMAKE_OP(subi, 8, ., d)
9774 uint src = OPER_I_8();
9775 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9776 uint res = dst - src;
9778 FLAG_N = NFLAG_8(res);
9779 FLAG_Z = MASK_OUT_ABOVE_8(res);
9780 FLAG_X = FLAG_C = CFLAG_8(res);
9781 FLAG_V = VFLAG_SUB_8(src, dst, res);
9783 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9787 M68KMAKE_OP(subi, 8, ., .)
9789 uint src = OPER_I_8();
9790 uint ea = M68KMAKE_GET_EA_AY_8;
9791 uint dst = m68ki_read_8(ea);
9792 uint res = dst - src;
9794 FLAG_N = NFLAG_8(res);
9795 FLAG_Z = MASK_OUT_ABOVE_8(res);
9796 FLAG_X = FLAG_C = CFLAG_8(res);
9797 FLAG_V = VFLAG_SUB_8(src, dst, res);
9799 m68ki_write_8(ea, FLAG_Z);
9803 M68KMAKE_OP(subi, 16, ., d)
9806 uint src = OPER_I_16();
9807 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9808 uint res = dst - src;
9810 FLAG_N = NFLAG_16(res);
9811 FLAG_Z = MASK_OUT_ABOVE_16(res);
9812 FLAG_X = FLAG_C = CFLAG_16(res);
9813 FLAG_V = VFLAG_SUB_16(src, dst, res);
9815 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9819 M68KMAKE_OP(subi, 16, ., .)
9821 uint src = OPER_I_16();
9822 uint ea = M68KMAKE_GET_EA_AY_16;
9823 uint dst = m68ki_read_16(ea);
9824 uint res = dst - src;
9826 FLAG_N = NFLAG_16(res);
9827 FLAG_Z = MASK_OUT_ABOVE_16(res);
9828 FLAG_X = FLAG_C = CFLAG_16(res);
9829 FLAG_V = VFLAG_SUB_16(src, dst, res);
9831 m68ki_write_16(ea, FLAG_Z);
9835 M68KMAKE_OP(subi, 32, ., d)
9838 uint src = OPER_I_32();
9840 uint res = dst - src;
9842 FLAG_N = NFLAG_32(res);
9843 FLAG_Z = MASK_OUT_ABOVE_32(res);
9844 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9845 FLAG_V = VFLAG_SUB_32(src, dst, res);
9851 M68KMAKE_OP(subi, 32, ., .)
9853 uint src = OPER_I_32();
9854 uint ea = M68KMAKE_GET_EA_AY_32;
9855 uint dst = m68ki_read_32(ea);
9856 uint res = dst - src;
9858 FLAG_N = NFLAG_32(res);
9859 FLAG_Z = MASK_OUT_ABOVE_32(res);
9860 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9861 FLAG_V = VFLAG_SUB_32(src, dst, res);
9863 m68ki_write_32(ea, FLAG_Z);
9867 M68KMAKE_OP(subq, 8, ., d)
9870 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9871 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9872 uint res = dst - src;
9874 FLAG_N = NFLAG_8(res);
9875 FLAG_Z = MASK_OUT_ABOVE_8(res);
9876 FLAG_X = FLAG_C = CFLAG_8(res);
9877 FLAG_V = VFLAG_SUB_8(src, dst, res);
9879 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9883 M68KMAKE_OP(subq, 8, ., .)
9885 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9886 uint ea = M68KMAKE_GET_EA_AY_8;
9887 uint dst = m68ki_read_8(ea);
9888 uint res = dst - src;
9890 FLAG_N = NFLAG_8(res);
9891 FLAG_Z = MASK_OUT_ABOVE_8(res);
9892 FLAG_X = FLAG_C = CFLAG_8(res);
9893 FLAG_V = VFLAG_SUB_8(src, dst, res);
9895 m68ki_write_8(ea, FLAG_Z);
9899 M68KMAKE_OP(subq, 16, ., d)
9902 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9903 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9904 uint res = dst - src;
9906 FLAG_N = NFLAG_16(res);
9907 FLAG_Z = MASK_OUT_ABOVE_16(res);
9908 FLAG_X = FLAG_C = CFLAG_16(res);
9909 FLAG_V = VFLAG_SUB_16(src, dst, res);
9911 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9915 M68KMAKE_OP(subq, 16, ., a)
9919 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9923 M68KMAKE_OP(subq, 16, ., .)
9925 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9926 uint ea = M68KMAKE_GET_EA_AY_16;
9927 uint dst = m68ki_read_16(ea);
9928 uint res = dst - src;
9930 FLAG_N = NFLAG_16(res);
9931 FLAG_Z = MASK_OUT_ABOVE_16(res);
9932 FLAG_X = FLAG_C = CFLAG_16(res);
9933 FLAG_V = VFLAG_SUB_16(src, dst, res);
9935 m68ki_write_16(ea, FLAG_Z);
9939 M68KMAKE_OP(subq, 32, ., d)
9942 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9944 uint res = dst - src;
9946 FLAG_N = NFLAG_32(res);
9947 FLAG_Z = MASK_OUT_ABOVE_32(res);
9948 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9949 FLAG_V = VFLAG_SUB_32(src, dst, res);
9955 M68KMAKE_OP(subq, 32, ., a)
9959 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9963 M68KMAKE_OP(subq, 32, ., .)
9965 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9966 uint ea = M68KMAKE_GET_EA_AY_32;
9967 uint dst = m68ki_read_32(ea);
9968 uint res = dst - src;
9970 FLAG_N = NFLAG_32(res);
9971 FLAG_Z = MASK_OUT_ABOVE_32(res);
9972 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9973 FLAG_V = VFLAG_SUB_32(src, dst, res);
9975 m68ki_write_32(ea, FLAG_Z);
9979 M68KMAKE_OP(subx, 8, rr, .)
9982 uint src = MASK_OUT_ABOVE_8(DY);
9983 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9984 uint res = dst - src - XFLAG_AS_1();
9986 FLAG_N = NFLAG_8(res);
9987 FLAG_X = FLAG_C = CFLAG_8(res);
9988 FLAG_V = VFLAG_SUB_8(src, dst, res);
9990 res = MASK_OUT_ABOVE_8(res);
9993 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9997 M68KMAKE_OP(subx, 16, rr, .)
10000 uint src = MASK_OUT_ABOVE_16(DY);
10001 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10002 uint res = dst - src - XFLAG_AS_1();
10004 FLAG_N = NFLAG_16(res);
10005 FLAG_X = FLAG_C = CFLAG_16(res);
10006 FLAG_V = VFLAG_SUB_16(src, dst, res);
10008 res = MASK_OUT_ABOVE_16(res);
10011 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10015 M68KMAKE_OP(subx, 32, rr, .)
10020 uint res = dst - src - XFLAG_AS_1();
10022 FLAG_N = NFLAG_32(res);
10023 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10024 FLAG_V = VFLAG_SUB_32(src, dst, res);
10026 res = MASK_OUT_ABOVE_32(res);
10033 M68KMAKE_OP(subx, 8, mm, ax7)
10035 uint src = OPER_AY_PD_8();
10036 uint ea = EA_A7_PD_8();
10037 uint dst = m68ki_read_8(ea);
10038 uint res = dst - src - XFLAG_AS_1();
10040 FLAG_N = NFLAG_8(res);
10041 FLAG_X = FLAG_C = CFLAG_8(res);
10042 FLAG_V = VFLAG_SUB_8(src, dst, res);
10044 res = MASK_OUT_ABOVE_8(res);
10047 m68ki_write_8(ea, res);
10051 M68KMAKE_OP(subx, 8, mm, ay7)
10053 uint src = OPER_A7_PD_8();
10054 uint ea = EA_AX_PD_8();
10055 uint dst = m68ki_read_8(ea);
10056 uint res = dst - src - XFLAG_AS_1();
10058 FLAG_N = NFLAG_8(res);
10059 FLAG_X = FLAG_C = CFLAG_8(res);
10060 FLAG_V = VFLAG_SUB_8(src, dst, res);
10062 res = MASK_OUT_ABOVE_8(res);
10065 m68ki_write_8(ea, res);
10069 M68KMAKE_OP(subx, 8, mm, axy7)
10071 uint src = OPER_A7_PD_8();
10072 uint ea = EA_A7_PD_8();
10073 uint dst = m68ki_read_8(ea);
10074 uint res = dst - src - XFLAG_AS_1();
10076 FLAG_N = NFLAG_8(res);
10077 FLAG_X = FLAG_C = CFLAG_8(res);
10078 FLAG_V = VFLAG_SUB_8(src, dst, res);
10080 res = MASK_OUT_ABOVE_8(res);
10083 m68ki_write_8(ea, res);
10087 M68KMAKE_OP(subx, 8, mm, .)
10089 uint src = OPER_AY_PD_8();
10090 uint ea = EA_AX_PD_8();
10091 uint dst = m68ki_read_8(ea);
10092 uint res = dst - src - XFLAG_AS_1();
10094 FLAG_N = NFLAG_8(res);
10095 FLAG_X = FLAG_C = CFLAG_8(res);
10096 FLAG_V = VFLAG_SUB_8(src, dst, res);
10098 res = MASK_OUT_ABOVE_8(res);
10101 m68ki_write_8(ea, res);
10105 M68KMAKE_OP(subx, 16, mm, .)
10107 uint src = OPER_AY_PD_16();
10108 uint ea = EA_AX_PD_16();
10109 uint dst = m68ki_read_16(ea);
10110 uint res = dst - src - XFLAG_AS_1();
10112 FLAG_N = NFLAG_16(res);
10113 FLAG_X = FLAG_C = CFLAG_16(res);
10114 FLAG_V = VFLAG_SUB_16(src, dst, res);
10116 res = MASK_OUT_ABOVE_16(res);
10119 m68ki_write_16(ea, res);
10123 M68KMAKE_OP(subx, 32, mm, .)
10125 uint src = OPER_AY_PD_32();
10126 uint ea = EA_AX_PD_32();
10127 uint dst = m68ki_read_32(ea);
10128 uint res = dst - src - XFLAG_AS_1();
10130 FLAG_N = NFLAG_32(res);
10131 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10132 FLAG_V = VFLAG_SUB_32(src, dst, res);
10134 res = MASK_OUT_ABOVE_32(res);
10137 m68ki_write_32(ea, res);
10141 M68KMAKE_OP(swap, 32, ., .)
10145 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10146 *r_dst = (*r_dst>>16) | FLAG_Z;
10149 FLAG_N = NFLAG_32(*r_dst);
10150 FLAG_C = CFLAG_CLEAR;
10151 FLAG_V = VFLAG_CLEAR;
10155 M68KMAKE_OP(tas, 8, ., d)
10159 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10160 FLAG_N = NFLAG_8(*r_dst);
10161 FLAG_V = VFLAG_CLEAR;
10162 FLAG_C = CFLAG_CLEAR;
10167 M68KMAKE_OP(tas, 8, ., .)
10169 uint ea = M68KMAKE_GET_EA_AY_8;
10170 uint dst = m68ki_read_8(ea);
10171 uint allow_writeback;
10174 FLAG_N = NFLAG_8(dst);
10175 FLAG_V = VFLAG_CLEAR;
10176 FLAG_C = CFLAG_CLEAR;
10178 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10179 disabled in order to function properly. Some Amiga software may also rely
10180 on this, but only when accessing specific addresses so additional functionality
10182 allow_writeback = m68ki_tas_callback();
10184 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
10188 M68KMAKE_OP(trap, 0, ., .)
10190 /* Trap#n stacks exception frame type 0 */
10191 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10195 M68KMAKE_OP(trapt, 0, ., .)
10197 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10199 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10202 m68ki_exception_illegal();
10206 M68KMAKE_OP(trapt, 16, ., .)
10208 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10210 REG_PC += 2; // JFF else stackframe & return addresses are incorrect
10211 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10214 m68ki_exception_illegal();
10218 M68KMAKE_OP(trapt, 32, ., .)
10220 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10222 REG_PC += 4; // JFF else stackframe & return addresses are incorrect
10223 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10226 m68ki_exception_illegal();
10230 M68KMAKE_OP(trapf, 0, ., .)
10232 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10236 m68ki_exception_illegal();
10240 M68KMAKE_OP(trapf, 16, ., .)
10242 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10247 m68ki_exception_illegal();
10251 M68KMAKE_OP(trapf, 32, ., .)
10253 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10258 m68ki_exception_illegal();
10262 M68KMAKE_OP(trapcc, 0, ., .)
10264 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10267 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10270 m68ki_exception_illegal();
10274 M68KMAKE_OP(trapcc, 16, ., .)
10276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10278 REG_PC += 2; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10281 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10287 m68ki_exception_illegal();
10291 M68KMAKE_OP(trapcc, 32, ., .)
10293 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10295 REG_PC += 4; /* JFF increase before or 1) stackframe is incorrect 2) RTE address is wrong if trap is taken */
10298 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10303 m68ki_exception_illegal();
10307 M68KMAKE_OP(trapv, 0, ., .)
10313 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10317 M68KMAKE_OP(tst, 8, ., d)
10319 uint res = MASK_OUT_ABOVE_8(DY);
10321 FLAG_N = NFLAG_8(res);
10323 FLAG_V = VFLAG_CLEAR;
10324 FLAG_C = CFLAG_CLEAR;
10328 M68KMAKE_OP(tst, 8, ., .)
10330 uint res = M68KMAKE_GET_OPER_AY_8;
10332 FLAG_N = NFLAG_8(res);
10334 FLAG_V = VFLAG_CLEAR;
10335 FLAG_C = CFLAG_CLEAR;
10339 M68KMAKE_OP(tst, 8, ., pcdi)
10341 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10343 uint res = OPER_PCDI_8();
10345 FLAG_N = NFLAG_8(res);
10347 FLAG_V = VFLAG_CLEAR;
10348 FLAG_C = CFLAG_CLEAR;
10351 m68ki_exception_illegal();
10355 M68KMAKE_OP(tst, 8, ., pcix)
10357 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10359 uint res = OPER_PCIX_8();
10361 FLAG_N = NFLAG_8(res);
10363 FLAG_V = VFLAG_CLEAR;
10364 FLAG_C = CFLAG_CLEAR;
10367 m68ki_exception_illegal();
10371 M68KMAKE_OP(tst, 8, ., i)
10373 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10375 uint res = OPER_I_8();
10377 FLAG_N = NFLAG_8(res);
10379 FLAG_V = VFLAG_CLEAR;
10380 FLAG_C = CFLAG_CLEAR;
10383 m68ki_exception_illegal();
10387 M68KMAKE_OP(tst, 16, ., d)
10389 uint res = MASK_OUT_ABOVE_16(DY);
10391 FLAG_N = NFLAG_16(res);
10393 FLAG_V = VFLAG_CLEAR;
10394 FLAG_C = CFLAG_CLEAR;
10398 M68KMAKE_OP(tst, 16, ., a)
10400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10402 uint res = MAKE_INT_16(AY);
10404 FLAG_N = NFLAG_16(res);
10406 FLAG_V = VFLAG_CLEAR;
10407 FLAG_C = CFLAG_CLEAR;
10410 m68ki_exception_illegal();
10414 M68KMAKE_OP(tst, 16, ., .)
10416 uint res = M68KMAKE_GET_OPER_AY_16;
10418 FLAG_N = NFLAG_16(res);
10420 FLAG_V = VFLAG_CLEAR;
10421 FLAG_C = CFLAG_CLEAR;
10425 M68KMAKE_OP(tst, 16, ., pcdi)
10427 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10429 uint res = OPER_PCDI_16();
10431 FLAG_N = NFLAG_16(res);
10433 FLAG_V = VFLAG_CLEAR;
10434 FLAG_C = CFLAG_CLEAR;
10437 m68ki_exception_illegal();
10441 M68KMAKE_OP(tst, 16, ., pcix)
10443 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10445 uint res = OPER_PCIX_16();
10447 FLAG_N = NFLAG_16(res);
10449 FLAG_V = VFLAG_CLEAR;
10450 FLAG_C = CFLAG_CLEAR;
10453 m68ki_exception_illegal();
10457 M68KMAKE_OP(tst, 16, ., i)
10459 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10461 uint res = OPER_I_16();
10463 FLAG_N = NFLAG_16(res);
10465 FLAG_V = VFLAG_CLEAR;
10466 FLAG_C = CFLAG_CLEAR;
10469 m68ki_exception_illegal();
10473 M68KMAKE_OP(tst, 32, ., d)
10477 FLAG_N = NFLAG_32(res);
10479 FLAG_V = VFLAG_CLEAR;
10480 FLAG_C = CFLAG_CLEAR;
10484 M68KMAKE_OP(tst, 32, ., a)
10486 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10490 FLAG_N = NFLAG_32(res);
10492 FLAG_V = VFLAG_CLEAR;
10493 FLAG_C = CFLAG_CLEAR;
10496 m68ki_exception_illegal();
10500 M68KMAKE_OP(tst, 32, ., .)
10502 uint res = M68KMAKE_GET_OPER_AY_32;
10504 FLAG_N = NFLAG_32(res);
10506 FLAG_V = VFLAG_CLEAR;
10507 FLAG_C = CFLAG_CLEAR;
10511 M68KMAKE_OP(tst, 32, ., pcdi)
10513 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10515 uint res = OPER_PCDI_32();
10517 FLAG_N = NFLAG_32(res);
10519 FLAG_V = VFLAG_CLEAR;
10520 FLAG_C = CFLAG_CLEAR;
10523 m68ki_exception_illegal();
10527 M68KMAKE_OP(tst, 32, ., pcix)
10529 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10531 uint res = OPER_PCIX_32();
10533 FLAG_N = NFLAG_32(res);
10535 FLAG_V = VFLAG_CLEAR;
10536 FLAG_C = CFLAG_CLEAR;
10539 m68ki_exception_illegal();
10543 M68KMAKE_OP(tst, 32, ., i)
10545 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10547 uint res = OPER_I_32();
10549 FLAG_N = NFLAG_32(res);
10551 FLAG_V = VFLAG_CLEAR;
10552 FLAG_C = CFLAG_CLEAR;
10555 m68ki_exception_illegal();
10559 M68KMAKE_OP(unlk, 32, ., a7)
10561 REG_A[7] = m68ki_read_32(REG_A[7]);
10565 M68KMAKE_OP(unlk, 32, ., .)
10570 *r_dst = m68ki_pull_32();
10574 M68KMAKE_OP(unpk, 16, rr, .)
10576 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10578 /* Note: DX and DY are reversed in Motorola's docs */
10582 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
10585 m68ki_exception_illegal();
10589 M68KMAKE_OP(unpk, 16, mm, ax7)
10591 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10593 /* Note: AX and AY are reversed in Motorola's docs */
10594 uint src = OPER_AY_PD_8();
10597 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10598 ea_dst = EA_A7_PD_8();
10599 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10600 ea_dst = EA_A7_PD_8();
10601 m68ki_write_8(ea_dst, src & 0xff);
10604 m68ki_exception_illegal();
10608 M68KMAKE_OP(unpk, 16, mm, ay7)
10610 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10612 /* Note: AX and AY are reversed in Motorola's docs */
10613 uint src = OPER_A7_PD_8();
10616 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10617 ea_dst = EA_AX_PD_8();
10618 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10619 ea_dst = EA_AX_PD_8();
10620 m68ki_write_8(ea_dst, src & 0xff);
10623 m68ki_exception_illegal();
10627 M68KMAKE_OP(unpk, 16, mm, axy7)
10629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10631 uint src = OPER_A7_PD_8();
10634 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10635 ea_dst = EA_A7_PD_8();
10636 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10637 ea_dst = EA_A7_PD_8();
10638 m68ki_write_8(ea_dst, src & 0xff);
10641 m68ki_exception_illegal();
10645 M68KMAKE_OP(unpk, 16, mm, .)
10647 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10649 /* Note: AX and AY are reversed in Motorola's docs */
10650 uint src = OPER_AY_PD_8();
10653 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10654 ea_dst = EA_AX_PD_8();
10655 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10656 ea_dst = EA_AX_PD_8();
10657 m68ki_write_8(ea_dst, src & 0xff);
10660 m68ki_exception_illegal();
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projects / pistorm / blob