2 Copyright 2005-2011 Intel Corporation. All Rights Reserved.
4 This file is part of Threading Building Blocks.
6 Threading Building Blocks is free software; you can redistribute it
7 and/or modify it under the terms of the GNU General Public License
8 version 2 as published by the Free Software Foundation.
10 Threading Building Blocks is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
12 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with Threading Building Blocks; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 As a special exception, you may use this file as part of a free software
20 library without restriction. Specifically, if other files instantiate
21 templates or use macros or inline functions from this file, or you compile
22 this file and link it with other files to produce an executable, this
23 file does not by itself cause the resulting executable to be covered by
24 the GNU General Public License. This exception does not however
25 invalidate any other reasons why the executable file might be covered by
26 the GNU General Public License.
29 #ifndef __TBB_machine_H
30 #error Do not include this file directly; include tbb_machine.h instead
36 #define __TBB_WORDSIZE 8
37 #define __TBB_BIG_ENDIAN 0
39 #define __TBB_release_consistency_helper() __asm__ __volatile__("": : :"memory")
41 // __TBB_full_memory_fence can be predefined
42 #ifndef __TBB_full_memory_fence
43 #define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
46 #define __MACHINE_DECL_ATOMICS(S,T,X) \
47 static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
51 __asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
52 : "=a"(result), "=m"(*(volatile T*)ptr) \
53 : "q"(value), "0"(comparand), "m"(*(volatile T*)ptr) \
58 static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
61 __asm__ __volatile__("lock\nxadd" X " %0,%1" \
62 : "=r"(result),"=m"(*(volatile T*)ptr) \
63 : "0"(addend), "m"(*(volatile T*)ptr) \
68 static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
71 __asm__ __volatile__("lock\nxchg" X " %0,%1" \
72 : "=r"(result),"=m"(*(volatile T*)ptr) \
73 : "0"(value), "m"(*(volatile T*)ptr) \
78 __MACHINE_DECL_ATOMICS(1,int8_t,"")
79 __MACHINE_DECL_ATOMICS(2,int16_t,"")
80 __MACHINE_DECL_ATOMICS(4,int32_t,"")
81 __MACHINE_DECL_ATOMICS(8,int64_t,"q")
83 static inline int64_t __TBB_machine_lg( uint64_t x ) {
85 __asm__ ("bsr %1,%0" : "=r"(j) : "r"(x));
89 static inline void __TBB_machine_or( volatile void *ptr, uint64_t addend ) {
90 __asm__ __volatile__("lock\norq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(addend), "m"(*(volatile uint64_t*)ptr) : "memory");
93 static inline void __TBB_machine_and( volatile void *ptr, uint64_t addend ) {
94 __asm__ __volatile__("lock\nandq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(addend), "m"(*(volatile uint64_t*)ptr) : "memory");
97 // Machine specific atomic operations
99 #define __TBB_CompareAndSwap1(P,V,C) __TBB_machine_cmpswp1(P,V,C)
100 #define __TBB_CompareAndSwap2(P,V,C) __TBB_machine_cmpswp2(P,V,C)
101 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
102 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
103 #define __TBB_CompareAndSwapW(P,V,C) __TBB_machine_cmpswp8(P,V,C)
105 #define __TBB_FetchAndAdd1(P,V) __TBB_machine_fetchadd1(P,V)
106 #define __TBB_FetchAndAdd2(P,V) __TBB_machine_fetchadd2(P,V)
107 #define __TBB_FetchAndAdd4(P,V) __TBB_machine_fetchadd4(P,V)
108 #define __TBB_FetchAndAdd8(P,V) __TBB_machine_fetchadd8(P,V)
109 #define __TBB_FetchAndAddW(P,V) __TBB_machine_fetchadd8(P,V)
111 #define __TBB_FetchAndStore1(P,V) __TBB_machine_fetchstore1(P,V)
112 #define __TBB_FetchAndStore2(P,V) __TBB_machine_fetchstore2(P,V)
113 #define __TBB_FetchAndStore4(P,V) __TBB_machine_fetchstore4(P,V)
114 #define __TBB_FetchAndStore8(P,V) __TBB_machine_fetchstore8(P,V)
115 #define __TBB_FetchAndStoreW(P,V) __TBB_machine_fetchstore8(P,V)
120 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
121 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
123 // Definition of other functions
125 static inline void __TBB_machine_pause( int32_t delay ) {
126 for (int32_t i = 0; i < delay; i++) {
127 __asm__ __volatile__("pause;");
131 #define __TBB_Pause(V) __TBB_machine_pause(V)
133 #define __TBB_Log2(V) __TBB_machine_lg(V)
135 // Special atomic functions
136 #define __TBB_FetchAndAddWrelease(P,V) __TBB_FetchAndAddW(P,V)
137 #define __TBB_FetchAndIncrementWacquire(P) __TBB_FetchAndAddW(P,1)
138 #define __TBB_FetchAndDecrementWrelease(P) __TBB_FetchAndAddW(P,-1)
140 // Use generic definitions from tbb_machine.h
141 #undef __TBB_TryLockByte
142 #undef __TBB_LockByte
144 // API to retrieve/update FPU control setting
145 #ifndef __TBB_CPU_CTL_ENV_PRESENT
146 #define __TBB_CPU_CTL_ENV_PRESENT 1
148 struct __TBB_cpu_ctl_env_t {
153 inline void __TBB_get_cpu_ctl_env ( __TBB_cpu_ctl_env_t* ctl ) {
154 __asm__ __volatile__ (
157 : "=m"(ctl->mxcsr), "=m"(ctl->x87cw)
160 inline void __TBB_set_cpu_ctl_env ( const __TBB_cpu_ctl_env_t* ctl ) {
161 __asm__ __volatile__ (
164 : : "m"(ctl->mxcsr), "m"(ctl->x87cw)