2 Copyright 2005-2011 Intel Corporation. All Rights Reserved.
4 This file is part of Threading Building Blocks.
6 Threading Building Blocks is free software; you can redistribute it
7 and/or modify it under the terms of the GNU General Public License
8 version 2 as published by the Free Software Foundation.
10 Threading Building Blocks is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
12 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with Threading Building Blocks; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 As a special exception, you may use this file as part of a free software
20 library without restriction. Specifically, if other files instantiate
21 templates or use macros or inline functions from this file, or you compile
22 this file and link it with other files to produce an executable, this
23 file does not by itself cause the resulting executable to be covered by
24 the GNU General Public License. This exception does not however
25 invalidate any other reasons why the executable file might be covered by
26 the GNU General Public License.
30 #if !defined(__TBB_machine_H) || defined(__TBB_machine_sunos_sparc_H)
31 #error Do not include this file directly; include tbb_machine.h instead
34 #define __TBB_machine_sunos_sparc_H
39 #define __TBB_WORDSIZE 8
40 #define __TBB_BIG_ENDIAN 1
42 /** To those working on SPARC hardware. Consider relaxing acquire and release
43 consistency helpers to no-op (as this port covers TSO mode only). **/
44 #define __TBB_compiler_fence() __asm__ __volatile__ ("": : :"memory")
45 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
46 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
47 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
48 #define __TBB_full_memory_fence() __asm__ __volatile__("membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad": : : "memory")
50 //--------------------------------------------------
52 //--------------------------------------------------
55 * Atomic CAS for 32 bit values, if *ptr==comparand, then *ptr=value, returns *ptr
56 * @param ptr pointer to value in memory to be swapped with value if *ptr==comparand
57 * @param value value to assign *ptr to if *ptr==comparand
58 * @param comparand value to compare with *ptr
59 ( @return value originally in memory at ptr, regardless of success
61 static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand ){
65 : "=m"(*(int32_t *)ptr), "=r"(result)
66 : "m"(*(int32_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
72 * Atomic CAS for 64 bit values, if *ptr==comparand, then *ptr=value, returns *ptr
73 * @param ptr pointer to value in memory to be swapped with value if *ptr==comparand
74 * @param value value to assign *ptr to if *ptr==comparand
75 * @param comparand value to compare with *ptr
76 ( @return value originally in memory at ptr, regardless of success
78 static inline int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand ){
82 : "=m"(*(int64_t *)ptr), "=r"(result)
83 : "m"(*(int64_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
88 //---------------------------------------------------
90 //---------------------------------------------------
93 * Atomic fetch and add for 32 bit values, in this case implemented by continuously checking success of atomicity
94 * @param ptr pointer to value to add addend to
95 * @param addened value to add to *ptr
96 * @return value at ptr before addened was added
98 static inline int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend){
100 __asm__ __volatile__ (
101 "0:\t add\t %3, %4, %0\n" // do addition
102 "\t cas\t [%2], %3, %0\n" // cas to store result in memory
103 "\t cmp\t %3, %0\n" // check if value from memory is original
104 "\t bne,a,pn\t %%icc, 0b\n" // if not try again
105 "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
106 : "=&r"(result), "=m"(*(int32_t *)ptr)
107 : "r"(ptr), "r"(*(int32_t *)ptr), "r"(addend), "m"(*(int32_t *)ptr)
113 * Atomic fetch and add for 64 bit values, in this case implemented by continuously checking success of atomicity
114 * @param ptr pointer to value to add addend to
115 * @param addened value to add to *ptr
116 * @return value at ptr before addened was added
118 static inline int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend){
120 __asm__ __volatile__ (
121 "0:\t add\t %3, %4, %0\n" // do addition
122 "\t casx\t [%2], %3, %0\n" // cas to store result in memory
123 "\t cmp\t %3, %0\n" // check if value from memory is original
124 "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
125 "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
126 : "=&r"(result), "=m"(*(int64_t *)ptr)
127 : "r"(ptr), "r"(*(int64_t *)ptr), "r"(addend), "m"(*(int64_t *)ptr)
132 //--------------------------------------------------------
133 // Logarithm (base two, integer)
134 //--------------------------------------------------------
136 static inline int64_t __TBB_machine_lg( uint64_t x ) {
146 __asm__ ("popc %1, %0" : "=r"(count) : "r"(x) );
150 //--------------------------------------------------------
152 static inline void __TBB_machine_or( volatile void *ptr, uint64_t addend ) {
153 __asm__ __volatile__ (
154 "0:\t or\t %2, %3, %%g1\n" // do addition
155 "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
156 "\t cmp\t %2, %%g1\n" // check if value from memory is original
157 "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
158 "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
159 : "=m"(*(int64_t *)ptr)
160 : "r"(ptr), "r"(*(int64_t *)ptr), "r"(addend), "m"(*(int64_t *)ptr)
161 : "ccr", "g1", "memory");
164 static inline void __TBB_machine_and( volatile void *ptr, uint64_t addend ) {
165 __asm__ __volatile__ (
166 "0:\t and\t %2, %3, %%g1\n" // do addition
167 "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
168 "\t cmp\t %2, %%g1\n" // check if value from memory is original
169 "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
170 "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
171 : "=m"(*(int64_t *)ptr)
172 : "r"(ptr), "r"(*(int64_t *)ptr), "r"(addend), "m"(*(int64_t *)ptr)
173 : "ccr", "g1", "memory");
177 static inline void __TBB_machine_pause( int32_t delay ) {
178 // do nothing, inlined, doesnt matter
181 // put 0xff in memory location, return memory value,
182 // generic trylockbyte puts 0x01, however this is fine
183 // because all that matters is that 0 is unlocked
184 static inline bool __TBB_machine_trylockbyte(unsigned char &flag){
185 unsigned char result;
186 __asm__ __volatile__ (
187 "ldstub\t [%2], %0\n"
188 : "=r"(result), "=m"(flag)
189 : "r"(&flag), "m"(flag)
194 #define __TBB_USE_GENERIC_PART_WORD_CAS 1
195 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
196 #define __TBB_USE_GENERIC_FETCH_STORE 1
197 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
198 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
200 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
201 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
203 // Definition of other functions
204 #define __TBB_Pause(V) __TBB_machine_pause(V)
205 #define __TBB_Log2(V) __TBB_machine_lg(V)
207 #define __TBB_TryLockByte(P) __TBB_machine_trylockbyte(P)