+#endif /* __TBB_UnknownArchitecture || __TBB_WORDSIZE==4 */
+
+#if __TBB_UnknownArchitecture
+
+#ifndef __TBB_WORDSIZE
+#define __TBB_WORDSIZE 4
+#endif
+
+#define __TBB_BIG_ENDIAN __BIG_ENDIAN__
+
+/** As this generic implementation has absolutely no information about underlying
+ hardware, its performance most likely will be sub-optimal because of full memory
+ fence usages where a more lightweight synchronization means (or none at all)
+ could suffice. Thus if you use this header to enable TBB on a new platform,
+ consider forking it and relaxing below helpers as appropriate. **/
+#define __TBB_control_consistency_helper() OSMemoryBarrier()
+#define __TBB_acquire_consistency_helper() OSMemoryBarrier()
+#define __TBB_release_consistency_helper() OSMemoryBarrier()
+#define __TBB_full_memory_fence() OSMemoryBarrier()
+
+static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand)
+{
+ __TBB_ASSERT( !((uintptr_t)ptr&0x3), "address not properly aligned for Mac OS atomics");
+ int32_t* address = (int32_t*)ptr;
+ while( !OSAtomicCompareAndSwap32Barrier(comparand, value, address) ){
+ int32_t snapshot = *address;
+ if( snapshot!=comparand ) return snapshot;
+ }
+ return comparand;
+}
+
+static inline int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend)