Some more failed PiSCSI 1.3 autoboot ventures

[pistorm] / m68kfpu.c

diff --git a/m68kfpu.c b/m68kfpu.c
index 505c83375e4d8dfbf87d816f1a06d73bf42f1142..68c3f6f1614702554c5ea3ba240faa20d6517581 100644 (file)
--- a/m68kfpu.c
+++ b/m68kfpu.c
@@ -1403,10 +1403,13 @@ static void fpgen_rm_reg(uint16 w2)
                source = REG_FP[src];
        }
 
-
+       // For FD* and FS* prefixes we already converted the source to floatx80
+       // so we can treat these as their parent op.
 
        switch (opmode)
        {
+               case 0x44:              // FDMOVE
+               case 0x40:              // FSMOVE
                case 0x00:              // FMOVE
                {
                        REG_FP[dst] = source;
@@ -1440,7 +1443,10 @@ static void fpgen_rm_reg(uint16 w2)
                        SET_CONDITION_CODES(REG_FP[dst]);  // JFF needs update condition codes
                        break;
                }
+               case 0x45:              // FDSQRT
+               case 0x41:              // FSSQRT
                case 0x04:              // FSQRT
+               case 0x05:              // FSQRT
                {
                        REG_FP[dst] = floatx80_sqrt(source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
@@ -1448,6 +1454,7 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x06:      // FLOGNP1
+               case 0x07:      // FLOGNP1
                {
                        REG_FP[dst] = floatx80_lognp1 (source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
@@ -1469,6 +1476,7 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x0a:      // FATAN
+               case 0x0b:      // FATAN
                {
                        REG_FP[dst] = floatx80_atan(source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
@@ -1518,6 +1526,7 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x12:      // FTENTOX
+               case 0x13:      // FTENTOX
                {
                        REG_FP[dst] = floatx80_tentox(source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
@@ -1539,12 +1548,15 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x16:      // FLOG2
+               case 0x17:      // FLOG2
                {
                        REG_FP[dst] = floatx80_log2(source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
                        USE_CYCLES(604); // for MC68881
                        break;
                }
+               case 0x5C:              // FDABS
+               case 0x58:              // FSABS
                case 0x18:              // FABS
                {
                        REG_FP[dst] = source;
@@ -1560,7 +1572,10 @@ static void fpgen_rm_reg(uint16 w2)
                        USE_CYCLES(64);
                        break;
                }
+               case 0x5e:              // FDNEG
+               case 0x5a:              // FSNEG
                case 0x1a:              // FNEG
+               case 0x1b:              // FNEG
                {
                        REG_FP[dst] = source;
                        REG_FP[dst].high ^= 0x8000;
@@ -1597,7 +1612,8 @@ static void fpgen_rm_reg(uint16 w2)
                        USE_CYCLES(6);
                        break;
                }
-               case 0x60:              // FSDIVS (JFF) (source has already been converted to floatx80)
+               case 0x64:              // FDDIV
+               case 0x60:              // FSDIV
                case 0x20:              // FDIV
                {
                        REG_FP[dst] = floatx80_div(REG_FP[dst], source, &status);
@@ -1618,6 +1634,8 @@ static void fpgen_rm_reg(uint16 w2)
                        USE_CYCLES(43);   // guess
                        break;
                }
+               case 0x66:              // FDADD
+               case 0x62:              // FSADD
                case 0x22:              // FADD
                {
                        REG_FP[dst] = floatx80_add(REG_FP[dst], source, &status);
@@ -1625,7 +1643,8 @@ static void fpgen_rm_reg(uint16 w2)
                        USE_CYCLES(9);
                        break;
                }
-               case 0x63:              // FSMULS (JFF) (source has already been converted to floatx80)
+               case 0x67:              // FDMUL
+               case 0x63:              // FSMUL
                case 0x23:              // FMUL
                {
                        REG_FP[dst] = floatx80_mul(REG_FP[dst], source, &status);
@@ -1665,7 +1684,16 @@ static void fpgen_rm_reg(uint16 w2)
                        USE_CYCLES(11); // ? (value is from FMUL)
                        break;
                }
+               case 0x6c:              // FDSUB
+               case 0x68:              // FSSUB
                case 0x28:              // FSUB
+               case 0x29:              // FSUB
+               case 0x2a:              // FSUB
+               case 0x2b:              // FSUB
+               case 0x2c:              // FSUB
+               case 0x2d:              // FSUB
+               case 0x2e:              // FSUB
+               case 0x2f:              // FSUB
                {
                        REG_FP[dst] = floatx80_sub(REG_FP[dst], source, &status);
                        SET_CONDITION_CODES(REG_FP[dst]);
@@ -1689,6 +1717,9 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x38:              // FCMP
+               case 0x39:              // FCMP
+               case 0x3c:              // FCMP
+               case 0x3d:              // FCMP
                {
                        floatx80 res;
                        res = floatx80_sub(REG_FP[dst], source, &status);
@@ -1697,6 +1728,9 @@ static void fpgen_rm_reg(uint16 w2)
                        break;
                }
                case 0x3a:              // FTST
+               case 0x3b:              // FTST
+               case 0x3e:              // FTST
+               case 0x3f:              // FTST
                {
                        floatx80 res;
                        res = source;