output reg PI_IPL_ZERO, // GPIO1
input [1:0] PI_A, // GPIO[3..2]
input PI_CLK, // GPIO4
- input PI_UNUSED, // GPIO5
+ output reg PI_RESET, // GPIO5
input PI_RD, // GPIO6
input PI_WR, // GPIO7
inout [15:0] PI_D, // GPIO[23..8]
PI_TXN_IN_PROGRESS <= 1'b0;
PI_IPL_ZERO <= 1'b0;
+ PI_RESET <= 1'b0;
+
M68K_FC <= 3'd0;
M68K_RW <= 1'b1;
PI_IPL_ZERO <= ipl == 3'd0;
end
+ always @(posedge c200m) begin
+ PI_RESET <= reset_out ? 1'b1 : M68K_RESET_n;
+ end
+
reg [3:0] e_counter = 4'd0;
always @(negedge c7m) begin