- ldr w11, [x10], #4 // read 2x16-bit coeffs (X, Y) at (filter[j], filter[j+1])
- zip1 v16.8H, v5.8H, v6.8H // A,I,B,J,C,K,D,L
- zip2 v17.8H, v5.8H, v6.8H // E,M,F,N,F,O,H,P
- dup v7.4S, w11 // X,Y,X,Y,X,Y,X,Y
- smull v18.4S, v16.4H, v7.4H // A.X I.Y B.X J.Y
- smull v20.4S, v17.4H, v7.4H // E.X M.Y F.X N.Y
- smull2 v19.4S, v16.8H, v7.8H // C.X K.Y D.X L.Y
- smull2 v21.4S, v17.8H, v7.8H // G.X O.Y H.X P.Y
- addp v16.4S, v18.4S, v19.4S // A.X+I.Y B.X+J.Y C.X+K.Y D.X+L.Y
- addp v17.4S, v20.4S, v21.4S // E.X+M.Y F.X+N.Y F.X+O.Y H.X+P.Y
- add v3.4S, v3.4S, v16.4S // update val accumulator for part 1
- add v4.4S, v4.4S, v17.4S // update val accumulator for part 2
+ ld1r {v7.8H}, [x10], #2 // read 1x16-bit coeff X at filter[j ] and duplicate across lanes
+ ld1r {v8.8H}, [x10], #2 // read 1x16-bit coeff Y at filter[j+1] and duplicate across lanes
+ smlal v3.4S, v5.4H, v7.4H // val0 += {A,B,C,D} * X
+ smlal2 v4.4S, v5.8H, v7.8H // val1 += {E,F,G,H} * X
+ smlal v3.4S, v6.4H, v8.4H // val0 += {I,J,K,L} * Y
+ smlal2 v4.4S, v6.8H, v8.8H // val1 += {M,N,O,P} * Y