*.o
+*.img
+*.hdf
+*.rom
+*.dll
+*.bin
+*.exe
+*.stackdump
+!/platforms/amiga/piscsi/*.rom
/m68kmake
/m68kmake.exe
/m68kops.c
/m68kops.h
+/emulator
# this supports ECP5 Evaluation Board
reset_config none
-interface bcm2835gpio
-
-
+adapter driver bcm2835gpio
#bcm2835gpio_peripheral_base 0x20000000
bcm2835gpio_peripheral_base 0x3F000000
-
# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
# These depend on system clock, calibrated for stock 700MHz
# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
#bcm2835gpio_speed_coeffs 146203 36
bcm2835gpio_speed_coeffs 194938 48
-
-
#bcm2835gpio_peripheral_base 0x3F000000
#bcm2835gpio_speed_coeffs 194938 48
reset_config none
-adapter_khz 100
+adapter speed 100
# JTAG tck tms tdi tdo
bcm2835gpio_jtag_nums 26 24 27 25
reset_config srst_only srst_open_drain
transport select jtag
-jtag newtap max2 tap -irlen 11 -expected-id 0x020a20dd
+jtag newtap max2 tap -irlen 11 -expected-id 0x020a20dd
init
-svf bitstream.svf -quiet
+svf ./rtl/bitstream.svf -quiet
sleep 200
shutdown
+++ /dev/null
-//
-// Gayle.c
-// Omega
-//
-// Created by Matt Parsons on 06/03/2019.
-// Copyright © 2019 Matt Parsons. All rights reserved.
-//
-
-// Write Byte to Gayle Space 0xda9000 (0x0000c3)
-// Read Byte From Gayle Space 0xda9000
-// Read Byte From Gayle Space 0xdaa000
-
-#include "Gayle.h"
-#include <fcntl.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include "ide.h"
-#include "platforms/amiga/amiga-registers.h"
-
-
-//#define GSTATUS 0xda201c
-//#define GCLOW 0xda2010
-//#define GDH 0xda2018
-
-// Gayle Addresses
-//#define GAYLE_IDE_BASE_A1200 0xDA0000 //8 bit base
-#define GAYLE_IDE_BASE_A1200 0xDA2000 //16bit base
-#define GAYLE_IDE_BASE_A4000 0xDD2020
-
-// Gayle IDE Reads
-#define GERROR 0xda2004 // Error
-#define GSTATUS 0xda201C // Status
-#define GERROR_A4000 GAYLE_IDE_BASE_A4000 + 0x06 // Error
-#define GSTATUS_A4000 GAYLE_IDE_BASE_A4000 + 0x1E // Status
-
-// Gayle IDE Writes
-#define GFEAT 0xda2004 // Write : Feature
-#define GCMD 0xda201c // Write : Command
-#define GFEAT_A4000 GAYLE_IDE_BASE_A4000 + 0x06 // Write : Feature
-#define GCMD_A4000 GAYLE_IDE_BASE_A4000 + 0x1E // Write : Command
-#define GMODEREG0_A4000 0x0DD1020 // D31, PIO modes (00,01,10)
-#define GMODEREG1_A4000 0x0DD1022 // D31, (MSB)
-
-// Gayle IDE RW
-#define GDATA 0xda2000 // Data - 16 bit
-#define GSECTCNT 0xda2008 // SectorCount
-#define GSECTNUM 0xda200c // SectorNumber
-#define GCYLLOW 0xda2010 // CylinderLow
-#define GCYLHIGH 0xda2014 // CylinderHigh
-#define GDEVHEAD 0xda2018 // Device/Head
-#define GCTRL 0xda3018 // Control
-
-#define GDATA_A4000 GAYLE_IDE_BASE_A4000 // Data
-#define GSECTCNT_A4000 GAYLE_IDE_BASE_A4000 + 0x0a // SectorCount
-#define GSECTNUM_A4000 GAYLE_IDE_BASE_A4000 + 0x0e // SectorNumber
-#define GCYLLOW_A4000 GAYLE_IDE_BASE_A4000 + 0x12 // CylinderLow
-#define GCYLHIGH_A4000 GAYLE_IDE_BASE_A4000 + 0x16 // CylinderHigh
-#define GDEVHEAD_A4000 GAYLE_IDE_BASE_A4000 + 0x1a // Device/Head
-#define GCTRL_A4000 GAYLE_IDE_BASE_A4000 + 0x101a // Control
-
-// Gayle Ident
-#define GIDENT 0xDE1000
-
-// Gayle IRQ/CC
-#define GCS 0xDA8000 // Card Control
-#define GIRQ 0xDA9000 // IRQ
-#define GINT 0xDAA000 // Int enable
-#define GCONF 0xDAB000 // Gayle Config
-
-// For A4000 there's no need to populate other areas, just GIRQ
-#define GIRQ_A4000 GAYLE_IDE_BASE_A4000 + 0x1000 // IRQ 0xDD3020
-
-/* DA8000 */
-#define GAYLE_CS_IDE 0x80 /* IDE int status */
-#define GAYLE_CS_CCDET 0x40 /* credit card detect */
-#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
-#define GAYLE_CS_SC 0x20 /* credit card status change */
-#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
-#define GAYLE_CS_DA 0x10 /* digital audio */
-#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
-#define GAYLE_CS_BSY 0x04 /* credit card busy */
-#define GAYLE_CS_IRQ 0x04 /* interrupt request */
-#define GAYLE_CS_DAEN 0x02 /* enable digital audio */
-#define GAYLE_CS_DIS 0x01 /* disable PCMCIA slot */
-
-/* DA9000 */
-#define GAYLE_IRQ_IDE 0x80
-#define GAYLE_IRQ_CCDET 0x40 /* credit card detect */
-#define GAYLE_IRQ_BVD1 0x20 /* battery voltage detect 1 */
-#define GAYLE_IRQ_SC 0x20 /* credit card status change */
-#define GAYLE_IRQ_BVD2 0x10 /* battery voltage detect 2 */
-#define GAYLE_IRQ_DA 0x10 /* digital audio */
-#define GAYLE_IRQ_WR 0x08 /* write enable (1 == enabled) */
-#define GAYLE_IRQ_BSY 0x04 /* credit card busy */
-#define GAYLE_IRQ_IRQ 0x04 /* interrupt request */
-#define GAYLE_IRQ_RESET 0x02 /* reset machine after CCDET change */
-#define GAYLE_IRQ_BERR 0x01 /* generate bus error after CCDET change */
-
-/* DAA000 */
-#define GAYLE_INT_IDE 0x80 /* IDE interrupt enable */
-#define GAYLE_INT_CCDET 0x40 /* credit card detect change enable */
-#define GAYLE_INT_BVD1 0x20 /* battery voltage detect 1 change enable */
-#define GAYLE_INT_SC 0x20 /* credit card status change enable */
-#define GAYLE_INT_BVD2 0x10 /* battery voltage detect 2 change enable */
-#define GAYLE_INT_DA 0x10 /* digital audio change enable */
-#define GAYLE_INT_WR 0x08 /* write enable change enabled */
-#define GAYLE_INT_BSY 0x04 /* credit card busy */
-#define GAYLE_INT_IRQ 0x04 /* credit card interrupt request */
-#define GAYLE_INT_BVD_LEV 0x02 /* BVD int level, 0=lev2,1=lev6 */
-#define GAYLE_INT_BSY_LEV 0x01 /* BSY int level, 0=lev2,1=lev6 */
-
-#define GAYLE_MAX_HARDFILES 8
-
-int counter;
-static uint8_t gayle_irq, gayle_int, gayle_cs, gayle_cs_mask, gayle_cfg;
-static struct ide_controller *ide0;
-int fd;
-
-uint8_t gary_cfg0 = 0x00;
-uint8_t gary_cfg1 = 0x00;
-uint8_t gary_cfg2 = 0x00;
-uint8_t gary_cfg3 = 0x00;
-uint8_t gary_cfg4 = 0x00;
-uint8_t gary_cfg5 = 0x00;
-
-uint8_t gayle_a4k = 0xA0;
-uint16_t gayle_a4k_irq;
-uint8_t ramsey_cfg = 0x08;
-static uint8_t ramsey_id = RAMSEY_REV7;
-
-char *hdd_image_file[GAYLE_MAX_HARDFILES];
-
-void set_hard_drive_image_file_amiga(uint8_t index, char *filename) {
- if (hdd_image_file[index] != NULL)
- free(hdd_image_file[index]);
- hdd_image_file[index] = calloc(1, strlen(filename) + 1);
- strcpy(hdd_image_file[index], filename);
-}
-
-void InitGayle(void) {
- if (!hdd_image_file[0]) {
- hdd_image_file[0] = calloc(1, 64);
- sprintf(hdd_image_file[0], "hd0.img");
- }
-
- ide0 = ide_allocate("cf");
- fd = open(hdd_image_file[0], O_RDWR);
- if (fd == -1) {
- printf("HDD Image %s failed open\n", hdd_image_file[0]);
- } else {
- ide_attach(ide0, 0, fd);
- ide_reset_begin(ide0);
- printf("HDD Image %s attached\n", hdd_image_file[0]);
- }
-}
-
-uint8_t CheckIrq(void) {
- uint8_t irq;
- /* skipping gayle_int check makes A4000 ROMs IDE work at decent speed */
- irq = ide0->drive->intrq;
- return irq;
-}
-
-void writeGayleB(unsigned int address, unsigned int value) {
- if (address == GFEAT || address == GFEAT_A4000) {
- ide_write8(ide0, ide_feature_w, value);
- return;
- }
- if (address == GCMD || address == GCMD_A4000) {
- ide_write8(ide0, ide_command_w, value);
- return;
- }
- if (address == GSECTCNT || address == GSECTCNT_A4000) {
- ide_write8(ide0, ide_sec_count, value);
- return;
- }
- if (address == GSECTNUM || address == GSECTNUM_A4000) {
- ide_write8(ide0, ide_sec_num, value);
- return;
- }
- if (address == GCYLLOW || address == GCYLLOW_A4000) {
- ide_write8(ide0, ide_cyl_low, value);
- return;
- }
- if (address == GCYLHIGH || address == GCYLHIGH_A4000) {
- ide_write8(ide0, ide_cyl_hi, value);
- return;
- }
- if (address == GDEVHEAD || address == GDEVHEAD_A4000) {
- ide_write8(ide0, ide_dev_head, value);
- return;
- }
- if (address == GCTRL || address == GCTRL_A4000) {
- ide_write8(ide0, ide_devctrl_w, value);
- return;
- }
-
- if (address == GIDENT) {
- counter = 0;
- printf("Write Byte to Gayle Ident 0x%06x (0x%06x)\n",address,value);
- return;
- }
-
- if (address == 0xDD203A) {
- printf("Write Byte to 0xDD203A Gayle 0x%06x (0x%06x)\n",address,value);
- gayle_a4k = value;
- return;
- }
-
- if (address == GIRQ || address == GIRQ_A4000) {
- //printf("Write Byte to Gayle GIRQ 0x%06x (0x%06x)\n",address,value);
- gayle_irq = (gayle_irq & value) & (value & (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR));
- return;
- }
-
- if (address == GCS) {
- printf("Write Byte to Gayle GCS 0x%06x (0x%06x)\n", address, value);
- gayle_cs_mask = value & ~3;
- gayle_cs &= ~3;
- gayle_cs |= value & 3;
- return;
- }
-
- if (address == GINT) {
- printf("Write Byte to Gayle GINT 0x%06x (0x%06x)\n", address, value);
- gayle_int = value;
- return;
- }
-
- if (address == GCONF) {
- printf("Write Byte to Gayle GCONF 0x%06x (0x%06x)\n", address, value);
- gayle_cfg = value;
- return;
- }
-
- if (address == RAMSEY_REG) {
- printf("Write Byte to RAMSEY_REG Space 0x%06x (0x%06x)\n", address, value);
- ramsey_cfg = value & 0x0f;
- return;
- }
-
- printf("Write Byte to Gayle Space 0x%06x (0x%06x)\n", address, value);
-}
-
-void writeGayle(unsigned int address, unsigned int value) {
- if (address == GDATA || address == GDATA_A4000) {
- ide_write16(ide0, ide_data, value);
- return;
- }
-
- if (address == GIRQ_A4000) {
- gayle_a4k_irq = value;
- return;
- }
-
- printf("Write Word to Gayle Space 0x%06x (0x%06x)\n", address, value);
-}
-
-void writeGayleL(unsigned int address, unsigned int value) {
- printf("Write Long to Gayle Space 0x%06x (0x%06x)\n", address, value);
-}
-
-uint8_t readGayleB(unsigned int address) {
- if (address == GERROR || address == GERROR_A4000) {
- return ide_read8(ide0, ide_error_r);
- }
- if (address == GSTATUS || address == GSTATUS_A4000) {
- return ide_read8(ide0, ide_status_r);
- }
-
- if (address == GSECTCNT || address == GSECTCNT_A4000) {
- return ide_read8(ide0, ide_sec_count);
- }
-
- if (address == GSECTNUM || address == GSECTNUM_A4000) {
- return ide_read8(ide0, ide_sec_num);
- }
-
- if (address == GCYLLOW || address == GCYLLOW_A4000) {
- return ide_read8(ide0, ide_cyl_low);
- }
-
- if (address == GCYLHIGH || address == GCYLHIGH_A4000) {
- return ide_read8(ide0, ide_cyl_hi);
- }
-
- if (address == GDEVHEAD || address == GDEVHEAD_A4000) {
- return ide_read8(ide0, ide_dev_head);
- }
-
- if (address == GCTRL || address == GCTRL_A4000) {
- return ide_read8(ide0, ide_altst_r);
- }
-
- if (address == 0xDD203A) {
- printf("Write Byte to 0xDD203A Gayle 0x%06x (0x%06x)\n",address, gayle_a4k);
- return gayle_a4k;
- }
-
- if (address == GIDENT) {
- uint8_t val;
- // printf("Read Byte from Gayle Ident 0x%06x (0x%06x)\n",address,counter);
- if (counter == 0 || counter == 1 || counter == 3) {
- val = 0x80; // 80; to enable gayle
- } else {
- val = 0x00;
- }
- counter++;
- return val;
- }
-
- if (address == GARY_REG5) {
- uint8_t val;
- printf("Read Byte from GARY Ident 0x%06x (0x%06x)\n",address,counter);
- if (counter == 0 || counter == 1 || counter == 3) {
- val = 0x80; // 80; to enable GARY
- } else {
- val = 0x00;
- }
- counter++;
- return val;
- }
-
-
- if (address == GIRQ || address == GIRQ_A4000) {
- //printf("Read Byte From GIRQ Space 0x%06x\n",gayle_irq);
- return 0x80;//gayle_irq;
-/*
- uint8_t irq;
- irq = ide0->drive->intrq;
-
- if (irq == 1) {
- // printf("IDE IRQ: %x\n",irq);
- return 0x80; // gayle_irq;
- }
-
- return 0;
-*/
- }
-
- if (address == GCS) {
- printf("Read Byte From GCS Space 0x%06x\n", 0x1234);
- uint8_t v;
- v = gayle_cs_mask | gayle_cs;
- return v;
- }
-
- if (address == GINT) {
- printf("Read Byte From GINT Space 0x%06x\n",gayle_int);
- return gayle_int;
- }
-
- if (address == GCONF) {
- printf("Read Byte From GCONF Space 0x%06x\n", gayle_cfg & 0x0f);
- return gayle_cfg & 0x0f;
- }
-
- if (address == GARY_REG0) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg0 & 0x80);
- return gary_cfg0;
- }
- if (address == GARY_REG1) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg1 & 0x80);
- return gary_cfg1;
- }
- if (address == GARY_REG2) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg2 & 0x80);
- return gary_cfg2;
- }
- if (address == GARY_REG3) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg3 & 0x80);
- return gary_cfg3;
- }
- if (address == GARY_REG4) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg4 & 0x80);
- return gary_cfg4;
- }
- if (address == GARY_REG5) {
- printf("Read Byte From GARY_REG Space 0x%06x (0x%06x)\n", address, gary_cfg5 & 0x80);
- return gary_cfg5;
- }
-
- if (address == RAMSEY_REG) {
- printf("Read Byte From RAMSEY_REG Space 0x%06x (0x%06x)\n", address, ramsey_cfg & 0x0f);
- return ramsey_cfg;
- }
-
- if (address == RAMSEY_ID) {
- printf("Read Byte From RAMSEY_ID Space 0x%06x (0x%06x)\n", address, ramsey_id & 0x0f);
- return ramsey_id;
- }
-
- printf("Read Byte From Gayle Space 0x%06x\n", address);
- return 0xFF;
-}
-
-uint16_t readGayle(unsigned int address) {
- if (address == GDATA || address == GDATA_A4000) {
- uint16_t value;
- value = ide_read16(ide0, ide_data);
- // value = (value << 8) | (value >> 8);
- return value;
- }
- if (address == GIRQ_A4000) {
- //printf("Read Word From GIRQ_A4000 Space 0x%06x\n", address);
- gayle_a4k_irq = 0x8000;
- return 0x80FF;
- }
- printf("Read Word From Gayle Space 0x%06x\n", address);
- return 0x8000;
-}
-
-uint32_t readGayleL(unsigned int address) {
- printf("Read Long From Gayle Space 0x%06x\n", address);
- return 0x8000;
-}
+++ /dev/null
-//
-// Gayle.h
-// Omega
-//
-// Created by Matt Parsons on 06/03/2019.
-// Copyright © 2019 Matt Parsons. All rights reserved.
-//
-
-#ifndef Gayle_h
-#define Gayle_h
-
-#include <stdio.h>
-#include <stdint.h>
-
-
-
-
-uint8_t CheckIrq(void);
-void InitGayle(void);
-void writeGayleB(unsigned int address, unsigned value);
-void writeGayle(unsigned int address, unsigned value);
-void writeGayleL(unsigned int address, unsigned value);
-uint8_t readGayleB(unsigned int address);
-uint16_t readGayle(unsigned int address);
-uint32_t readGayleL(unsigned int address);
-#endif /* Gayle_h */
EXENAME = emulator
MAINFILES = emulator.c \
- Gayle.c \
- ide.c \
memory_mapped.c \
config_file/config_file.c \
input/input.c \
+ gpio/ps_protocol.c \
platforms/platforms.c \
platforms/amiga/amiga-autoconf.c \
platforms/amiga/amiga-platform.c \
platforms/amiga/amiga-registers.c \
platforms/dummy/dummy-platform.c \
- platforms/dummy/dummy-registers.c
-
-MUSASHIFILES = m68kcpu.c softfloat/softfloat.c
+ platforms/dummy/dummy-registers.c \
+ platforms/amiga/Gayle.c \
+ platforms/amiga/hunk-reloc.c \
+ platforms/amiga/gayle-ide/ide.c \
+ platforms/amiga/cdtv-dmac.c \
+ platforms/amiga/rtg/rtg.c \
+ platforms/amiga/rtg/rtg-output.c \
+ platforms/amiga/rtg/rtg-gfx.c \
+ platforms/amiga/piscsi/piscsi.c \
+ platforms/amiga/net/pi-net.c \
+ platforms/shared/rtc.c
+
+MUSASHIFILES = m68kcpu.c m68kdasm.c softfloat/softfloat.c
MUSASHIGENCFILES = m68kops.c
MUSASHIGENHFILES = m68kops.h
MUSASHIGENERATOR = m68kmake
CC = gcc
WARNINGS = -Wall -Wextra -pedantic
-CFLAGS = $(WARNINGS) -march=armv7 -O3
-LFLAGS = $(WARNINGS)
+CFLAGS = $(WARNINGS) -I. -march=armv8-a -mfloat-abi=hard -mfpu=neon-fp-armv8 -O3 -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE
+LFLAGS = $(WARNINGS) `sdl2-config --libs`
TARGET = $(EXENAME)$(EXE)
* Hardware files are in Hardware.zip, using the hardware design or parts of it in a commercial product (aka selling with profit) needs a explicit approval from me!
* Even selling blank PCBs at eBay or so without my approval might makes me pretty mad and probably leads to the forthcomming related projects to be closed source. You have been warned :)
+# wip-crap tutorial/quickstart
-Simple quickstart
+In order to successfully use the features on the wip-crap branch, you need to take a few additional steps:
+* Follow the steps in the "Simple quickstart" below up to `sudo apt-install git`, then do this:
+* `git clone https://github.com/beeanyew/pistorm.git`
+* `cd pistorm`
+* `git checkout wip-crap`
+* `sudo apt-get install libsdl2-dev`
+* `make`
+* Follow the instructions for `FPGA bitstream update` below the quickstart. This is very important, as the latest commit on the branch uses the updated proto3 firmware.
+# Simple quickstart
+
* Download Raspberry OS from https://www.raspberrypi.org/software/operating-systems/ , the Lite version is sufficent
* Write the Image to a SD Card (8GB sized is plenty, for larger HDD Images pick a bigger one)
* Install the pistorm adapter inplace of the orignal CPU into the Amiga500. Make sure the pistorm sits flush and correct in the Amiga.
to start the pistorm emulator
-run : `./run.sh`
+run : `sudo ./emulator`
to exit emulation
-`ctrl+c`
+`ctrl+c` or pressing `q` on the keyboard connected to the Raspberry Pi.
-If you want to use the minimal hdd image you need to unpack it :
-run : `tar xvfz hd0.tar.gz`
+The IDE emulation can take both hard drive images generated using `makedisk` in the `ide` directory (these have a 1KB header) or headerless RDSK/RDB images created for instance in WinUAE or as empty files. The IDE emulation currently has a quirk that may require you to reduce/increase the size of the image file by 2MB in order for it to work.
-**Currently the emulation is a bit buggy on IDE Interrupts, so it takes ages to boot from the emulated HDD. This will be fixed soon :)
+Since PiSCSI can now autoboot RDSK hard drive images, using the IDE controller emulation is not recommended unless you already have a suitable .img file set up for it.
-** FPGA bitstream update :
+# FPGA bitstream update :
install openocd
`sudo apt-get install openocd`
--- /dev/null
+gcc buptest.c gpio/gpio.c -o buptest -march=armv8-a -mfloat-abi=hard -mfpu=neon-fp-armv8 -O0
\ No newline at end of file
--- /dev/null
+#include <assert.h>
+#include <dirent.h>
+#include <endian.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <sched.h>
+#include <signal.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <time.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include "emulator.h"
+#include "gpio/gpio.h"
+#include "platforms/amiga/gayle-ide/ide.h"
+
+uint8_t garbege_datas[2 * 1024 * 1024];
+
+struct timespec f2;
+
+uint8_t gayle_int;
+uint32_t mem_fd;
+uint32_t errors = 0;
+
+void sigint_handler(int sig_num) {
+ //if (sig_num) { }
+ //cpu_emulation_running = 0;
+
+ //return;
+ printf("Received sigint %d, exiting.\n", sig_num);
+ if (mem_fd)
+ close(mem_fd);
+
+ exit(0);
+}
+
+int main() {
+ clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &f2);
+ srand((unsigned int)f2.tv_nsec);
+
+ signal(SIGINT, sigint_handler);
+ setup_io();
+
+ printf("Enable 200MHz GPCLK0 on GPIO4\n");
+ gpio_enable_200mhz();
+
+ write_reg(0x01);
+ usleep(100);
+ usleep(1500);
+ write_reg(0x00);
+ usleep(100);
+
+ usleep(1500);
+
+ write_reg(0x00);
+ // printf("Status Reg%x\n",read_reg());
+ usleep(100000);
+ write_reg(0x02);
+ usleep(1500);
+
+ write8(0xbfe201, 0x0101); //CIA OVL
+ write8(0xbfe001, 0x0000); //CIA OVL LOW
+
+ printf("Writing garbege datas.\n");
+ for (uint32_t i = 0; i < 512 * 1024; i++) {
+ while(garbege_datas[i] == 0x00)
+ garbege_datas[i] = (uint8_t)(rand() % 0xFF);
+ write8(i, (uint32_t)garbege_datas[i]);
+ }
+
+ printf("Reading back garbege datas, read8()...\n");
+ for (uint32_t i = 0; i < 512 * 1024; i++) {
+ uint32_t c = read8(i);
+ if (c != garbege_datas[i]) {
+ if (errors < 512)
+ printf("READ8: Garbege data mismatch at $%.6X: %.2X should be %.2X.\n", i, c, garbege_datas[i]);
+ errors++;
+ }
+ }
+ printf("read8 errors total: %d.\n", errors);
+ errors = 0;
+ sleep (1);
+
+ printf("Reading back garbege datas, read16(), even addresses...\n");
+ for (uint32_t i = 0; i < (512 * 1024) - 2; i += 2) {
+ uint32_t c = be16toh(read16(i));
+ if (c != *((uint16_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ16_EVEN: Garbege data mismatch at $%.6X: %.4X should be %.4X.\n", i, c, *((uint16_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read16 even errors total: %d.\n", errors);
+ errors = 0;
+ sleep (1);
+
+ printf("Reading back garbege datas, read16(), odd addresses...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 2; i += 2) {
+ uint32_t c = be16toh((read8(i) << 8) | read8(i + 1));
+ if (c != *((uint16_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ16_ODD: Garbege data mismatch at $%.6X: %.4X should be %.4X.\n", i, c, *((uint16_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read16 odd errors total: %d.\n", errors);
+ errors = 0;
+ sleep (1);
+
+ printf("Reading back garbege datas, read32(), even addresses...\n");
+ for (uint32_t i = 0; i < (512 * 1024) - 4; i += 2) {
+ uint32_t c = be32toh(read32(i));
+ if (c != *((uint32_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ32_EVEN: Garbege data mismatch at $%.6X: %.8X should be %.8X.\n", i, c, *((uint32_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read32 even errors total: %d.\n", errors);
+ errors = 0;
+ sleep (1);
+
+ printf("Reading back garbege datas, read32(), odd addresses...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 4; i += 2) {
+ uint32_t c = read8(i);
+ c |= (be16toh(read16(i + 1)) << 8);
+ c |= (read8(i + 3) << 24);
+ //c = be32toh(c);
+ if (c != *((uint32_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ32_ODD: Garbege data mismatch at $%.6X: %.8X should be %.8X.\n", i, c, *((uint32_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read32 odd errors total: %d.\n", errors);
+ errors = 0;
+ sleep (1);
+
+ printf("Clearing 512KB of Chip again\n");
+ for (uint32_t i = 0; i < 512 * 1024; i++) {
+ write8(i, (uint32_t)0x0);
+ }
+
+ printf("[WORD] Writing garbege datas to Chip, unaligned...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 2; i += 2) {
+ uint16_t v = *((uint16_t *)&garbege_datas[i]);
+ write8(i, (v & 0x00FF));
+ write8(i + 1, (v >> 8));
+ //write16(i, *((uint16_t *)&garbege_datas[i]));
+ }
+
+ sleep (1);
+ printf("Reading back garbege datas, read16(), odd addresses...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 2; i += 2) {
+ //uint32_t c = be16toh(read16(i));
+ uint32_t c = be16toh((read8(i) << 8) | read8(i + 1));
+ if (c != *((uint16_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ16_EVEN: Garbege data mismatch at $%.6X: %.4X should be %.4X.\n", i, c, *((uint16_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read16 even errors total: %d.\n", errors);
+ errors = 0;
+
+ printf("Clearing 512KB of Chip again\n");
+ for (uint32_t i = 0; i < 512 * 1024; i++) {
+ write8(i, (uint32_t)0x0);
+ }
+
+ printf("[LONG] Writing garbege datas to Chip, unaligned...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 4; i += 4) {
+ uint32_t v = *((uint32_t *)&garbege_datas[i]);
+ write8(i , v & 0x0000FF);
+ write16(i + 1, htobe16(((v & 0x00FFFF00) >> 8)));
+ write8(i + 3 , (v & 0xFF000000) >> 24);
+ //write32(i, v);
+ }
+
+ sleep (1);
+ printf("Reading back garbege datas, read32(), even addresses...\n");
+ for (uint32_t i = 1; i < (512 * 1024) - 4; i += 4) {
+ uint32_t c = read8(i);
+ c |= (be16toh(read16(i + 1)) << 8);
+ c |= (read8(i + 3) << 24);
+ //uint32_t c = be32toh(read32(i));
+ if (c != *((uint32_t *)&garbege_datas[i])) {
+ if (errors < 512)
+ printf("READ32_EVEN: Garbege data mismatch at $%.6X: %.8X should be %.8X.\n", i, c, *((uint32_t *)&garbege_datas[i]));
+ errors++;
+ }
+ }
+ printf("read32 even errors total: %d.\n", errors);
+ errors = 0;
+
+ return 0;
+}
+
+void m68k_set_irq(unsigned int level) {
+}
+
+struct ide_controller *get_ide(int index) {
+ return NULL;
+}
-#include "../platforms/platforms.h"
+#include "platforms/platforms.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
cfg->map_type[index] = type;
cfg->map_offset[index] = addr;
cfg->map_size[index] = size;
+ cfg->map_high[index] = addr + size;
cfg->map_mirror[index] = mirr_addr;
if (strlen(map_id)) {
cfg->map_id[index] = (char *)malloc(strlen(map_id) + 1);
file_size = (int)ftell(in);
if (size == 0) {
cfg->map_size[index] = file_size;
+ cfg->map_high[index] = addr + cfg->map_size[index];
}
fseek(in, 0, SEEK_SET);
cfg->map_data[index] = (unsigned char *)calloc(1, cfg->map_size[index]);
case MAPTYPE_REGISTER:
default:
break;
- break;
}
- printf("[MAP %d] Added %s mapping for range %.8lX-%.8lX ID: %s\n", index, map_type_names[type], cfg->map_offset[index], cfg->map_offset[index] + cfg->map_size[index] - 1, cfg->map_id[index] ? cfg->map_id[index] : "None");
+ printf("[MAP %d] Added %s mapping for range %.8lX-%.8lX ID: %s\n", index, map_type_names[type], cfg->map_offset[index], cfg->map_high[index] - 1, cfg->map_id[index] ? cfg->map_id[index] : "None");
+ if (cfg->map_size[index] == cfg->rom_size[index])
+ m68k_add_rom_range(cfg->map_offset[index], cfg->map_high[index], cfg->map_data[index]);
return;
goto skip_line;
trim_whitespace(parse_line);
-
+
get_next_string(parse_line, cur_cmd, &str_pos, ' ');
switch (get_config_item_type(cur_cmd)) {
memset(var_value, 0x00, 128);
get_next_string(parse_line, var_name, &str_pos, ' ');
get_next_string(parse_line, var_value, &str_pos, ' ');
- cfg->platform->setvar(var_name, var_value);
+ cfg->platform->setvar(cfg, var_name, var_value);
break;
}
printf("Unknown config item %s on line %d.\n", cur_cmd, cur_line);
break;
}
-
+
skip_line:;
cur_line++;
}
return -1;
}
+
+int get_mapped_item_by_address(struct emulator_config *cfg, uint32_t address) {
+ for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i++) {
+ if (cfg->map_type[i] == MAPTYPE_NONE || !cfg->map_data[i])
+ continue;
+ if (address >= cfg->map_offset[i] && address < cfg->map_high[i])
+ return i;
+ }
+
+ return -1;
+}
-#include "../m68k.h"
+#ifndef _CONFIG_FILE_H
+#define _CONFIG_FILE_H
+
+#include "m68k.h"
+
+#include <unistd.h>
#define MAX_NUM_MAPPED_ITEMS 8
#define SIZE_KILO 1024
unsigned char map_type[MAX_NUM_MAPPED_ITEMS];
long map_offset[MAX_NUM_MAPPED_ITEMS];
+ long map_high[MAX_NUM_MAPPED_ITEMS];
unsigned int map_size[MAX_NUM_MAPPED_ITEMS];
unsigned int rom_size[MAX_NUM_MAPPED_ITEMS];
unsigned char *map_data[MAX_NUM_MAPPED_ITEMS];
unsigned char mouse_enabled, keyboard_enabled;
unsigned int loop_cycles;
+ unsigned int mapped_low, mapped_high;
+ unsigned int custom_low, custom_high;
};
struct platform_config {
char *subsys;
+ unsigned char id;
int (*custom_read)(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type);
int (*custom_write)(struct emulator_config *cfg, unsigned int addr, unsigned int val, unsigned char type);
int (*register_write)(unsigned int addr, unsigned int value, unsigned char type);
int (*platform_initial_setup)(struct emulator_config *cfg);
- void (*setvar)(char *var, char *val);
+ void (*handle_reset)(struct emulator_config *cfg);
+ void (*shutdown)(struct emulator_config *cfg);
+ void (*setvar)(struct emulator_config *cfg, char *var, char *val);
};
unsigned int get_m68k_cpu_type(char *name);
struct emulator_config *load_config_file(char *filename);
-int handle_mapped_read(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type, unsigned char mirror);
-int handle_mapped_write(struct emulator_config *cfg, unsigned int addr, unsigned int value, unsigned char type, unsigned char mirror);
+int handle_mapped_read(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type);
+int handle_mapped_write(struct emulator_config *cfg, unsigned int addr, unsigned int value, unsigned char type);
int get_named_mapped_item(struct emulator_config *cfg, char *name);
+int get_mapped_item_by_address(struct emulator_config *cfg, uint32_t address);
unsigned int get_int(char *str);
+
+#endif /* _CONFIG_FILE_H */
--- /dev/null
+# Data directory
+
+This is the directory used for storing emulator-related volatile and non-volatile items such as temporary files (volatile) and the CDTV/CD32 SRAM (non-volatile).
platform amiga
# Uncomment to let reads/writes through from/to the RTC memory range
#setvar enable_rtc_emulation 0
-# Uncomment to set a custom HD image file for ide0
+# Uncomment to set a HD image file for ide0 drive 0/1
#setvar hdd0 snakes.img
+#setvar hdd1 snakes2.img
+# Uncomment to enable RTG
+#setvar rtg
+# Uncomment to enable CDTV mode (not working, requires Kickstart 1.3+CDTV extended ROM)
+#setvar cdtv
+# Uncomment this line to enable the PiSCSI interface
+#setvar piscsi
+# Use setvar piscsi0 through piscsi6 to add up to seven mapped drives to the interface.
+#setvar piscsi0 PI0.hdf
+#setvar piscsi1 PI1.hdf
+# Uncomment this line to enable the (currently non-working) Pi-Net interface.
+#setvar pi-net
# Forward mouse events to host system, defaults to off unless toggle key is pressed on the Pi.
# Syntax is mouse [device] [toggle key]
+#include "m68k.h"
+#include "emulator.h"
+#include "platforms/platforms.h"
+#include "input/input.h"
+
+#include "platforms/amiga/Gayle.h"
+#include "platforms/amiga/gayle-ide/ide.h"
+#include "platforms/amiga/amiga-registers.h"
+#include "platforms/amiga/rtg/rtg.h"
+#include "platforms/amiga/hunk-reloc.h"
+#include "platforms/amiga/piscsi/piscsi.h"
+#include "platforms/amiga/piscsi/piscsi-enums.h"
+#include "platforms/amiga/net/pi-net.h"
+#include "platforms/amiga/net/pi-net-enums.h"
+#include "gpio/ps_protocol.h"
+
#include <assert.h>
#include <dirent.h>
#include <endian.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <sys/ioctl.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
-#include <sys/ioctl.h>
-#include "Gayle.h"
-#include "ide.h"
-#include "m68k.h"
-#include "main.h"
-#include "platforms/platforms.h"
-#include "input/input.h"
-//#define BCM2708_PERI_BASE 0x20000000 //pi0-1
-//#define BCM2708_PERI_BASE 0xFE000000 //pi4
-#define BCM2708_PERI_BASE 0x3F000000 // pi3
-#define BCM2708_PERI_SIZE 0x01000000
-#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
-#define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
-#define GPIO_ADDR 0x200000 /* GPIO controller */
-#define GPCLK_ADDR 0x101000
-#define CLK_PASSWD 0x5a000000
-#define CLK_GP0_CTL 0x070
-#define CLK_GP0_DIV 0x074
-
-#define SA0 5
-#define SA1 3
-#define SA2 2
-
-#define STATUSREGADDR \
- GPIO_CLR = 1 << SA0; \
- GPIO_CLR = 1 << SA1; \
- GPIO_SET = 1 << SA2;
-#define W16 \
- GPIO_CLR = 1 << SA0; \
- GPIO_CLR = 1 << SA1; \
- GPIO_CLR = 1 << SA2;
-#define R16 \
- GPIO_SET = 1 << SA0; \
- GPIO_CLR = 1 << SA1; \
- GPIO_CLR = 1 << SA2;
-#define W8 \
- GPIO_CLR = 1 << SA0; \
- GPIO_SET = 1 << SA1; \
- GPIO_CLR = 1 << SA2;
-#define R8 \
- GPIO_SET = 1 << SA0; \
- GPIO_SET = 1 << SA1; \
- GPIO_CLR = 1 << SA2;
-
-#define PAGE_SIZE (4 * 1024)
-#define BLOCK_SIZE (4 * 1024)
-
-#define GPIOSET(no, ishigh) \
- do { \
- if (ishigh) \
- set |= (1 << (no)); \
- else \
- reset |= (1 << (no)); \
- } while (0)
-
-#define FASTBASE 0x07FFFFFF
-#define FASTSIZE 0xFFFFFFF
-#define GAYLEBASE 0xD80000 // D7FFFF
-#define GAYLESIZE 0x6FFFF
-
-#define JOY0DAT 0xDFF00A
-#define JOY1DAT 0xDFF00C
-#define CIAAPRA 0xBFE001
-#define POTGOR 0xDFF016
+
+unsigned char read_ranges;
+unsigned int read_addr[8];
+unsigned int read_upper[8];
+unsigned char *read_data[8];
+unsigned char write_ranges;
+unsigned int write_addr[8];
+unsigned int write_upper[8];
+unsigned char *write_data[8];
int kb_hook_enabled = 0;
int mouse_hook_enabled = 0;
int cpu_emulation_running = 1;
-char mouse_dx = 0, mouse_dy = 0;
-char mouse_buttons = 0;
+uint8_t mouse_dx = 0, mouse_dy = 0;
+uint8_t mouse_buttons = 0;
+uint8_t mouse_extra = 0;
+
+extern uint8_t gayle_int;
+extern uint8_t gayle_ide_enabled;
+extern uint8_t gayle_emulation_enabled;
+extern uint8_t gayle_a4k_int;
+extern volatile unsigned int *gpio;
+extern volatile uint16_t srdata;
+extern uint8_t realtime_graphics_debug;
+uint8_t realtime_disassembly, int2_enabled = 0;
+uint32_t do_disasm = 0, old_level;
+uint32_t last_irq = 0, last_last_irq = 0;
+char c = 0, c_code = 0, c_type = 0; // @todo temporary main/cpu_task scope workaround until input moved to a thread
+
+char disasm_buf[4096];
#define KICKBASE 0xF80000
#define KICKSIZE 0x7FFFF
int mem_fd, mouse_fd = -1, keyboard_fd = -1;
int mem_fd_gpclk;
-int gayle_emulation_enabled = 1;
-void *gpio_map;
-void *gpclk_map;
+int irq;
+int gayleirq;
+
+//#define MUSASHI_HAX
+
+#ifdef MUSASHI_HAX
+#include "m68kcpu.h"
+extern m68ki_cpu_core m68ki_cpu;
+extern int m68ki_initial_cycles;
+extern int m68ki_remaining_cycles;
+
+#define M68K_SET_IRQ(i) old_level = CPU_INT_LEVEL; \
+ CPU_INT_LEVEL = (i << 8); \
+ if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700) \
+ m68ki_cpu.nmi_pending = TRUE;
+#define M68K_END_TIMESLICE m68ki_initial_cycles = GET_CYCLES(); \
+ SET_CYCLES(0);
+#else
+#define M68K_SET_IRQ m68k_set_irq
+#define M68K_END_TIMESLICE m68k_end_timeslice()
+#endif
+
+#define NOP asm("nop"); asm("nop"); asm("nop"); asm("nop");
+
+#define DEBUG_EMULATOR
+#ifdef DEBUG_EMULATOR
+#define DEBUG printf
+#else
+#define DEBUG(...)
+#endif
// Configurable emulator options
unsigned int cpu_type = M68K_CPU_TYPE_68000;
-unsigned int loop_cycles = 300;
+unsigned int loop_cycles = 300, irq_status = 0;
struct emulator_config *cfg = NULL;
-char keyboard_file[256] = "/dev/input/event0";
-
-// I/O access
-volatile unsigned int *gpio;
-volatile unsigned int *gpclk;
-volatile unsigned int gpfsel0;
-volatile unsigned int gpfsel1;
-volatile unsigned int gpfsel2;
-volatile unsigned int gpfsel0_o;
-volatile unsigned int gpfsel1_o;
-volatile unsigned int gpfsel2_o;
-
-// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
-// SET_GPIO_ALT(x,y)
-#define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
-#define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
-#define SET_GPIO_ALT(g, a) \
- *(gpio + (((g) / 10))) |= \
- (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
-
-#define GPIO_SET \
- *(gpio + 7) // sets bits which are 1 ignores bits which are 0
-#define GPIO_CLR \
- *(gpio + 10) // clears bits which are 1 ignores bits which are 0
-
-#define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
-
-#define GPIO_PULL *(gpio + 37) // Pull up/pull down
-#define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
-
-void setup_io();
-
-uint32_t read8(uint32_t address);
-void write8(uint32_t address, uint32_t data);
-
-uint32_t read16(uint32_t address);
-void write16(uint32_t address, uint32_t data);
-
-void write32(uint32_t address, uint32_t data);
-uint32_t read32(uint32_t address);
-
-uint16_t read_reg(void);
-void write_reg(unsigned int value);
-
-volatile uint16_t srdata;
-volatile uint32_t srdata2;
-volatile uint32_t srdata2_old;
-
-//unsigned char g_kick[524288];
-//unsigned char g_ram[FASTSIZE + 1]; /* RAM */
-unsigned char toggle;
-static volatile unsigned char ovl;
+char keyboard_file[256] = "/dev/input/event1";
+
+uint64_t trig_irq = 0, serv_irq = 0;
+uint16_t irq_delay = 0;
+
+void *ipl_task(void *args) {
+ printf("IPL thread running\n");
+ uint16_t old_irq = 0;
+ uint32_t value;
+
+ while (1) {
+ value = *(gpio + 13);
+
+ if (!(value & (1 << PIN_IPL_ZERO))) {
+ irq = 1;
+ old_irq = irq_delay;
+ NOP
+ M68K_END_TIMESLICE;
+ }
+ else {
+ if (irq) {
+ if (old_irq) {
+ old_irq--;
+ }
+ else {
+ irq = 0;
+ }
+ NOP
+ M68K_END_TIMESLICE;
+ }
+ }
+
+ if (gayle_ide_enabled) {
+ if (((gayle_int & 0x80) || gayle_a4k_int) && (get_ide(0)->drive[0].intrq || get_ide(0)->drive[1].intrq)) {
+ //get_ide(0)->drive[0].intrq = 0;
+ gayleirq = 1;
+ M68K_END_TIMESLICE;
+ }
+ else
+ gayleirq = 0;
+ }
+ //usleep(0);
+ NOP NOP NOP NOP NOP NOP NOP NOP
+ NOP NOP NOP NOP NOP NOP NOP NOP
+ NOP NOP NOP NOP NOP NOP NOP NOP
+ /*NOP NOP NOP NOP NOP NOP NOP NOP
+ NOP NOP NOP NOP NOP NOP NOP NOP
+ NOP NOP NOP NOP NOP NOP NOP NOP*/
+ }
+ return args;
+}
+
+void *cpu_task() {
+ m68k_pulse_reset();
+ while (42) {
+ if (mouse_hook_enabled) {
+ get_mouse_status(&mouse_dx, &mouse_dy, &mouse_buttons, &mouse_extra);
+ }
+
+ if (realtime_disassembly && (do_disasm || cpu_emulation_running)) {
+ m68k_disassemble(disasm_buf, m68k_get_reg(NULL, M68K_REG_PC), cpu_type);
+ printf("REGA: 0:$%.8X 1:$%.8X 2:$%.8X 3:$%.8X 4:$%.8X 5:$%.8X 6:$%.8X 7:$%.8X\n", m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), m68k_get_reg(NULL, M68K_REG_A2), m68k_get_reg(NULL, M68K_REG_A3), \
+ m68k_get_reg(NULL, M68K_REG_A4), m68k_get_reg(NULL, M68K_REG_A5), m68k_get_reg(NULL, M68K_REG_A6), m68k_get_reg(NULL, M68K_REG_A7));
+ printf("REGD: 0:$%.8X 1:$%.8X 2:$%.8X 3:$%.8X 4:$%.8X 5:$%.8X 6:$%.8X 7:$%.8X\n", m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2), m68k_get_reg(NULL, M68K_REG_D3), \
+ m68k_get_reg(NULL, M68K_REG_D4), m68k_get_reg(NULL, M68K_REG_D5), m68k_get_reg(NULL, M68K_REG_D6), m68k_get_reg(NULL, M68K_REG_D7));
+ printf("%.8X (%.8X)]] %s\n", m68k_get_reg(NULL, M68K_REG_PC), (m68k_get_reg(NULL, M68K_REG_PC) & 0xFFFFFF), disasm_buf);
+ if (do_disasm)
+ do_disasm--;
+ m68k_execute(1);
+ }
+ else {
+ if (cpu_emulation_running)
+ m68k_execute(loop_cycles);
+ }
+
+ if (irq) {
+ while (irq) {
+ last_irq = ((read_reg() & 0xe000) >> 13);
+ if (last_irq != last_last_irq) {
+ last_last_irq = last_irq;
+ M68K_SET_IRQ(last_irq);
+ }
+ m68k_execute(5);
+ }
+ if (gayleirq && int2_enabled) {
+ write16(0xdff09c, 0x8000 | (1 << 3) && last_irq != 2);
+ last_last_irq = last_irq;
+ last_irq = 2;
+ M68K_SET_IRQ(2);
+ }
+ M68K_SET_IRQ(0);
+ last_last_irq = 0;
+ }
+ /*else {
+ if (last_irq != 0) {
+ M68K_SET_IRQ(0);
+ last_last_irq = last_irq;
+ last_irq = 0;
+ }
+ }*/
+
+ while (get_key_char(&c, &c_code, &c_type)) {
+ if (c && c == cfg->keyboard_toggle_key && !kb_hook_enabled) {
+ kb_hook_enabled = 1;
+ printf("Keyboard hook enabled.\n");
+ }
+ else if (kb_hook_enabled) {
+ if (c == 0x1B && c_type) {
+ kb_hook_enabled = 0;
+ printf("Keyboard hook disabled.\n");
+ }
+ else {
+ /*printf("Key code: %.2X - ", c_code);
+ switch (c_type) {
+ case 0:
+ printf("released.\n");
+ break;
+ case 1:
+ printf("pressed.\n");
+ break;
+ case 2:
+ printf("repeat.\n");
+ break;
+ default:
+ printf("unknown.\n");
+ break;
+ }*/
+ if (queue_keypress(c_code, c_type, cfg->platform->id) && int2_enabled && last_irq != 2) {
+ //last_irq = 0;
+ //M68K_SET_IRQ(2);
+ }
+ }
+ }
+
+ // pause pressed; trigger nmi (int level 7)
+ if (c == 0x01 && c_type) {
+ printf("[INT] Sending NMI\n");
+ M68K_SET_IRQ(7);
+ }
+
+ if (!kb_hook_enabled && c_type) {
+ if (c && c == cfg->mouse_toggle_key) {
+ mouse_hook_enabled ^= 1;
+ printf("Mouse hook %s.\n", mouse_hook_enabled ? "enabled" : "disabled");
+ mouse_dx = mouse_dy = mouse_buttons = mouse_extra = 0;
+ }
+ if (c == 'r') {
+ cpu_emulation_running ^= 1;
+ printf("CPU emulation is now %s\n", cpu_emulation_running ? "running" : "stopped");
+ }
+ if (c == 'g') {
+ realtime_graphics_debug ^= 1;
+ printf("Real time graphics debug is now %s\n", realtime_graphics_debug ? "on" : "off");
+ }
+ if (c == 'R') {
+ cpu_pulse_reset();
+ //m68k_pulse_reset();
+ printf("CPU emulation reset.\n");
+ }
+ if (c == 'q') {
+ printf("Quitting and exiting emulator.\n");
+ goto stop_cpu_emulation;
+ }
+ if (c == 'd') {
+ realtime_disassembly ^= 1;
+ do_disasm = 1;
+ printf("Real time disassembly is now %s\n", realtime_disassembly ? "on" : "off");
+ }
+ if (c == 'D') {
+ int r = get_mapped_item_by_address(cfg, 0x08000000);
+ if (r != -1) {
+ printf("Dumping first 16MB of mapped range %d.\n", r);
+ FILE *dmp = fopen("./memdmp.bin", "wb+");
+ fwrite(cfg->map_data[r], 16 * SIZE_MEGA, 1, dmp);
+ fclose(dmp);
+ }
+ }
+ if (c == 's' && realtime_disassembly) {
+ do_disasm = 1;
+ }
+ if (c == 'S' && realtime_disassembly) {
+ do_disasm = 128;
+ }
+ }
+ }
+
+ if (mouse_hook_enabled && (mouse_extra != 0x00)) {
+ // mouse wheel events have occurred; unlike l/m/r buttons, these are queued as keypresses, so add to end of buffer
+ switch (mouse_extra) {
+ case 0xff:
+ // wheel up
+ queue_keypress(0xfe, KEYPRESS_PRESS, PLATFORM_AMIGA);
+ break;
+ case 0x01:
+ // wheel down
+ queue_keypress(0xff, KEYPRESS_PRESS, PLATFORM_AMIGA);
+ break;
+ }
+
+ // dampen the scroll wheel until next while loop iteration
+ mouse_extra = 0x00;
+ }
+ }
+
+stop_cpu_emulation:
+ printf("[CPU] End of CPU thread\n");
+}
+
+void stop_cpu_emulation(uint8_t disasm_cur) {
+ M68K_END_TIMESLICE;
+ if (disasm_cur) {
+ m68k_disassemble(disasm_buf, m68k_get_reg(NULL, M68K_REG_PC), cpu_type);
+ printf("REGA: 0:$%.8X 1:$%.8X 2:$%.8X 3:$%.8X 4:$%.8X 5:$%.8X 6:$%.8X 7:$%.8X\n", m68k_get_reg(NULL, M68K_REG_A0), m68k_get_reg(NULL, M68K_REG_A1), m68k_get_reg(NULL, M68K_REG_A2), m68k_get_reg(NULL, M68K_REG_A3), \
+ m68k_get_reg(NULL, M68K_REG_A4), m68k_get_reg(NULL, M68K_REG_A5), m68k_get_reg(NULL, M68K_REG_A6), m68k_get_reg(NULL, M68K_REG_A7));
+ printf("REGD: 0:$%.8X 1:$%.8X 2:$%.8X 3:$%.8X 4:$%.8X 5:$%.8X 6:$%.8X 7:$%.8X\n", m68k_get_reg(NULL, M68K_REG_D0), m68k_get_reg(NULL, M68K_REG_D1), m68k_get_reg(NULL, M68K_REG_D2), m68k_get_reg(NULL, M68K_REG_D3), \
+ m68k_get_reg(NULL, M68K_REG_D4), m68k_get_reg(NULL, M68K_REG_D5), m68k_get_reg(NULL, M68K_REG_D6), m68k_get_reg(NULL, M68K_REG_D7));
+ printf("%.8X (%.8X)]] %s\n", m68k_get_reg(NULL, M68K_REG_PC), (m68k_get_reg(NULL, M68K_REG_PC) & 0xFFFFFF), disasm_buf);
+ realtime_disassembly = 1;
+ }
+
+ cpu_emulation_running = 0;
+ do_disasm = 0;
+}
+
+unsigned int ovl;
static volatile unsigned char maprom;
void sigint_handler(int sig_num) {
if (mem_fd)
close(mem_fd);
- exit(0);
-}
-
-void *iplThread(void *args) {
- printf("IPL thread running/n");
-
- while (42) {
-
- if (GET_GPIO(1) == 0) {
- toggle = 1;
- m68k_end_timeslice();
- //printf("thread!/n");
- } else {
- toggle = 0;
- };
- usleep(1);
+ if (cfg->platform->shutdown) {
+ cfg->platform->shutdown(cfg);
}
+ printf("IRQs triggered: %lld\n", trig_irq);
+ printf("IRQs serviced: %lld\n", serv_irq);
+
+ exit(0);
}
int main(int argc, char *argv[]) {
int g;
- const struct sched_param priority = {99};
+ //const struct sched_param priority = {99};
+
+ if (argc > 1) {
+ irq_delay = atoi(argv[1]);
+ printf("Setting IRQ delay to %d loops (%s).\n", irq_delay, argv[1]);
+ }
// Some command line switch stuffles
for (g = 1; g < argc; g++) {
- if (strcmp(argv[g], "--disable-gayle") == 0) {
- gayle_emulation_enabled = 0;
- }
- else if (strcmp(argv[g], "--cpu_type") == 0 || strcmp(argv[g], "--cpu") == 0) {
+ if (strcmp(argv[g], "--cpu_type") == 0 || strcmp(argv[g], "--cpu") == 0) {
if (g + 1 >= argc) {
printf("%s switch found, but no CPU type specified.\n", argv[g]);
} else {
}
if (cfg->mouse_enabled) {
- mouse_fd = open(cfg->mouse_file, O_RDONLY | O_NONBLOCK);
+ mouse_fd = open(cfg->mouse_file, O_RDWR | O_NONBLOCK);
if (mouse_fd == -1) {
printf("Failed to open %s, can't enable mouse hook.\n", cfg->mouse_file);
cfg->mouse_enabled = 0;
+ } else {
+ /**
+ * *-*-*-* magic numbers! *-*-*-*
+ * great, so waaaay back in the history of the pc, the ps/2 protocol set the standard for mice
+ * and in the process, the mouse sample rate was defined as a way of putting mice into vendor-specific modes.
+ * as the ancient gpm command explains, almost everything except incredibly old mice talk the IntelliMouse
+ * protocol, which reports four bytes. by default, every mouse starts in 3-byte mode (don't report wheel or
+ * additional buttons) until imps2 magic is sent. so, command $f3 is "set sample rate", followed by a byte.
+ */
+ uint8_t mouse_init[] = { 0xf4, 0xf3, 0x64 }; // enable, then set sample rate 100
+ uint8_t imps2_init[] = { 0xf3, 0xc8, 0xf3, 0x64, 0xf3, 0x50 }; // magic sequence; set sample 200, 100, 80
+ if (write(mouse_fd, mouse_init, sizeof(mouse_init)) != -1) {
+ if (write(mouse_fd, imps2_init, sizeof(imps2_init)) == -1)
+ printf("[MOUSE] Couldn't enable scroll wheel events; is this mouse from the 1980s?\n");
+ } else
+ printf("[MOUSE] Mouse didn't respond to normal PS/2 init; have you plugged a brick in by mistake?\n");
}
}
printf("Failed to open keyboard event source.\n");
}
- sched_setscheduler(0, SCHED_FIFO, &priority);
- mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
-
InitGayle();
signal(SIGINT, sigint_handler);
- setup_io();
+ /*setup_io();
//goto skip_everything;
// Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
// on pi model
printf("Enable 200MHz GPCLK0 on GPIO4\n");
-
- *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
- usleep(10);
- while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
- ;
- usleep(100);
- *(gpclk + (CLK_GP0_DIV / 4)) =
- CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
- usleep(10);
- *(gpclk + (CLK_GP0_CTL / 4)) =
- CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
- usleep(10);
- while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
- ;
- usleep(100);
-
- SET_GPIO_ALT(4, 0); // gpclk0
-
- // set SA to output
- INP_GPIO(2);
- OUT_GPIO(2);
- INP_GPIO(3);
- OUT_GPIO(3);
- INP_GPIO(5);
- OUT_GPIO(5);
-
- // set gpio0 (aux0) and gpio1 (aux1) to input
- INP_GPIO(0);
- INP_GPIO(1);
-
- // Set GPIO pins 6,7 and 8-23 to output
- for (g = 6; g <= 23; g++) {
- INP_GPIO(g);
- OUT_GPIO(g);
- }
- printf("Precalculate GPIO8-23 as Output\n");
- gpfsel0_o = *(gpio); // store gpio ddr
- printf("gpfsel0: %#x\n", gpfsel0_o);
- gpfsel1_o = *(gpio + 1); // store gpio ddr
- printf("gpfsel1: %#x\n", gpfsel1_o);
- gpfsel2_o = *(gpio + 2); // store gpio ddr
- printf("gpfsel2: %#x\n", gpfsel2_o);
-
- // Set GPIO pins 8-23 to input
- for (g = 8; g <= 23; g++) {
- INP_GPIO(g);
- }
- printf("Precalculate GPIO8-23 as Input\n");
- gpfsel0 = *(gpio); // store gpio ddr
- printf("gpfsel0: %#x\n", gpfsel0);
- gpfsel1 = *(gpio + 1); // store gpio ddr
- printf("gpfsel1: %#x\n", gpfsel1);
- gpfsel2 = *(gpio + 2); // store gpio ddr
- printf("gpfsel2: %#x\n", gpfsel2);
-
- GPIO_CLR = 1 << 2;
- GPIO_CLR = 1 << 3;
- GPIO_SET = 1 << 5;
-
- GPIO_SET = 1 << 6;
- GPIO_SET = 1 << 7;
+ gpio_enable_200mhz();
// reset cpld statemachine first
// reset amiga and statemachine
skip_everything:;
- cpu_pulse_reset();
- ovl = 1;
- m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
- m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
usleep(1500);
m68k_init();
printf("Setting CPU type to %d.\n", cpu_type);
m68k_set_cpu_type(cpu_type);
- m68k_pulse_reset();
+ cpu_pulse_reset();
if (maprom == 1) {
m68k_set_reg(M68K_REG_PC, 0xF80002);
} else {
m68k_set_reg(M68K_REG_PC, 0x0);
- }
+ }*/
+ ps_setup_protocol();
+ ps_reset_state_machine();
+ ps_pulse_reset();
-/*
- pthread_t id;
- int err;
- err = pthread_create(&id, NULL, &iplThread, NULL);
- if (err != 0)
- printf("\ncan't create IPL thread :[%s]", strerror(err));
- else
- printf("\n IPL Thread created successfully\n");
-*/
- char c = 0;
+ usleep(1500);
+ m68k_init();
+ printf("Setting CPU type to %d.\n", cpu_type);
+ m68k_set_cpu_type(cpu_type);
+ cpu_pulse_reset();
- m68k_pulse_reset();
- while (42) {
- if (mouse_hook_enabled) {
- if (get_mouse_status(&mouse_dx, &mouse_dy, &mouse_buttons)) {
- //printf("Maus: %d (%.2X), %d (%.2X), B:%.2X\n", mouse_dx, mouse_dx, mouse_dy, mouse_dy, mouse_buttons);
- }
+ pthread_t ipl_tid, cpu_tid;
+ int err;
+ err = pthread_create(&ipl_tid, NULL, &ipl_task, NULL);
+ if (err != 0)
+ printf("[ERROR] Cannot create IPL thread: [%s]", strerror(err));
+ else {
+ pthread_setname_np(ipl_tid, "pistorm: ipl");
+ printf("IPL thread created successfully\n");
}
- if (cpu_emulation_running)
- m68k_execute(loop_cycles);
-
- // FIXME: Rework this to use keyboard events instead.
- while (get_key_char(&c)) {
- if (c == cfg->keyboard_toggle_key && !kb_hook_enabled) {
- kb_hook_enabled = 1;
- printf("Keyboard hook enabled.\n");
- }
- else if (c == 0x1B && kb_hook_enabled) {
- kb_hook_enabled = 0;
- printf("Keyboard hook disabled.\n");
- }
- if (!kb_hook_enabled) {
- if (c == cfg->mouse_toggle_key) {
- mouse_hook_enabled ^= 1;
- printf("Mouse hook %s.\n", mouse_hook_enabled ? "enabled" : "disabled");
- mouse_dx = mouse_dy = mouse_buttons = 0;
- }
- if (c == 'r') {
- cpu_emulation_running ^= 1;
- printf("CPU emulation is now %s\n", cpu_emulation_running ? "running" : "stopped");
- }
- if (c == 'R') {
- cpu_pulse_reset();
- m68k_pulse_reset();
- printf("CPU emulation reset.\n");
- }
- if (c == 'q') {
- printf("Quitting and exiting emulator.\n");
- goto stop_cpu_emulation;
- }
- }
+ // create cpu task
+ err = pthread_create(&cpu_tid, NULL, &cpu_task, NULL);
+ if (err != 0)
+ printf("[ERROR] Cannot create CPU thread: [%s]", strerror(err));
+ else {
+ pthread_setname_np(cpu_tid, "pistorm: cpu");
+ printf("CPU thread created successfully\n");
}
-/*
- if (toggle == 1){
- srdata = read_reg();
- m68k_set_irq((srdata >> 13) & 0xff);
- } else {
- m68k_set_irq(0);
- };
- usleep(1);
-*/
-
- if (GET_GPIO(1) == 0) {
- srdata = read_reg();
- m68k_set_irq((srdata >> 13) & 0xff);
- } else {
- if (CheckIrq() == 1) {
- write16(0xdff09c, 0x8008);
- m68k_set_irq(2);
- }
- else
- m68k_set_irq(0);
- };
-
- }
-
- stop_cpu_emulation:;
+ // wait for cpu task to end before closing up and finishing
+ pthread_join(cpu_tid, NULL);
+ printf("[MAIN] All threads appear to have concluded; ending process\n");
if (mouse_fd != -1)
close(mouse_fd);
}
void cpu_pulse_reset(void) {
- write_reg(0x00);
+ ps_pulse_reset();
+ //write_reg(0x00);
// printf("Status Reg%x\n",read_reg());
- usleep(100000);
- write_reg(0x02);
+ //usleep(100000);
+ //write_reg(0x02);
// printf("Status Reg%x\n",read_reg());
+ if (cfg->platform->handle_reset)
+ cfg->platform->handle_reset(cfg);
+
+
+ m68k_write_memory_16(INTENA, 0x7FFF);
+ ovl = 1;
+ m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
+ m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
+
+ m68k_pulse_reset();
}
int cpu_irq_ack(int level) {
}
static unsigned int target = 0;
+static uint8_t send_keypress = 0;
+
+uint8_t cdtv_dmac_reg_idx_read();
+void cdtv_dmac_reg_idx_write(uint8_t value);
+uint32_t cdtv_dmac_read(uint32_t address, uint8_t type);
+void cdtv_dmac_write(uint32_t address, uint32_t value, uint8_t type);
+
+#define PLATFORM_CHECK_READ(a) \
+ if (address >= cfg->custom_low && address < cfg->custom_high) { \
+ unsigned int target = 0; \
+ switch(cfg->platform->id) { \
+ case PLATFORM_AMIGA: { \
+ if (address >= PISCSI_OFFSET && address < PISCSI_UPPER) { \
+ return handle_piscsi_read(address, a); \
+ } \
+ if (address >= PINET_OFFSET && address < PINET_UPPER) { \
+ return handle_pinet_read(address, a); \
+ } \
+ if (address >= PIGFX_RTG_BASE && address < PIGFX_UPPER) { \
+ return rtg_read((address & 0x0FFFFFFF), a); \
+ } \
+ if (custom_read_amiga(cfg, address, &target, a) != -1) { \
+ return target; \
+ } \
+ break; \
+ } \
+ default: \
+ break; \
+ } \
+ } \
+ if (ovl || (address >= cfg->mapped_low && address < cfg->mapped_high)) { \
+ if (handle_mapped_read(cfg, address, &target, a) != -1) \
+ return target; \
+ }
unsigned int m68k_read_memory_8(unsigned int address) {
- if (cfg->platform->custom_read && cfg->platform->custom_read(cfg, address, &target, OP_TYPE_BYTE) != -1) {
- return target;
- }
+ PLATFORM_CHECK_READ(OP_TYPE_BYTE);
- if (cfg) {
- int ret = handle_mapped_read(cfg, address, &target, OP_TYPE_BYTE, ovl);
- if (ret != -1)
- return target;
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("BYTE read from DMAC @%.8X:", address);
+ uint32_t v = cdtv_dmac_read(address & 0xFFFF, OP_TYPE_BYTE);
+ printf("%.2X\n", v);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
+ return v;
+ }*/
+
+ /*if (m68k_get_reg(NULL, M68K_REG_PC) >= 0x080032F0 && m68k_get_reg(NULL, M68K_REG_PC) <= 0x080032F0 + 0x4000) {
+ stop_cpu_emulation(1);
+ }*/
+
+
+ if (address & 0xFF000000)
+ return 0;
+
+ unsigned char result = (unsigned int)read8((uint32_t)address);
+
+ if (mouse_hook_enabled) {
+ if (address == CIAAPRA) {
+ if (mouse_buttons & 0x01) {
+ //mouse_buttons -= 1;
+ return (unsigned int)(result ^ 0x40);
+ }
+
+ return (unsigned int)result;
+ }
}
- address &=0xFFFFFF;
-// if (address < 0xffffff) {
- return read8((uint32_t)address);
-// }
+ if (kb_hook_enabled) {
+ if (address == CIAAICR) {
+ if (get_num_kb_queued() && (!send_keypress || send_keypress == 1)) {
+ result |= 0x08;
+ if (!send_keypress)
+ send_keypress = 1;
+ }
+ if (send_keypress == 2) {
+ //result |= 0x02;
+ send_keypress = 0;
+ }
+ return result;
+ }
+ if (address == CIAADAT) {
+ //if (send_keypress) {
+ uint8_t c = 0, t = 0;
+ pop_queued_key(&c, &t);
+ t ^= 0x01;
+ result = ((c << 1) | t) ^ 0xFF;
+ send_keypress = 2;
+ //M68K_SET_IRQ(0);
+ //}
+ return result;
+ }
+ }
-// return 1;
+ return result;
}
unsigned int m68k_read_memory_16(unsigned int address) {
- if (cfg->platform->custom_read && cfg->platform->custom_read(cfg, address, &target, OP_TYPE_WORD) != -1) {
- return target;
- }
+ PLATFORM_CHECK_READ(OP_TYPE_WORD);
- if (cfg) {
- int ret = handle_mapped_read(cfg, address, &target, OP_TYPE_WORD, ovl);
- if (ret != -1)
- return target;
- }
+ /*if (m68k_get_reg(NULL, M68K_REG_PC) >= 0x080032F0 && m68k_get_reg(NULL, M68K_REG_PC) <= 0x080032F0 + 0x4000) {
+ stop_cpu_emulation(1);
+ }*/
+
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("WORD read from DMAC @%.8X:", address);
+ uint32_t v = cdtv_dmac_read(address & 0xFFFF, OP_TYPE_WORD);
+ printf("%.2X\n", v);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
+ return v;
+ }*/
if (mouse_hook_enabled) {
if (address == JOY0DAT) {
// Forward mouse valueses to Amyga.
unsigned short result = (mouse_dy << 8) | (mouse_dx);
- mouse_dx = mouse_dy = 0;
return (unsigned int)result;
}
- if (address == CIAAPRA) {
+ /*if (address == CIAAPRA) {
unsigned short result = (unsigned int)read16((uint32_t)address);
if (mouse_buttons & 0x01) {
- mouse_buttons -= 1;
return (unsigned int)(result | 0x40);
}
else
return (unsigned int)result;
- }
+ }*/
if (address == POTGOR) {
unsigned short result = (unsigned int)read16((uint32_t)address);
- if (mouse_buttons & 0x02) {
- mouse_buttons -= 2;
- return (unsigned int)(result | 0x2);
+ // bit 1 rmb, bit 2 mmb
+ if (mouse_buttons & 0x06) {
+ return (unsigned int)((result ^ ((mouse_buttons & 0x02) << 9)) // move rmb to bit 10
+ & (result ^ ((mouse_buttons & 0x04) << 6))); // move mmb to bit 8
}
- else
- return (unsigned int)result;
+ return (unsigned int)(result & 0xfffd);
}
}
-// if (address < 0xffffff) {
- address &=0xFFFFFF;
- return (unsigned int)read16((uint32_t)address);
-// }
+ if (address & 0xFF000000)
+ return 0;
-// return 1;
+ if (address & 0x01) {
+ return ((read8(address) << 8) | read8(address + 1));
+ }
+ return (unsigned int)read16((uint32_t)address);
}
unsigned int m68k_read_memory_32(unsigned int address) {
- if (cfg->platform->custom_read && cfg->platform->custom_read(cfg, address, &target, OP_TYPE_LONGWORD) != -1) {
- return target;
+ PLATFORM_CHECK_READ(OP_TYPE_LONGWORD);
+
+ /*if (m68k_get_reg(NULL, M68K_REG_PC) >= 0x080032F0 && m68k_get_reg(NULL, M68K_REG_PC) <= 0x080032F0 + 0x4000) {
+ stop_cpu_emulation(1);
+ }*/
+
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("LONGWORD read from DMAC @%.8X:", address);
+ uint32_t v = cdtv_dmac_read(address & 0xFFFF, OP_TYPE_LONGWORD);
+ printf("%.2X\n", v);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
+ return v;
+ }*/
+
+ if (address & 0xFF000000)
+ return 0;
+
+ if (address & 0x01) {
+ uint32_t c = read8(address);
+ c |= (be16toh(read16(address+1)) << 8);
+ c |= (read8(address + 3) << 24);
+ return htobe32(c);
}
+ uint16_t a = read16(address);
+ uint16_t b = read16(address + 2);
+ return (a << 16) | b;
+}
- if (cfg) {
- int ret = handle_mapped_read(cfg, address, &target, OP_TYPE_LONGWORD, ovl);
- if (ret != -1)
- return target;
+#define PLATFORM_CHECK_WRITE(a) \
+ if (address >= cfg->custom_low && address < cfg->custom_high) { \
+ switch(cfg->platform->id) { \
+ case PLATFORM_AMIGA: { \
+ if (address >= PISCSI_OFFSET && address < PISCSI_UPPER) { \
+ handle_piscsi_write(address, value, a); \
+ } \
+ if (address >= PINET_OFFSET && address < PINET_UPPER) { \
+ handle_pinet_write(address, value, a); \
+ } \
+ if (address >= PIGFX_RTG_BASE && address < PIGFX_UPPER) { \
+ rtg_write((address & 0x0FFFFFFF), value, a); \
+ return; \
+ } \
+ if (custom_write_amiga(cfg, address, value, a) != -1) { \
+ return; \
+ } \
+ break; \
+ } \
+ default: \
+ break; \
+ } \
+ } \
+ if (address >= cfg->mapped_low && address < cfg->mapped_high) { \
+ if (handle_mapped_write(cfg, address, value, a) != -1) \
+ return; \
}
-// if (address < 0xffffff) {
- address &=0xFFFFFF;
- uint16_t a = read16(address);
- uint16_t b = read16(address + 2);
- return (a << 16) | b;
-// }
-
-// return 1;
-}
-
void m68k_write_memory_8(unsigned int address, unsigned int value) {
- if (cfg->platform->custom_write && cfg->platform->custom_write(cfg, address, value, OP_TYPE_BYTE) != -1) {
- return;
- }
+ PLATFORM_CHECK_WRITE(OP_TYPE_BYTE);
- if (cfg) {
- int ret = handle_mapped_write(cfg, address, value, OP_TYPE_BYTE, ovl);
- if (ret != -1)
- return;
- }
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("BYTE write to DMAC @%.8X: %.2X\n", address, value);
+ cdtv_dmac_write(address & 0xFFFF, value, OP_TYPE_BYTE);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
+ return;
+ }*/
if (address == 0xbfe001) {
- ovl = (value & (1 << 0));
- printf("OVL:%x\n", ovl);
+ if (ovl != (value & (1 << 0))) {
+ ovl = (value & (1 << 0));
+ printf("OVL:%x\n", ovl);
+ }
}
-// if (address < 0xffffff) {
- address &=0xFFFFFF;
- write8((uint32_t)address, value);
+ if (address & 0xFF000000)
return;
-// }
-// return;
+ write8((uint32_t)address, value);
+ return;
}
void m68k_write_memory_16(unsigned int address, unsigned int value) {
- if (cfg->platform->custom_write && cfg->platform->custom_write(cfg, address, value, OP_TYPE_WORD) != -1) {
- return;
- }
+ PLATFORM_CHECK_WRITE(OP_TYPE_WORD);
- if (cfg) {
- int ret = handle_mapped_write(cfg, address, value, OP_TYPE_WORD, ovl);
- if (ret != -1)
- return;
- }
-
-// if (address < 0xffffff) {
- address &=0xFFFFFF;
- write16((uint32_t)address, value);
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("WORD write to DMAC @%.8X: %.4X\n", address, value);
+ cdtv_dmac_write(address & 0xFFFF, value, OP_TYPE_WORD);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
return;
-// }
-// return;
-}
+ }*/
-void m68k_write_memory_32(unsigned int address, unsigned int value) {
- if (cfg->platform->custom_write && cfg->platform->custom_write(cfg, address, value, OP_TYPE_LONGWORD) != -1) {
- return;
+ if (address == 0xDFF030) {
+ char *serdat = (char *)&value;
+ // SERDAT word. see amiga dev docs appendix a; upper byte is control codes, and bit 0 is always 1.
+ // ignore this upper byte as it's not viewable data, only display lower byte.
+ printf("%c", serdat[0]);
}
-
- if (cfg) {
- int ret = handle_mapped_write(cfg, address, value, OP_TYPE_LONGWORD, ovl);
- if (ret != -1)
- return;
+ if (address == 0xDFF09A) {
+ if (!(value & 0x8000)) {
+ if (value & 0x04) {
+ int2_enabled = 0;
+ }
+ }
+ else if (value & 0x04) {
+ int2_enabled = 1;
+ }
}
-// if (address < 0xffffff) {
- address &=0xFFFFFF;
- write16(address, value >> 16);
- write16(address + 2, value);
+ if (address & 0xFF000000)
return;
-// }
-// return;
-}
+ if (address & 0x01)
+ printf("Unaligned WORD write!\n");
-void write16(uint32_t address, uint32_t data) {
- uint32_t addr_h_s = (address & 0x0000ffff) << 8;
- uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
- uint32_t addr_l_s = (address >> 16) << 8;
- uint32_t addr_l_r = (~address >> 16) << 8;
- uint32_t data_s = (data & 0x0000ffff) << 8;
- uint32_t data_r = (~data & 0x0000ffff) << 8;
-
- // asm volatile ("dmb" ::: "memory");
- W16
- *(gpio) = gpfsel0_o;
- *(gpio + 1) = gpfsel1_o;
- *(gpio + 2) = gpfsel2_o;
-
- *(gpio + 7) = addr_h_s;
- *(gpio + 10) = addr_h_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio + 7) = addr_l_s;
- *(gpio + 10) = addr_l_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- // write phase
- *(gpio + 7) = data_s;
- *(gpio + 10) = data_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
- while ((GET_GPIO(0)))
- ;
- // asm volatile ("dmb" ::: "memory");
+ write16((uint32_t)address, value);
+ return;
}
-void write8(uint32_t address, uint32_t data) {
- if ((address & 1) == 0)
- data = data + (data << 8); // EVEN, A0=0,UDS
- else
- data = data & 0xff; // ODD , A0=1,LDS
- uint32_t addr_h_s = (address & 0x0000ffff) << 8;
- uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
- uint32_t addr_l_s = (address >> 16) << 8;
- uint32_t addr_l_r = (~address >> 16) << 8;
- uint32_t data_s = (data & 0x0000ffff) << 8;
- uint32_t data_r = (~data & 0x0000ffff) << 8;
-
- // asm volatile ("dmb" ::: "memory");
- W8
- *(gpio) = gpfsel0_o;
- *(gpio + 1) = gpfsel1_o;
- *(gpio + 2) = gpfsel2_o;
-
- *(gpio + 7) = addr_h_s;
- *(gpio + 10) = addr_h_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio + 7) = addr_l_s;
- *(gpio + 10) = addr_l_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- // write phase
- *(gpio + 7) = data_s;
- *(gpio + 10) = data_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
- while ((GET_GPIO(0)))
- ;
- // asm volatile ("dmb" ::: "memory");
-}
+void m68k_write_memory_32(unsigned int address, unsigned int value) {
+ PLATFORM_CHECK_WRITE(OP_TYPE_LONGWORD);
-uint32_t read16(uint32_t address) {
- volatile int val;
- uint32_t addr_h_s = (address & 0x0000ffff) << 8;
- uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
- uint32_t addr_l_s = (address >> 16) << 8;
- uint32_t addr_l_r = (~address >> 16) << 8;
-
- // asm volatile ("dmb" ::: "memory");
- R16
- *(gpio) = gpfsel0_o;
- *(gpio + 1) = gpfsel1_o;
- *(gpio + 2) = gpfsel2_o;
-
- *(gpio + 7) = addr_h_s;
- *(gpio + 10) = addr_h_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio + 7) = addr_l_s;
- *(gpio + 10) = addr_l_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- // read phase
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
- GPIO_CLR = 1 << 6;
- while (!(GET_GPIO(0)))
- ;
- GPIO_CLR = 1 << 6;
- val = *(gpio + 13);
- GPIO_SET = 1 << 6;
- // asm volatile ("dmb" ::: "memory");
- return (val >> 8) & 0xffff;
-}
+ /*if (address >= 0xE90000 && address < 0xF00000) {
+ printf("LONGWORD write to DMAC @%.8X: %.8X\n", address, value);
+ cdtv_dmac_write(address & 0xFFFF, value, OP_TYPE_LONGWORD);
+ M68K_END_TIMESLICE;
+ cpu_emulation_running = 0;
+ return;
+ }*/
-uint32_t read8(uint32_t address) {
- int val;
- uint32_t addr_h_s = (address & 0x0000ffff) << 8;
- uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
- uint32_t addr_l_s = (address >> 16) << 8;
- uint32_t addr_l_r = (~address >> 16) << 8;
-
- // asm volatile ("dmb" ::: "memory");
- R8
- *(gpio) = gpfsel0_o;
- *(gpio + 1) = gpfsel1_o;
- *(gpio + 2) = gpfsel2_o;
-
- *(gpio + 7) = addr_h_s;
- *(gpio + 10) = addr_h_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- *(gpio + 7) = addr_l_s;
- *(gpio + 10) = addr_l_r;
- GPIO_CLR = 1 << 7;
- GPIO_SET = 1 << 7;
-
- // read phase
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
-
- GPIO_CLR = 1 << 6;
- while (!(GET_GPIO(0)))
- ;
- GPIO_CLR = 1 << 6;
- val = *(gpio + 13);
- GPIO_SET = 1 << 6;
- // asm volatile ("dmb" ::: "memory");
-
- val = (val >> 8) & 0xffff;
- if ((address & 1) == 0)
- return (val >> 8) & 0xff; // EVEN, A0=0,UDS
- else
- return val & 0xff; // ODD , A0=1,LDS
-}
+ if (address & 0xFF000000)
+ return;
-/******************************************************/
-
-void write_reg(unsigned int value) {
- STATUSREGADDR
- *(gpio) = gpfsel0_o;
- *(gpio + 1) = gpfsel1_o;
- *(gpio + 2) = gpfsel2_o;
- *(gpio + 7) = (value & 0xffff) << 8;
- *(gpio + 10) = (~value & 0xffff) << 8;
- GPIO_CLR = 1 << 7;
- GPIO_CLR = 1 << 7; // delay
- GPIO_SET = 1 << 7;
- GPIO_SET = 1 << 7;
- // Bus HIGH-Z
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
-}
+ if (address & 0x01)
+ printf("Unaligned LONGWORD write!\n");
-uint16_t read_reg(void) {
- uint32_t val;
- STATUSREGADDR
- // Bus HIGH-Z
- *(gpio) = gpfsel0;
- *(gpio + 1) = gpfsel1;
- *(gpio + 2) = gpfsel2;
- GPIO_CLR = 1 << 6;
- GPIO_CLR = 1 << 6; // delay
- GPIO_CLR = 1 << 6;
- GPIO_CLR = 1 << 6;
- val = *(gpio + 13);
- GPIO_SET = 1 << 6;
- return (uint16_t)(val >> 8);
+ write16(address, value >> 16);
+ write16(address + 2, value);
+ return;
}
-
-//
-// Set up a memory regions to access GPIO
-//
-void setup_io() {
- /* open /dev/mem */
- if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
- printf("can't open /dev/mem \n");
- exit(-1);
- }
-
- /* mmap GPIO */
- gpio_map = mmap(
- NULL, // Any adddress in our space will do
- BCM2708_PERI_SIZE, // Map length
- PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
- MAP_SHARED, // Shared with other processes
- mem_fd, // File to map
- BCM2708_PERI_BASE // Offset to GPIO peripheral
- );
-
- close(mem_fd); // No need to keep mem_fd open after mmap
-
- if (gpio_map == MAP_FAILED) {
- printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
- exit(-1);
- }
-
- gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
- gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;
-
-} // setup_io
-//
-// BCM283x SMI interface
-// Derived from Documentation
-// GVL 15-Oct-2014
-//
-#ifndef MAIN__HEADER
-#define MAIN__HEADER
+/**
+ * pistorm
+ * emulator function declarations
+ */
+#ifndef _EMULATOR_H
+#define _EMULATOR_H
+
+// see feature_set_macros(7)
+#define _GNU_SOURCE
#include <stdint.h>
-void setup_io();
-void restore_io();
-int set_pio_timing(int p);
/*
void write16(uint32_t address,uint16_t data);
uint16_t read16(uint32_t address);
uint16_t read8(uint32_t address);
*/
-
void cpu_pulse_reset(void);
void m68ki_int_ack(uint8_t int_level);
int cpu_irq_ack(int level);
void m68k_write_memory_16(unsigned int address, unsigned int value);
void m68k_write_memory_32(unsigned int address, unsigned int value);
-
-
-#endif /* MAIN__HEADER */
-
+#endif /* _EMULATOR_H */
--- /dev/null
+#include <stdint.h>
+#include <stddef.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/ioctl.h>
+#include "m68k.h"
+#include "platforms/amiga/Gayle.h"
+#include "platforms/amiga/gayle-ide/ide.h"
+#include "gpio_old.h"
+
+// I/O access
+volatile unsigned int *gpio;
+volatile unsigned int *gpclk;
+volatile unsigned int gpfsel0;
+volatile unsigned int gpfsel1;
+volatile unsigned int gpfsel2;
+volatile unsigned int gpfsel0_o;
+volatile unsigned int gpfsel1_o;
+volatile unsigned int gpfsel2_o;
+
+volatile uint16_t srdata;
+volatile uint32_t srdata2;
+volatile uint32_t srdata2_old;
+
+extern int mem_fd, mouse_fd, keyboard_fd;
+extern int mem_fd_gpclk;
+extern uint8_t gayle_int;
+
+void *gpio_map;
+void *gpclk_map;
+
+unsigned char toggle;
+
+static int g = 0;
+
+inline void write16(uint32_t address, uint32_t data) {
+ // asm volatile ("dmb" ::: "memory");
+ W16
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = ((address & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~address & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = ((address >> 16) << 8);
+ *(gpio + 10) = ((~address >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // write phase
+ *(gpio + 7) = ((data & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~data & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ while ((GET_GPIO(0)))
+ ;
+ // asm volatile ("dmb" ::: "memory");
+}
+
+inline void write8(uint32_t address, uint32_t data) {
+ if ((address & 1) == 0)
+ data = data + (data << 8); // EVEN, A0=0,UDS
+ else
+ data = data & 0xff; // ODD , A0=1,LDS
+
+ // asm volatile ("dmb" ::: "memory");
+ W8
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = ((address & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~address & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = ((address >> 16) << 8);
+ *(gpio + 10) = ((~address >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // write phase
+ *(gpio + 7) = ((data & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~data & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ while ((GET_GPIO(0)))
+ ;
+ // asm volatile ("dmb" ::: "memory");
+}
+
+inline uint32_t read32(uint32_t address) {
+ int val;
+ int a;
+ int b;
+ asm volatile ("dmb" ::: "memory");
+ R16
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = ((address & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~address & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = ((address >> 16) << 8);
+ *(gpio + 10) = ((~address >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // read phase
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ GPIO_CLR = 1 << 6;
+ while (!(GET_GPIO(0)))
+ ;
+ GPIO_CLR = 1 << 6;
+ GPIO_CLR = 1 << 6;
+ val = *(gpio + 13);
+ GPIO_SET = 1 << 6;
+ // asm volatile ("dmb" ::: "memory");
+ a = (val >> 8) & 0xffff;
+ while (GET_GPIO(0));
+ //R16
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = (((address+2) & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~(address+2) & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = (((address+2) >> 16) << 8);
+ *(gpio + 10) = ((~(address+2) >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // read phase
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ GPIO_CLR = 1 << 6;
+ while (!(GET_GPIO(0)))
+ ;
+ GPIO_CLR = 1 << 6;
+ GPIO_CLR = 1 << 6;
+ val = *(gpio + 13);
+ GPIO_SET = 1 << 6;
+ b = (val >> 8) & 0xffff;
+ asm volatile ("dmb" ::: "memory");
+
+ return (a << 16) | b;
+}
+
+inline uint32_t read16(uint32_t address) {
+ int val;
+ // asm volatile ("dmb" ::: "memory");
+ R16
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = ((address & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~address & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = ((address >> 16) << 8);
+ *(gpio + 10) = ((~address >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // read phase
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ GPIO_CLR = 1 << 6;
+ while (!(GET_GPIO(0)))
+ ;
+ GPIO_CLR = 1 << 6;
+ val = *(gpio + 13);
+ GPIO_SET = 1 << 6;
+ // asm volatile ("dmb" ::: "memory");
+ return (val >> 8) & 0xffff;
+}
+
+inline uint32_t read8(uint32_t address) {
+ int val;
+ // asm volatile ("dmb" ::: "memory");
+ R8
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+
+ *(gpio + 7) = ((address & 0x0000ffff) << 8);
+ *(gpio + 10) = ((~address & 0x0000ffff) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ *(gpio + 7) = ((address >> 16) << 8);
+ *(gpio + 10) = ((~address >> 16) << 8);
+ GPIO_CLR = 1 << 7;
+ GPIO_SET = 1 << 7;
+
+ // read phase
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+
+ GPIO_CLR = 1 << 6;
+ while (!(GET_GPIO(0)))
+ ;
+ GPIO_CLR = 1 << 6;
+ val = *(gpio + 13);
+ GPIO_SET = 1 << 6;
+ // asm volatile ("dmb" ::: "memory");
+
+ val = (val >> 8) & 0xffff;
+ if ((address & 1) == 0)
+ return (val >> 8) & 0xff; // EVEN, A0=0,UDS
+ else
+ return val & 0xff; // ODD , A0=1,LDS
+}
+
+/******************************************************/
+
+void write_reg(unsigned int value) {
+ STATUSREGADDR
+ *(gpio) = gpfsel0_o;
+ *(gpio + 1) = gpfsel1_o;
+ *(gpio + 2) = gpfsel2_o;
+ *(gpio + 7) = (value & 0xffff) << 8;
+ *(gpio + 10) = (~value & 0xffff) << 8;
+ GPIO_CLR = 1 << 7;
+ GPIO_CLR = 1 << 7; // delay
+ GPIO_SET = 1 << 7;
+ GPIO_SET = 1 << 7;
+ // Bus HIGH-Z
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+}
+
+uint16_t read_reg(void) {
+ uint32_t val;
+ STATUSREGADDR
+ // Bus HIGH-Z
+ *(gpio) = gpfsel0;
+ *(gpio + 1) = gpfsel1;
+ *(gpio + 2) = gpfsel2;
+ GPIO_CLR = 1 << 6;
+ GPIO_CLR = 1 << 6; // delay
+ GPIO_CLR = 1 << 6;
+ GPIO_CLR = 1 << 6;
+ val = *(gpio + 13);
+ GPIO_SET = 1 << 6;
+ return (uint16_t)(val >> 8);
+}
+
+//
+// Set up a memory regions to access GPIO
+//
+void setup_io() {
+ /* open /dev/mem */
+ if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
+ printf("can't open /dev/mem \n");
+ exit(-1);
+ }
+
+ /* mmap GPIO */
+ gpio_map = mmap(
+ NULL, // Any adddress in our space will do
+ BCM2708_PERI_SIZE, // Map length
+ PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
+ MAP_SHARED, // Shared with other processes
+ mem_fd, // File to map
+ BCM2708_PERI_BASE // Offset to GPIO peripheral
+ );
+
+ close(mem_fd); // No need to keep mem_fd open after mmap
+
+ if (gpio_map == MAP_FAILED) {
+ printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
+ exit(-1);
+ }
+
+ gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
+ gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;
+
+} // setup_io
+
+void gpio_enable_200mhz() {
+ *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
+ usleep(10);
+ while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
+ ;
+ usleep(100);
+ *(gpclk + (CLK_GP0_DIV / 4)) =
+ CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
+ usleep(10);
+ *(gpclk + (CLK_GP0_CTL / 4)) =
+ CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
+ usleep(10);
+ while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
+ ;
+ usleep(100);
+
+ SET_GPIO_ALT(4, 0); // gpclk0
+
+ // set SA to output
+ INP_GPIO(2);
+ OUT_GPIO(2);
+ INP_GPIO(3);
+ OUT_GPIO(3);
+ INP_GPIO(5);
+ OUT_GPIO(5);
+
+ // set gpio0 (aux0) and gpio1 (aux1) to input
+ INP_GPIO(0);
+ INP_GPIO(1);
+
+ // Set GPIO pins 6,7 and 8-23 to output
+ for (g = 6; g <= 23; g++) {
+ INP_GPIO(g);
+ OUT_GPIO(g);
+ }
+ printf("Precalculate GPIO8-23 as Output\n");
+ gpfsel0_o = *(gpio); // store gpio ddr
+ printf("gpfsel0: %#x\n", gpfsel0_o);
+ gpfsel1_o = *(gpio + 1); // store gpio ddr
+ printf("gpfsel1: %#x\n", gpfsel1_o);
+ gpfsel2_o = *(gpio + 2); // store gpio ddr
+ printf("gpfsel2: %#x\n", gpfsel2_o);
+
+ // Set GPIO pins 8-23 to input
+ for (g = 8; g <= 23; g++) {
+ INP_GPIO(g);
+ }
+ printf("Precalculate GPIO8-23 as Input\n");
+ gpfsel0 = *(gpio); // store gpio ddr
+ printf("gpfsel0: %#x\n", gpfsel0);
+ gpfsel1 = *(gpio + 1); // store gpio ddr
+ printf("gpfsel1: %#x\n", gpfsel1);
+ gpfsel2 = *(gpio + 2); // store gpio ddr
+ printf("gpfsel2: %#x\n", gpfsel2);
+
+ GPIO_CLR = 1 << 2;
+ GPIO_CLR = 1 << 3;
+ GPIO_SET = 1 << 5;
+
+ GPIO_SET = 1 << 6;
+ GPIO_SET = 1 << 7;
+}
+
+inline void gpio_handle_irq() {
+ if (GET_GPIO(1) == 0) {
+ srdata = read_reg();
+ m68k_set_irq((srdata >> 13) & 0xff);
+ } else {
+ if ((gayle_int & 0x80) && (get_ide(0)->drive[0].intrq || get_ide(0)->drive[1].intrq)) {
+ write16(0xdff09c, 0x8008);
+ m68k_set_irq(2);
+ }
+ else
+ m68k_set_irq(0);
+ };
+}
+
+inline int gpio_get_irq() {
+ return (GET_GPIO(1));
+}
--- /dev/null
+//#define BCM2708_PERI_BASE 0x20000000 //pi0-1
+//#define BCM2708_PERI_BASE 0xFE000000 //pi4
+#define BCM2708_PERI_BASE 0x3F000000 // pi3
+#define BCM2708_PERI_SIZE 0x01000000
+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
+#define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
+#define GPIO_ADDR 0x200000 /* GPIO controller */
+#define GPCLK_ADDR 0x101000
+#define CLK_PASSWD 0x5a000000
+#define CLK_GP0_CTL 0x070
+#define CLK_GP0_DIV 0x074
+
+#define SA0 5
+#define SA1 3
+#define SA2 2
+
+#define STATUSREGADDR \
+ GPIO_CLR = 1 << SA0; \
+ GPIO_CLR = 1 << SA1; \
+ GPIO_SET = 1 << SA2;
+#define W16 \
+ GPIO_CLR = 1 << SA0; \
+ GPIO_CLR = 1 << SA1; \
+ GPIO_CLR = 1 << SA2;
+#define R16 \
+ GPIO_SET = 1 << SA0; \
+ GPIO_CLR = 1 << SA1; \
+ GPIO_CLR = 1 << SA2;
+#define W8 \
+ GPIO_CLR = 1 << SA0; \
+ GPIO_SET = 1 << SA1; \
+ GPIO_CLR = 1 << SA2;
+#define R8 \
+ GPIO_SET = 1 << SA0; \
+ GPIO_SET = 1 << SA1; \
+ GPIO_CLR = 1 << SA2;
+
+#define PAGE_SIZE (4 * 1024)
+#define BLOCK_SIZE (4 * 1024)
+
+#define GPIOSET(no, ishigh) \
+ do { \
+ if (ishigh) \
+ set |= (1 << (no)); \
+ else \
+ reset |= (1 << (no)); \
+ } while (0)
+
+// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
+// SET_GPIO_ALT(x,y)
+#define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
+#define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
+#define SET_GPIO_ALT(g, a) \
+ *(gpio + (((g) / 10))) |= \
+ (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
+
+#define GPIO_SET \
+ *(gpio + 7) // sets bits which are 1 ignores bits which are 0
+#define GPIO_CLR \
+ *(gpio + 10) // clears bits which are 1 ignores bits which are 0
+
+#define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
+
+#define GPIO_PULL *(gpio + 37) // Pull up/pull down
+#define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
+
+#define GPIO_HANDLE_IRQ \
+ if (GET_GPIO(1) == 0) { \
+ srdata = read_reg(); \
+ m68k_set_irq((srdata >> 13) & 0xff); \
+ } else { \
+ if ((gayle_int & 0x80) && (get_ide(0)->drive[0].intrq || get_ide(0)->drive[1].intrq)) { \
+ write16(0xdff09c, 0x8008); \
+ m68k_set_irq(2); \
+ } \
+ else \
+ m68k_set_irq(0); \
+ };
+
+void setup_io();
+void gpio_enable_200mhz();
+void gpio_handle_irq();
+
+int gpio_get_irq();
+
+uint32_t read8(uint32_t address);
+void write8(uint32_t address, uint32_t data);
+
+uint32_t read16(uint32_t address);
+void write16(uint32_t address, uint32_t data);
+
+void write32(uint32_t address, uint32_t data);
+uint32_t read32(uint32_t address);
+
+uint16_t read_reg(void);
+void write_reg(unsigned int value);
--- /dev/null
+/*
+ Original Copyright 2020 Claude Schwarz
+ Code reorganized and rewritten by
+ Niklas Ekström 2021 (https://github.com/niklasekstrom)
+*/
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "ps_protocol.h"
+#include "m68k.h"
+
+volatile unsigned int *gpio;
+volatile unsigned int *gpclk;
+
+unsigned int gpfsel0;
+unsigned int gpfsel1;
+unsigned int gpfsel2;
+
+unsigned int gpfsel0_o;
+unsigned int gpfsel1_o;
+unsigned int gpfsel2_o;
+
+static void setup_io() {
+ int fd = open("/dev/mem", O_RDWR | O_SYNC);
+ if (fd < 0) {
+ printf("Unable to open /dev/mem. Run as root using sudo?\n");
+ exit(-1);
+ }
+
+ void *gpio_map = mmap(
+ NULL, // Any adddress in our space will do
+ BCM2708_PERI_SIZE, // Map length
+ PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
+ MAP_SHARED, // Shared with other processes
+ fd, // File to map
+ BCM2708_PERI_BASE // Offset to GPIO peripheral
+ );
+
+ close(fd);
+
+ if (gpio_map == MAP_FAILED) {
+ printf("mmap failed, errno = %d\n", errno);
+ exit(-1);
+ }
+
+ gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
+ gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;
+}
+
+static void setup_gpclk() {
+ // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
+ // on pi model
+ *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
+ usleep(10);
+ while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
+ ;
+ usleep(100);
+ *(gpclk + (CLK_GP0_DIV / 4)) =
+ CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
+ usleep(10);
+ *(gpclk + (CLK_GP0_CTL / 4)) =
+ CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
+ usleep(10);
+ while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
+ ;
+ usleep(100);
+
+ SET_GPIO_ALT(PIN_CLK, 0); // gpclk0
+}
+
+void ps_setup_protocol() {
+ setup_io();
+ setup_gpclk();
+
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+}
+
+void ps_write_16(unsigned int address, unsigned int data) {
+ *(gpio + 0) = GPFSEL0_OUTPUT;
+ *(gpio + 1) = GPFSEL1_OUTPUT;
+ *(gpio + 2) = GPFSEL2_OUTPUT;
+
+ *(gpio + 7) = ((data & 0xffff) << 8) | (REG_DATA << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((0x0000 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+
+ while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS))
+ ;
+}
+
+void ps_write_8(unsigned int address, unsigned int data) {
+ if ((address & 1) == 0)
+ data = data + (data << 8); // EVEN, A0=0,UDS
+ else
+ data = data & 0xff; // ODD , A0=1,LDS
+
+ *(gpio + 0) = GPFSEL0_OUTPUT;
+ *(gpio + 1) = GPFSEL1_OUTPUT;
+ *(gpio + 2) = GPFSEL2_OUTPUT;
+
+ *(gpio + 7) = ((data & 0xffff) << 8) | (REG_DATA << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((0x0100 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+
+ while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS))
+ ;
+}
+
+void ps_write_32(unsigned int address, unsigned int value) {
+ ps_write_16(address, value >> 16);
+ ps_write_16(address + 2, value);
+}
+
+unsigned int ps_read_16(unsigned int address) {
+ *(gpio + 0) = GPFSEL0_OUTPUT;
+ *(gpio + 1) = GPFSEL1_OUTPUT;
+ *(gpio + 2) = GPFSEL2_OUTPUT;
+
+ *(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((0x0200 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+
+ *(gpio + 7) = (REG_DATA << PIN_A0);
+ *(gpio + 7) = 1 << PIN_RD;
+
+ while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS))
+ ;
+
+ unsigned int value = *(gpio + 13);
+
+ *(gpio + 10) = 0xffffec;
+
+ return (value >> 8) & 0xffff;
+}
+
+unsigned int ps_read_8(unsigned int address) {
+ *(gpio + 0) = GPFSEL0_OUTPUT;
+ *(gpio + 1) = GPFSEL1_OUTPUT;
+ *(gpio + 2) = GPFSEL2_OUTPUT;
+
+ *(gpio + 7) = ((address & 0xffff) << 8) | (REG_ADDR_LO << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 7) = ((0x0300 | (address >> 16)) << 8) | (REG_ADDR_HI << PIN_A0);
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+
+ *(gpio + 7) = (REG_DATA << PIN_A0);
+ *(gpio + 7) = 1 << PIN_RD;
+
+ while (*(gpio + 13) & (1 << PIN_TXN_IN_PROGRESS))
+ ;
+
+ unsigned int value = *(gpio + 13);
+
+ *(gpio + 10) = 0xffffec;
+
+ value = (value >> 8) & 0xffff;
+
+ if ((address & 1) == 0)
+ return (value >> 8) & 0xff; // EVEN, A0=0,UDS
+ else
+ return value & 0xff; // ODD , A0=1,LDS
+}
+
+unsigned int ps_read_32(unsigned int address) {
+ unsigned int a = ps_read_16(address);
+ unsigned int b = ps_read_16(address + 2);
+ return (a << 16) | b;
+}
+
+void ps_write_status_reg(unsigned int value) {
+ *(gpio + 0) = GPFSEL0_OUTPUT;
+ *(gpio + 1) = GPFSEL1_OUTPUT;
+ *(gpio + 2) = GPFSEL2_OUTPUT;
+
+ *(gpio + 7) = ((value & 0xffff) << 8) | (REG_STATUS << PIN_A0);
+
+ *(gpio + 7) = 1 << PIN_WR;
+ *(gpio + 7) = 1 << PIN_WR; // delay
+ *(gpio + 10) = 1 << PIN_WR;
+ *(gpio + 10) = 0xffffec;
+
+ *(gpio + 0) = GPFSEL0_INPUT;
+ *(gpio + 1) = GPFSEL1_INPUT;
+ *(gpio + 2) = GPFSEL2_INPUT;
+}
+
+unsigned int ps_read_status_reg() {
+ *(gpio + 7) = (REG_STATUS << PIN_A0);
+ *(gpio + 7) = 1 << PIN_RD;
+ *(gpio + 7) = 1 << PIN_RD;
+ *(gpio + 7) = 1 << PIN_RD;
+ *(gpio + 7) = 1 << PIN_RD;
+
+ unsigned int value = *(gpio + 13);
+
+ *(gpio + 10) = 0xffffec;
+
+ return (value >> 8) & 0xffff;
+}
+
+void ps_reset_state_machine() {
+ ps_write_status_reg(STATUS_BIT_INIT);
+ usleep(1500);
+ ps_write_status_reg(0);
+ usleep(100);
+}
+
+void ps_pulse_reset() {
+ ps_write_status_reg(0);
+ usleep(100000);
+ ps_write_status_reg(STATUS_BIT_RESET);
+}
+
+unsigned int ps_get_ipl_zero() {
+ unsigned int value = *(gpio + 13);
+ return value & (1 << PIN_IPL_ZERO);
+}
+
+#define INT2_ENABLED 1
+
+void ps_update_irq() {
+ unsigned int ipl = 0;
+
+ if (!ps_get_ipl_zero()) {
+ unsigned int status = ps_read_status_reg();
+ ipl = (status & 0xe000) >> 13;
+ }
+
+ /*if (ipl < 2 && INT2_ENABLED && emu_int2_req()) {
+ ipl = 2;
+ }*/
+
+ m68k_set_irq(ipl);
+}
--- /dev/null
+/*
+ Code reorganized and rewritten by
+ Niklas Ekström 2021 (https://github.com/niklasekstrom)
+*/
+
+#ifndef _PS_PROTOCOL_H
+#define _PS_PROTOCOL_H
+
+#define PIN_TXN_IN_PROGRESS 0
+#define PIN_IPL_ZERO 1
+#define PIN_A0 2
+#define PIN_A1 3
+#define PIN_CLK 4
+#define PIN_UNUSED 5
+#define PIN_RD 6
+#define PIN_WR 7
+#define PIN_D(x) (8 + x)
+
+#define REG_DATA 0
+#define REG_ADDR_LO 1
+#define REG_ADDR_HI 2
+#define REG_STATUS 3
+
+#define STATUS_BIT_INIT 1
+#define STATUS_BIT_RESET 2
+
+#define STATUS_MASK_IPL 0xe000
+#define STATUS_SHIFT_IPL 13
+
+//#define BCM2708_PERI_BASE 0x20000000 // pi0-1
+//#define BCM2708_PERI_BASE 0xFE000000 // pi4
+#define BCM2708_PERI_BASE 0x3F000000 // pi3
+#define BCM2708_PERI_SIZE 0x01000000
+
+#define GPIO_ADDR 0x200000 /* GPIO controller */
+#define GPCLK_ADDR 0x101000
+
+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
+#define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
+
+#define CLK_PASSWD 0x5a000000
+#define CLK_GP0_CTL 0x070
+#define CLK_GP0_DIV 0x074
+
+// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
+// SET_GPIO_ALT(x,y)
+#define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
+#define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
+#define SET_GPIO_ALT(g, a) \
+ *(gpio + (((g) / 10))) |= \
+ (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
+
+#define GPIO_PULL *(gpio + 37) // Pull up/pull down
+#define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
+
+#define GPFSEL0_INPUT 0x0024c240
+#define GPFSEL1_INPUT 0x00000000
+#define GPFSEL2_INPUT 0x00000000
+
+#define GPFSEL0_OUTPUT 0x0924c240
+#define GPFSEL1_OUTPUT 0x09249249
+#define GPFSEL2_OUTPUT 0x00000249
+
+unsigned int ps_read_8(unsigned int address);
+unsigned int ps_read_16(unsigned int address);
+unsigned int ps_read_32(unsigned int address);
+
+void ps_write_8(unsigned int address, unsigned int data);
+void ps_write_16(unsigned int address, unsigned int data);
+void ps_write_32(unsigned int address, unsigned int data);
+
+unsigned int ps_read_status_reg();
+void ps_write_status_reg(unsigned int value);
+
+void ps_setup_protocol();
+void ps_reset_state_machine();
+void ps_pulse_reset();
+
+unsigned int ps_get_ipl_zero();
+
+#define read8 ps_read_8
+#define read16 ps_read_16
+#define read32 ps_read_32
+
+#define write8 ps_write_8
+#define write16 ps_write_16
+#define write32 ps_write_32
+
+#define write_reg ps_write_status_reg
+#define read_reg ps_read_status_reg
+
+#define gpio_get_irq ps_get_ipl_zero
+
+#endif /* _PS_PROTOCOL_H */
+#include <linux/input.h>
+#include <pthread.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
#include <termios.h>
#include <unistd.h>
-#include <linux/input.h>
+
+#include "platforms/platforms.h"
+#include "input.h"
+
+#define NONE 0x80
static int lshift = 0, rshift = 0, lctrl = 0, rctrl = 0, lalt = 0, altgr = 0;
extern int mouse_fd;
extern int keyboard_fd;
-enum keypress_type {
- KEYPRESS_RELEASE,
- KEYPRESS_PRESS,
- KEYPRESS_REPEAT,
+// n.b. $fe and $ff are mapped to newmouse standard wheel up/down keycodes, nonexistant on amiga keyboards
+char keymap_amiga[256] = {
+/* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F */
+/*00*/ 0x80, 0x45, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x41, 0x42,
+/*10*/ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x44, 0x63, 0x20, 0x21,
+/*20*/ 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x00, 0x60, 0x2B, 0x31, 0x32, 0x33, 0x34,
+/*30*/ 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x61, 0x5D, 0x64, 0x40, NONE, 0x50, 0x51, 0x52, 0x53, 0x54,
+/*40*/ 0x55, 0x56, 0x57, 0x58, 0x69, 0x5B, NONE, 0x3D, 0x3E, 0x3F, 0x4A, 0x2D, 0x2E, 0x2F, 0x4E, 0x1D,
+/*50*/ 0x1E, 0x1F, 0x0F, 0x3C, NONE, NONE, 0x30, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*60*/ 0x43, NONE, 0x5C, NONE, NONE, NONE, 0x5F, 0x4C, 0x5A, 0x4F, 0x4E, NONE, 0x4D, NONE, 0x0D, 0x46,
+/*70*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, 0x66, 0x67, 0x67,
+/*80*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*90*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*A0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*B0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*C0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*D0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*E0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
+/*F0*/ NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, 0x7A, 0x7B,
};
int handle_modifier(struct input_event *ev) {
#define KEYCASE(a, b, c)case a: return (lshift || rshift) ? c : b;
+/**
+ * translates keycodes back into a simpler enumerable value for handling emulator command events
+ *
+ * @param *struct/input_event ev pointer to input layer event structure
+ * @return char
+ */
char char_from_input_event(struct input_event *ev) {
switch(ev->code) {
KEYCASE(KEY_A, 'a', 'A');
KEYCASE(KEY_9, '9', '(');
KEYCASE(KEY_0, '0', ')');
KEYCASE(KEY_F12, 0x1B, 0x1B);
+ KEYCASE(KEY_PAUSE, 0x01, 0x01);
default:
return 0;
}
}
-int get_key_char(char *c)
+int get_key_char(char *c, char *code, char *event_type)
{
if (keyboard_fd == -1)
return 0;
struct input_event ie;
while(read(keyboard_fd, &ie, sizeof(struct input_event)) != -1) {
if (ie.type == EV_KEY) {
- if (handle_modifier(&ie))
- continue;
+ handle_modifier(&ie);
char ret = char_from_input_event(&ie);
- if (ret != 0) {
- *c = ret;
- return 1;
- }
+ *c = ret;
+ *code = ie.code;
+ *event_type = ie.value;
+ return 1;
}
}
return 0;
}
-int get_mouse_status(char *x, char *y, char *b) {
- struct input_event ie;
- if (read(mouse_fd, &ie, sizeof(struct input_event)) != -1) {
- *b = ((char *)&ie)[0];
- *x = ((char *)&ie)[1];
- *y = ((char *)&ie)[2];
+uint8_t mouse_x = 0, mouse_y = 0;
+
+int get_mouse_status(uint8_t *x, uint8_t *y, uint8_t *b, uint8_t *e) {
+ uint8_t mouse_ev[4];
+ if (read(mouse_fd, &mouse_ev, 4) != -1) {
+ *b = ((uint8_t *)&mouse_ev)[0];
+ *e = ((uint8_t *)&mouse_ev)[3];
+
+ mouse_x += ((uint8_t *)&mouse_ev)[1];
+ *x = mouse_x;
+ mouse_y += (-((uint8_t *)&mouse_ev)[2]);
+ *y = mouse_y;
return 1;
}
return 0;
}
+
+static uint8_t queued_keypresses = 0, queue_output_pos = 0, queue_input_pos = 0;
+static uint8_t queued_keys[256];
+static uint8_t queued_events[256];
+
+void clear_keypress_queue() {
+ memset(queued_keys, 0x80, 256);
+ memset(queued_events, 0x80, 256);
+ queued_keypresses = 0;
+ queue_output_pos = 0;
+ queue_input_pos = 0;
+}
+
+int queue_keypress(uint8_t keycode, uint8_t event_type, uint8_t platform) {
+ char *keymap = NULL;
+ switch (platform) {
+ case PLATFORM_AMIGA:
+ if (event_type != KEYPRESS_REPEAT)
+ keymap = keymap_amiga;
+ break;
+ default:
+ break;
+ }
+ if (keymap != NULL) {
+ if (keymap[keycode] != NONE) {
+ if (queued_keypresses < 255) {
+ // printf("Keypress queued, matched %.2X to host key code %.2X\n", keycode, keymap[keycode]);
+ queued_keys[queue_output_pos] = keymap[keycode];
+ queued_events[queue_output_pos] = event_type;
+ queue_output_pos++;
+ queued_keypresses++;
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+int get_num_kb_queued() {
+ return queued_keypresses;
+}
+
+void pop_queued_key(uint8_t *c, uint8_t *t) {
+ if (queued_keypresses == 0) {
+ *c = NONE;
+ *t = NONE;
+ return;
+ }
+ *c = queued_keys[queue_input_pos];
+ *t = queued_events[queue_input_pos];
+ queue_input_pos++;
+ queued_keypresses--;
+ return;
+}
-int get_mouse_status(char *x, char *y, char *b);
-int get_key_char(char *c);
+#include <stdint.h>
+
+enum keypress_type {
+ KEYPRESS_RELEASE,
+ KEYPRESS_PRESS,
+ KEYPRESS_REPEAT,
+};
+
+int get_mouse_status(uint8_t *x, uint8_t *y, uint8_t *b, uint8_t *e);
+int get_key_char(char *c, char *code, char *event_type);
+int queue_keypress(uint8_t keycode, uint8_t event_type, uint8_t platform);
+int get_num_kb_queued();
+void pop_queued_key(uint8_t *c, uint8_t *t);
* USER mode, but it is also slower.
*/
+#define m68k_read_disassembler_8 m68k_read_memory_8
+#define m68k_read_disassembler_16 m68k_read_memory_16
+#define m68k_read_disassembler_32 m68k_read_memory_32
+
/* Read from anywhere */
unsigned int m68k_read_memory_8(unsigned int address);
unsigned int m68k_read_memory_16(unsigned int address);
void m68k_write_memory_16(unsigned int address, unsigned int value);
void m68k_write_memory_32(unsigned int address, unsigned int value);
+/* PiStorm speed hax */
+void m68k_add_ram_range(uint32_t addr, uint32_t upper, unsigned char *ptr);
+void m68k_add_rom_range(uint32_t addr, uint32_t upper, unsigned char *ptr);
+
/* Special call to simulate undocumented 68k behavior when move.l with a
* predecrement destination mode is executed.
* To simulate real 68k behavior, first write the high word to
*/
void m68k_write_memory_32_pd(unsigned int address, unsigned int value);
-
-
/* ======================================================================== */
/* ============================== CALLBACKS =============================== */
/* ======================================================================== */
#define M68K_USE_64_BIT OPT_ON
-#include "main.h"
+#include "emulator.h"
//#define m68k_read_memory_8(A) read16(A)
}
}
+uint m68k_get_address_mask() {
+ return m68ki_cpu.address_mask;
+}
+
/* Execute some instructions until we use up num_cycles clock cycles */
/* ASG: removed per-instruction interrupt checks */
int m68k_execute(int num_cycles)
/* Return point if we had an address error */
m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */
+#ifdef M68K_BUSERR_THING
m68ki_check_bus_error_trap();
+#endif
/* Main loop. Keep going until we run out of clock cycles */
do
{
+#ifdef M68K_BUSERR_THING
int i;
+#endif
/* Set tracing accodring to T1. (T0 is done inside instruction) */
m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */
REG_PPC = REG_PC;
/* Record previous D/A register state (in case of bus error) */
+#ifdef M68K_BUSERR_THING
for (i = 15; i >= 0; i--){
REG_DA_SAVE[i] = REG_DA[i];
}
+#endif
/* Read an instruction and call its handler */
REG_IR = m68ki_read_imm_16();
if(src) m68ki_cpu = *(m68ki_cpu_core*)src;
}
+#if M68K_SEPARATE_READS
+/* Read data immediately following the PC */
+inline unsigned int m68k_read_immediate_16(unsigned int address) {
+#if M68K_EMULATE_PREFETCH == OPT_ON
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be16toh(((unsigned short *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+#endif
+
+ return m68k_read_memory_16(address);
+}
+inline unsigned int m68k_read_immediate_32(unsigned int address) {
+#if M68K_EMULATE_PREFETCH == OPT_ON
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be32toh(((unsigned int *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+#endif
+
+ return m68k_read_memory_32(address);
+}
+
+/* Read data relative to the PC */
+inline unsigned int m68k_read_pcrelative_8(unsigned int address) {
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return read_data[i][address - read_addr[i]];
+ }
+ }
+
+ return m68k_read_memory_8(address);
+}
+inline unsigned int m68k_read_pcrelative_16(unsigned int address) {
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be16toh(((unsigned short *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
+ return m68k_read_memory_16(address);
+}
+inline unsigned int m68k_read_pcrelative_32(unsigned int address) {
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be32toh(((unsigned int *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
+ return m68k_read_memory_32(address);
+}
+#endif
+
+void m68k_add_ram_range(uint32_t addr, uint32_t upper, unsigned char *ptr)
+{
+ if ((addr == 0 && upper == 0) || upper < addr)
+ return;
+
+ for (int i = 0; i < write_ranges; i++) {
+ if (write_addr[i] == addr) {
+ uint8_t changed = 0;
+ if (write_upper[i] != upper) {
+ write_upper[i] = upper;
+ changed = 1;
+ }
+ if (write_data[i] != ptr) {
+ write_data[i] = ptr;
+ changed = 1;
+ }
+ if (changed) {
+ printf("[MUSASHI] Adjusted mapped write range %d: %.8X-%.8X (%p)\n", write_ranges, addr, upper, ptr);
+ }
+ return;
+ }
+ }
+
+ if (read_ranges + 1 < 8) {
+ read_addr[read_ranges] = addr;
+ read_upper[read_ranges] = upper;
+ read_data[read_ranges] = ptr;
+ read_ranges++;
+ printf("[MUSASHI] Mapped read range %d: %.8X-%.8X (%p)\n", read_ranges, addr, upper, ptr);
+ }
+ else {
+ printf("Can't Musashi map more than eight RAM/ROM read ranges.\n");
+ }
+ if (write_ranges + 1 < 8) {
+ write_addr[write_ranges] = addr;
+ write_upper[write_ranges] = upper;
+ write_data[write_ranges] = ptr;
+ write_ranges++;
+ printf("[MUSASHI] Mapped write range %d: %.8X-%.8X (%p)\n", write_ranges, addr, upper, ptr);
+ }
+ else {
+ printf("Can't Musashi map more than eight RAM write ranges.\n");
+ }
+}
+
+void m68k_add_rom_range(uint32_t addr, uint32_t upper, unsigned char *ptr)
+{
+ if ((addr == 0 && upper == 0) || upper < addr)
+ return;
+
+ for (int i = 0; i < read_ranges; i++) {
+ if (read_addr[i] == addr) {
+ uint8_t changed = 0;
+ if (read_upper[i] != upper) {
+ read_upper[i] = upper;
+ changed = 1;
+ }
+ if (read_data[i] != ptr) {
+ read_data[i] = ptr;
+ changed = 1;
+ }
+ if (changed) {
+ printf("[MUSASHI] Adjusted mapped read range %d: %.8X-%.8X (%p)\n", read_ranges, addr, upper, ptr);
+ }
+ return;
+ }
+ }
+
+ if (read_ranges + 1 < 8) {
+ read_addr[read_ranges] = addr;
+ read_upper[read_ranges] = upper;
+ read_data[read_ranges] = ptr;
+ read_ranges++;
+ printf("[MUSASHI] Mapped read range %d: %.8X-%.8X (%p)\n", read_ranges, addr, upper, ptr);
+ }
+ else {
+ printf("Can't Musashi map more than eight RAM/ROM read ranges.\n");
+ }
+}
+
/* ======================================================================== */
/* ============================== MAME STUFF ============================== */
/* ======================================================================== */
#include "m68k.h"
#include <limits.h>
+#include <endian.h>
#include <setjmp.h>
/* ---------------------------- Read Immediate ---------------------------- */
+extern unsigned char read_ranges;
+extern unsigned int read_addr[8];
+extern unsigned int read_upper[8];
+extern unsigned char *read_data[8];
+extern unsigned char write_ranges;
+extern unsigned int write_addr[8];
+extern unsigned int write_upper[8];
+extern unsigned char *write_data[8];
+
extern uint pmmu_translate_addr(uint addr_in);
/* Handles all immediate reads, does address error check, function code setting,
m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
#if M68K_SEPARATE_READS
-#if M68K_EMULATE_PMMU
+/*#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
- address = pmmu_translate_addr(address);
-#endif
+ address = pmmu_translate_addr(ADDRESS_68K(CPU_PREF_ADDR));
+#endif*/
#endif
#if M68K_EMULATE_PREFETCH
return result;
}
#else
+
+ uint32_t address = ADDRESS_68K(REG_PC);
REG_PC += 2;
+
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be16toh(((unsigned short *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2));
#endif /* M68K_EMULATE_PREFETCH */
}
static inline uint m68ki_read_imm_32(void)
{
#if M68K_SEPARATE_READS
-#if M68K_EMULATE_PMMU
+/*#if M68K_EMULATE_PMMU
if (PMMU_ENABLED)
- address = pmmu_translate_addr(address);
-#endif
+ address = pmmu_translate_addr(ADDRESS_68K(CPU_PREF_ADDR));
+#endif*/
#endif
#if M68K_EMULATE_PREFETCH
if(REG_PC != CPU_PREF_ADDR)
{
CPU_PREF_ADDR = REG_PC;
+
CPU_PREF_DATA = m68k_read_immediate_16(ADDRESS_68K(CPU_PREF_ADDR));
}
temp_val = MASK_OUT_ABOVE_16(CPU_PREF_DATA);
#else
m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
+ uint32_t address = ADDRESS_68K(REG_PC);
REG_PC += 4;
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be32toh(((unsigned int *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4));
#endif /* M68K_EMULATE_PREFETCH */
}
* These functions will also check for address error and set the function
* code if they are enabled in m68kconf.h.
*/
+
static inline uint m68ki_read_8_fc(uint address, uint fc)
{
(void)fc;
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return read_data[i][address - read_addr[i]];
+ }
+ }
+
return m68k_read_memory_8(ADDRESS_68K(address));
}
static inline uint m68ki_read_16_fc(uint address, uint fc)
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be16toh(((unsigned short *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
return m68k_read_memory_16(ADDRESS_68K(address));
}
static inline uint m68ki_read_32_fc(uint address, uint fc)
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < read_ranges; i++) {
+ if(address >= read_addr[i] && address < read_upper[i]) {
+ return be32toh(((unsigned int *)(read_data[i] + (address - read_addr[i])))[0]);
+ }
+ }
+
return m68k_read_memory_32(ADDRESS_68K(address));
}
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < write_ranges; i++) {
+ if(address >= write_addr[i] && address < write_upper[i]) {
+ write_data[i][address - write_addr[i]] = (unsigned char)value;
+ return;
+ }
+ }
+
m68k_write_memory_8(ADDRESS_68K(address), value);
}
static inline void m68ki_write_16_fc(uint address, uint fc, uint value)
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < write_ranges; i++) {
+ if(address >= write_addr[i] && address < write_upper[i]) {
+ ((short *)(write_data[i] + (address - write_addr[i])))[0] = htobe16(value);
+ return;
+ }
+ }
+
m68k_write_memory_16(ADDRESS_68K(address), value);
}
static inline void m68ki_write_32_fc(uint address, uint fc, uint value)
address = pmmu_translate_addr(address);
#endif
+ for (int i = 0; i < write_ranges; i++) {
+ if(address >= write_addr[i] && address < write_upper[i]) {
+ ((int *)(write_data[i] + (address - write_addr[i])))[0] = htobe32(value);
+ return;
+ }
+ }
+
m68k_write_memory_32(ADDRESS_68K(address), value);
}
#include "config_file/config_file.h"
#include "m68k.h"
-#include "Gayle.h"
+#include "platforms/amiga/Gayle.h"
#include <endian.h>
#define CHKRANGE(a, b, c) a >= (unsigned int)b && a < (unsigned int)(b + c)
+#define CHKRANGE_ABS(a, b, c) a >= (unsigned int)b && a < (unsigned int) c
static unsigned int target;
+extern int ovl;
extern const char *map_type_names[MAPTYPE_NUM];
const char *op_type_names[OP_TYPE_NUM] = {
"MEM",
};
-int handle_mapped_read(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type, unsigned char mirror) {
+inline int handle_mapped_read(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type) {
unsigned char *read_addr = NULL;
- char handle_regs = 0;
-
- //printf("Mapped read: %.8x\n", addr);
for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i++) {
if (cfg->map_type[i] == MAPTYPE_NONE)
continue;
- switch(cfg->map_type[i]) {
- case MAPTYPE_ROM:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- read_addr = cfg->map_data[i] + ((addr - cfg->map_offset[i]) % cfg->rom_size[i]);
- else if (cfg->map_mirror[i] != -1 && mirror && CHKRANGE(addr, cfg->map_mirror[i], cfg->map_size[i]))
- read_addr = cfg->map_data[i] + ((addr - cfg->map_mirror[i]) % cfg->rom_size[i]);
- break;
- case MAPTYPE_RAM:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- read_addr = cfg->map_data[i] + (addr - cfg->map_offset[i]);
- break;
- case MAPTYPE_REGISTER:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- handle_regs = 1;
- break;
- }
-
- if (!read_addr && !handle_regs)
- continue;
-
- if (handle_regs) {
- if (cfg->platform && cfg->platform->register_read) {
- if (cfg->platform->register_read(addr, type, &target) != -1) {
- *val = target;
- return 1;
- }
+ else if (ovl && cfg->map_type[i] == MAPTYPE_ROM) {
+ if (cfg->map_mirror[i] != -1 && CHKRANGE(addr, cfg->map_mirror[i], cfg->map_size[i])) {
+ read_addr = cfg->map_data[i] + ((addr - cfg->map_mirror[i]) % cfg->rom_size[i]);
+ goto read_value;
}
- return -1;
}
- else if (read_addr) {
- //printf("[PC: %.8X] Read %s from %s (%.8X) (%d)\n", m68k_get_reg(NULL, M68K_REG_PC), op_type_names[type], map_type_names[cfg->map_type[i]], addr, mirror);
- //printf("Readaddr: %.8lX (Base %.8lX\n", (uint64_t)(read_addr), (uint64_t)cfg->map_data[i]);
- switch(type) {
- case OP_TYPE_BYTE:
- *val = read_addr[0];
- //printf("Read val: %.8lX (%d)\n", (uint64_t)val, *val);
- return 1;
- break;
- case OP_TYPE_WORD:
- *val = be16toh(((unsigned short *)read_addr)[0]);
- //printf("Read val: %.8lX (%d)\n", (uint64_t)val, *val);
- return 1;
+ if (CHKRANGE_ABS(addr, cfg->map_offset[i], cfg->map_high[i])) {
+ switch(cfg->map_type[i]) {
+ case MAPTYPE_ROM:
+ read_addr = cfg->map_data[i] + ((addr - cfg->map_offset[i]) % cfg->rom_size[i]);
+ goto read_value;
break;
- case OP_TYPE_LONGWORD:
- *val = be32toh(((unsigned int *)read_addr)[0]);
- //printf("Read val: %.8lX (%d)\n", (uint64_t)val, *val);
- return 1;
+ case MAPTYPE_RAM:
+ read_addr = cfg->map_data[i] + (addr - cfg->map_offset[i]);
+ goto read_value;
break;
- case OP_TYPE_MEM:
+ case MAPTYPE_REGISTER:
+ if (cfg->platform && cfg->platform->register_read) {
+ if (cfg->platform->register_read(addr, type, &target) != -1) {
+ *val = target;
+ return 1;
+ }
+ }
return -1;
break;
}
}
return -1;
+
+read_value:;
+ //printf("Read value from %.8X\n", addr);
+ switch(type) {
+ case OP_TYPE_BYTE:
+ *val = read_addr[0];
+ return 1;
+ break;
+ case OP_TYPE_WORD:
+ *val = be16toh(((unsigned short *)read_addr)[0]);
+ return 1;
+ break;
+ case OP_TYPE_LONGWORD:
+ *val = be32toh(((unsigned int *)read_addr)[0]);
+ return 1;
+ break;
+ case OP_TYPE_MEM:
+ return -1;
+ break;
+ }
+
+ return 1;
}
-int handle_mapped_write(struct emulator_config *cfg, unsigned int addr, unsigned int value, unsigned char type, unsigned char mirror) {
+inline int handle_mapped_write(struct emulator_config *cfg, unsigned int addr, unsigned int value, unsigned char type) {
unsigned char *write_addr = NULL;
- char handle_regs = 0;
-
- //printf("Mapped write: %.8x\n", addr);
- if (mirror) { }
for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i++) {
if (cfg->map_type[i] == MAPTYPE_NONE)
continue;
- switch(cfg->map_type[i]) {
- case MAPTYPE_ROM:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- return 1;
- break;
- case MAPTYPE_RAM:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- write_addr = cfg->map_data[i] + (addr - cfg->map_offset[i]);
- break;
- case MAPTYPE_REGISTER:
- if (CHKRANGE(addr, cfg->map_offset[i], cfg->map_size[i]))
- handle_regs = 1;
- break;
- }
-
- if (!write_addr && !handle_regs)
- continue;
-
- if (handle_regs) {
- if (cfg->platform && cfg->platform->register_write) {
- return cfg->platform->register_write(addr, value, type);
- }
- }
- else if (write_addr) {
- //printf("[PC: %.8X] Write %s to %s (%.8X) (%d)\n", m68k_get_reg(NULL, M68K_REG_PC), op_type_names[type], map_type_names[cfg->map_type[i]], addr, mirror);
- //printf("Writeaddr: %.8lX (Base %.8lX\n", (uint64_t)(write_addr), (uint64_t)cfg->map_data[i]);
- switch(type) {
- case OP_TYPE_BYTE:
- write_addr[0] = (unsigned char)value;
- //printf("Write val: %.8X (%d)\n", (uint32_t)value, value);
+ else if (CHKRANGE_ABS(addr, cfg->map_offset[i], cfg->map_high[i])) {
+ switch(cfg->map_type[i]) {
+ case MAPTYPE_ROM:
return 1;
break;
- case OP_TYPE_WORD:
- ((short *)write_addr)[0] = htobe16(value);
- //printf("Write val: %.8X (%d)\n", (uint32_t)value, value);
- return 1;
- break;
- case OP_TYPE_LONGWORD:
- ((int *)write_addr)[0] = htobe32(value);
- //printf("Write val: %.8X (%d)\n", (uint32_t)value, value);
- return 1;
+ case MAPTYPE_RAM:
+ write_addr = cfg->map_data[i] + (addr - cfg->map_offset[i]);
+ goto write_value;
break;
- case OP_TYPE_MEM:
- return -1;
+ case MAPTYPE_REGISTER:
+ if (cfg->platform && cfg->platform->register_write) {
+ return cfg->platform->register_write(addr, value, type);
+ }
break;
}
}
}
return -1;
+
+write_value:;
+ //printf("Write value to %.8X\n", addr);
+ switch(type) {
+ case OP_TYPE_BYTE:
+ write_addr[0] = (unsigned char)value;
+ return 1;
+ break;
+ case OP_TYPE_WORD:
+ ((short *)write_addr)[0] = htobe16(value);
+ return 1;
+ break;
+ case OP_TYPE_LONGWORD:
+ ((int *)write_addr)[0] = htobe32(value);
+ return 1;
+ break;
+ case OP_TYPE_MEM:
+ return -1;
+ break;
+ }
+
+ return 1;
}
--- /dev/null
+//
+// Gayle.c
+// Omega
+//
+// Created by Matt Parsons on 06/03/2019.
+// Copyright © 2019 Matt Parsons. All rights reserved.
+//
+
+// Write Byte to Gayle Space 0xda9000 (0x0000c3)
+// Read Byte From Gayle Space 0xda9000
+// Read Byte From Gayle Space 0xdaa000
+
+#include "Gayle.h"
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <time.h>
+#include <endian.h>
+
+#include "platforms/shared/rtc.h"
+#include "config_file/config_file.h"
+
+#include "gayle-ide/ide.h"
+#include "amiga-registers.h"
+
+#define DEBUG(...)
+//#define DEBUG printf
+
+uint8_t gary_cfg[8];
+
+uint8_t ramsey_cfg = 0x08;
+static uint8_t ramsey_id = RAMSEY_REV7;
+
+int counter;
+static uint8_t gayle_irq, gayle_cs, gayle_cs_mask, gayle_cfg;
+static struct ide_controller *ide0 = NULL;
+int fd;
+
+uint8_t rtc_type = RTC_TYPE_RICOH;
+
+char *hdd_image_file[GAYLE_MAX_HARDFILES];
+
+uint8_t cdtv_mode = 0;
+unsigned char cdtv_sram[32 * SIZE_KILO];
+
+uint8_t gayle_a4k = 0xA0;
+uint16_t gayle_a4k_irq = 0;
+uint8_t gayle_a4k_int = 0;
+uint8_t gayle_int = 0;
+
+uint32_t gayle_ide_mask = ~GDATA;
+uint32_t gayle_ide_base = GDATA;
+uint8_t gayle_ide_enabled = 1;
+uint8_t gayle_emulation_enabled = 1;
+uint8_t gayle_ide_adj = 0;
+
+struct ide_controller *get_ide(int index) {
+ if (index) {}
+ return ide0;
+}
+
+void adjust_gayle_4000() {
+ gayle_ide_base = GAYLE_IDE_BASE_A4000;
+ gayle_ide_adj = 2;
+ gayle_a4k_int = 1;
+}
+
+void adjust_gayle_1200() {
+
+}
+
+void set_hard_drive_image_file_amiga(uint8_t index, char *filename) {
+ if (hdd_image_file[index] != NULL)
+ free(hdd_image_file[index]);
+ hdd_image_file[index] = calloc(1, strlen(filename) + 1);
+ strcpy(hdd_image_file[index], filename);
+}
+
+void InitGayle(void) {
+ uint8_t num_ide_drives = 0;
+
+ for (int i = 0; i < GAYLE_MAX_HARDFILES; i++) {
+ if (hdd_image_file[i]) {
+ fd = open(hdd_image_file[i], O_RDWR);
+ if (fd != -1) {
+ if (!ide0)
+ ide0 = ide_allocate("cf");
+ }
+
+ if (fd == -1) {
+ printf("[HDD%d] HDD Image %s failed open\n", i, hdd_image_file[i]);
+ } else {
+ printf("[HDD%d] Attaching HDD image %s.\n", i, hdd_image_file[i]);
+ if (strcmp(hdd_image_file[i] + (strlen(hdd_image_file[i]) - 3), "img") != 0) {
+ printf("No header present on HDD image %s.\n", hdd_image_file[i]);
+ ide_attach_hdf(ide0, i, fd);
+ num_ide_drives++;
+ }
+ else {
+ printf("Attaching HDD image with header.\n");
+ ide_attach(ide0, i, fd);
+ num_ide_drives++;
+ }
+ printf("[HDD%d] HDD Image %s attached\n", i, hdd_image_file[i]);
+ }
+ }
+ }
+ if (ide0)
+ ide_reset_begin(ide0);
+
+ if (num_ide_drives == 0) {
+ // No IDE drives mounted, disable IDE component of Gayle
+ printf("No IDE drives mounted, disabling Gayle IDE component.\n");
+ gayle_ide_enabled = 0;
+ }
+}
+
+uint8_t CheckIrq(void) {
+ uint8_t irq;
+
+ if (gayle_int & (1 << 7)) {
+ irq = ide0->drive[0].intrq || ide0->drive[1].intrq;
+ // if (irq==0)
+ // printf("IDE IRQ: %x\n",irq);
+ return irq;
+ };
+ return 0;
+}
+
+static uint8_t ide_action = 0;
+
+void writeGayleB(unsigned int address, unsigned int value) {
+ if (ide0) {
+ if (address >= gayle_ide_base) {
+ switch ((address - gayle_ide_base) - gayle_ide_adj) {
+ case GFEAT_OFFSET:
+ //printf("Write to GFEAT: %.2X.\n", value);
+ ide_action = ide_feature_w;
+ goto idewrite8;
+ case GCMD_OFFSET:
+ //printf("Write to GCMD: %.2X.\n", value);
+ ide_action = ide_command_w;
+ goto idewrite8;
+ case GSECTCOUNT_OFFSET:
+ ide_action = ide_sec_count;
+ goto idewrite8;
+ case GSECTNUM_OFFSET:
+ ide_action = ide_sec_num;
+ goto idewrite8;
+ case GCYLLOW_OFFSET:
+ ide_action = ide_cyl_low;
+ goto idewrite8;
+ case GCYLHIGH_OFFSET:
+ ide_action = ide_cyl_hi;
+ goto idewrite8;
+ case GDEVHEAD_OFFSET:
+ //printf("Write to GDEVHEAD: %.2X.\n", value);
+ ide_action = ide_dev_head;
+ goto idewrite8;
+ case GCTRL_OFFSET:
+ //printf("Write to GCTRL: %.2X.\n", value);
+ ide_action = ide_devctrl_w;
+ goto idewrite8;
+ case GIRQ_4000_OFFSET:
+ gayle_a4k_irq = value;
+ case GIRQ_OFFSET:
+ gayle_irq = (gayle_irq & value) | (value & (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR));
+ return;
+ }
+ goto skip_idewrite8;
+idewrite8:;
+ ide_write8(ide0, ide_action, value);
+ return;
+skip_idewrite8:;
+ }
+ }
+
+ switch (address) {
+ /*case 0xDD203A:
+ printf("Write bye to A4000 Gayle: %.2X\n", value);
+ gayle_a4k = value;
+ return;*/
+ case GIDENT:
+ //printf("Write to GIDENT: %d\n", value);
+ counter = 0;
+ return;
+ case GCONF:
+ //printf("Write to GCONF: %d\n", gayle_cfg);
+ gayle_cfg = value;
+ return;
+ case RAMSEY_REG:
+ ramsey_cfg = value & 0x0F;
+ return;
+ case GINT:
+ gayle_int = value;
+ return;
+ case GCS:
+ gayle_cs_mask = value & ~3;
+ gayle_cs &= ~3;
+ gayle_cs |= value & 3;
+ printf("Write to GCS: %d\n", gayle_cs);
+ //ide0->selected = gayle_cs;
+ return;
+ }
+
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] BYTE write to SRAM @%.8X (%.8X): %.2X\n", (address & CLOCKMASK) - 0x8000, address, value);
+ cdtv_sram[(address & CLOCKMASK) - 0x8000] = value;
+ }
+ return;
+ }
+ //printf("Byte write to RTC.\n");
+ put_rtc_byte(address, value, rtc_type);
+ return;
+ }
+
+ DEBUG("Write Byte to Gayle Space 0x%06x (0x%06x)\n", address, value);
+}
+
+void writeGayle(unsigned int address, unsigned int value) {
+ if (ide0) {
+ if (address - gayle_ide_base == GDATA_OFFSET) {
+ ide_write16(ide0, ide_data, value);
+ return;
+ }
+
+ if (address == GIRQ_A4000) {
+ gayle_a4k_irq = value;
+ return;
+ }
+ }
+
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] WORD write to SRAM @%.8X (%.8X): %.4X\n", (address & CLOCKMASK) - 0x8000, address, htobe16(value));
+ ((short *) ((size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000)))[0] = htobe16(value);
+ }
+ return;
+ }
+ //printf("Word write to RTC.\n");
+ put_rtc_byte(address + 1, (value & 0xFF), rtc_type);
+ put_rtc_byte(address, (value >> 8), rtc_type);
+ return;
+ }
+
+ DEBUG("Write Word to Gayle Space 0x%06x (0x%06x)\n", address, value);
+}
+
+void writeGayleL(unsigned int address, unsigned int value) {
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] LONGWORD write to SRAM @%.8X (%.8X): %.8X\n", (address & CLOCKMASK) - 0x8000, address, htobe32(value));
+ ((int *) (size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000))[0] = htobe32(value);
+ }
+ return;
+ }
+ //printf("Longword write to RTC.\n");
+ put_rtc_byte(address + 3, (value & 0xFF), rtc_type);
+ put_rtc_byte(address + 2, ((value & 0x0000FF00) >> 8), rtc_type);
+ put_rtc_byte(address + 1, ((value & 0x00FF0000) >> 16), rtc_type);
+ put_rtc_byte(address, (value >> 24), rtc_type);
+ return;
+ }
+
+ DEBUG("Write Long to Gayle Space 0x%06x (0x%06x)\n", address, value);
+}
+
+uint8_t readGayleB(unsigned int address) {
+ if (ide0) {
+ uint8_t ide_action = 0, ide_val = 0;
+
+ if (address >= gayle_ide_base) {
+ switch ((address - gayle_ide_base) - gayle_ide_adj) {
+ case GERROR_OFFSET:
+ ide_action = ide_error_r;
+ goto ideread8;
+ case GSTATUS_OFFSET:
+ ide_action = ide_status_r;
+ goto ideread8;
+ case GSECTCOUNT_OFFSET:
+ ide_action = ide_sec_count;
+ goto ideread8;
+ case GSECTNUM_OFFSET:
+ ide_action = ide_sec_num;
+ goto ideread8;
+ case GCYLLOW_OFFSET:
+ ide_action = ide_cyl_low;
+ goto ideread8;
+ case GCYLHIGH_OFFSET:
+ ide_action = ide_cyl_hi;
+ goto ideread8;
+ case GDEVHEAD_OFFSET:
+ ide_action = ide_dev_head;
+ goto ideread8;
+ case GCTRL_OFFSET:
+ ide_action = ide_altst_r;
+ goto ideread8;
+ case GIRQ_4000_OFFSET:
+ case GIRQ_OFFSET:
+ return 0x80;
+ //gayle_irq = (gayle_irq & value) | (value & (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR));
+ }
+ goto skip_ideread8;
+ideread8:;
+ ide_val = ide_read8(ide0, ide_action);
+ return ide_val;
+skip_ideread8:;
+ }
+
+ switch (address) {
+ case GIDENT: {
+ uint8_t val;
+ if (counter == 0 || counter == 1 || counter == 3) {
+ val = 0x80; // 80; to enable gayle
+ } else {
+ val = 0x00;
+ }
+ counter++;
+ //printf("Read from GIDENT: %.2X.\n", val);
+ return val;
+ }
+ case GINT:
+ return gayle_int;
+ case GCONF:
+ //printf("Read from GCONF: %d\n", gayle_cfg & 0x0F);
+ return gayle_cfg & 0x0f;
+ case GCS: {
+ uint8_t v;
+ v = gayle_cs_mask | gayle_cs;
+ printf("Read from GCS: %d\n", v);
+ return v;
+ }
+ // This seems incorrect, GARY_REG3 is the same as GIDENT, and the A4000
+ // service manual says that Gary is accessible in the address range $DFC000 to $DFFFFF.
+ case GARY_REG0:
+ case GARY_REG1:
+ case GARY_REG2:
+ return gary_cfg[address - GARY_REG0];
+ break;
+ //case GARY_REG3:
+ case GARY_REG4:
+ //case GARY_REG5:
+ return gary_cfg[address - GARY_REG4];
+ case RAMSEY_ID:
+ return ramsey_id;
+ case RAMSEY_REG:
+ return ramsey_cfg;
+ case GARY_REG5: { // This makes no sense.
+ uint8_t val;
+ if (counter == 0 || counter == 1 || counter == 3) {
+ val = 0x80; // 80; to enable GARY
+ } else {
+ val = 0x00;
+ }
+ counter++;
+ return val;
+ }
+ //case 0xDD203A:
+ // This can't be correct, as this is the same address as GDEVHEAD on the A4000 Gayle.
+ //printf("Read Byte from Gayle A4k: %.2X\n", gayle_a4k);
+ //return gayle_a4k;
+ }
+ }
+
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] BYTE read from SRAM @%.8X (%.8X): %.2X\n", (address & CLOCKMASK) - 0x8000, address, cdtv_sram[(address & CLOCKMASK) - 0x8000]);
+ return cdtv_sram[(address & CLOCKMASK) - 0x8000];
+ }
+ return 0;
+ }
+ //printf("Byte read from RTC.\n");
+ return get_rtc_byte(address, rtc_type);
+ }
+
+ DEBUG("Read Byte From Gayle Space 0x%06x\n", address);
+ return 0xFF;
+}
+
+uint16_t readGayle(unsigned int address) {
+ if (ide0) {
+ if (address - gayle_ide_base == GDATA_OFFSET) {
+ uint16_t value;
+ value = ide_read16(ide0, ide_data);
+ // value = (value << 8) | (value >> 8);
+ return value;
+ }
+
+ if (address == GIRQ_A4000) {
+ gayle_a4k_irq = 0x8000;
+ return 0x8000;
+ }
+ }
+
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] WORD read from SRAM @%.8X (%.8X): %.4X\n", (address & CLOCKMASK) - 0x8000, address, be16toh( (( unsigned short *) (size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000))[0]));
+ return be16toh( (( unsigned short *) (size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000))[0]);
+ }
+ return 0;
+ }
+ //printf("Word read from RTC.\n");
+ return ((get_rtc_byte(address, rtc_type) << 8) | (get_rtc_byte(address + 1, rtc_type)));
+ }
+
+ DEBUG("Read Word From Gayle Space 0x%06x\n", address);
+ return 0x8000;
+}
+
+uint32_t readGayleL(unsigned int address) {
+ if ((address & GAYLEMASK) == CLOCKBASE) {
+ if ((address & CLOCKMASK) >= 0x8000) {
+ if (cdtv_mode) {
+ //printf("[CDTV] LONGWORD read from SRAM @%.8X (%.8X): %.8X\n", (address & CLOCKMASK) - 0x8000, address, be32toh( (( unsigned short *) (size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000))[0]));
+ return be32toh( (( unsigned int *) (size_t)(cdtv_sram + (address & CLOCKMASK) - 0x8000))[0]);
+ }
+ return 0;
+ }
+ //printf("Longword read from RTC.\n");
+ return ((get_rtc_byte(address, rtc_type) << 24) | (get_rtc_byte(address + 1, rtc_type) << 16) | (get_rtc_byte(address + 2, rtc_type) << 8) | (get_rtc_byte(address + 3, rtc_type)));
+ }
+
+ DEBUG("Read Long From Gayle Space 0x%06x\n", address);
+ return 0x8000;
+}
--- /dev/null
+//
+// Gayle.h
+// Omega
+//
+// Created by Matt Parsons on 06/03/2019.
+// Copyright © 2019 Matt Parsons. All rights reserved.
+//
+
+#ifndef Gayle_h
+#define Gayle_h
+
+#define GAYLE_MAX_HARDFILES 8
+
+#include <stdio.h>
+#include <stdint.h>
+
+uint8_t CheckIrq(void);
+void InitGayle(void);
+void writeGayleB(unsigned int address, unsigned value);
+void writeGayle(unsigned int address, unsigned value);
+void writeGayleL(unsigned int address, unsigned value);
+uint8_t readGayleB(unsigned int address);
+uint16_t readGayle(unsigned int address);
+uint32_t readGayleL(unsigned int address);
+
+struct ide_controller *get_ide(int index);
+
+// Gayle Addresses
+#define GAYLE_IDE_BASE_A1200 0xDA2000 //16bit base
+#define GAYLE_IDE_BASE_A4000 0xDD2020
+
+// Gayle IDE Reads
+#define GERROR 0xda2004 // Error
+#define GSTATUS 0xda201C // Status
+#define GERROR_A4000 GAYLE_IDE_BASE_A4000 + 0x06 // Error
+#define GSTATUS_A4000 GAYLE_IDE_BASE_A4000 + 0x1E // Status
+
+// Gayle IDE read offsets
+#define GERROR_OFFSET 0x04
+#define GSTATUS_OFFSET 0x1C
+// Gayle IDE write offsets
+#define GFEAT_OFFSET 0x04
+#define GCMD_OFFSET 0x1C
+// Gayle IDE RW offsets
+#define GDATA_OFFSET 0x00
+#define GSECTCOUNT_OFFSET 0x08
+#define GSECTNUM_OFFSET 0x0C
+#define GCYLLOW_OFFSET 0x10
+#define GCYLHIGH_OFFSET 0x14
+#define GDEVHEAD_OFFSET 0x18
+#define GCTRL_OFFSET 0x1018
+#define GIRQ_OFFSET 0x7000
+#define GIRQ_4000_OFFSET 0x1002
+
+// Gayle IDE Writes
+#define GFEAT 0xda2004 // Write : Feature
+#define GCMD 0xda201c // Write : Command
+#define GFEAT_A4000 GAYLE_IDE_BASE_A4000 + 0x06 // Write : Feature
+#define GCMD_A4000 GAYLE_IDE_BASE_A4000 + 0x1E // Write : Command
+#define GMODEREG0_A4000 0x0DD1020 // D31, PIO modes (00,01,10)
+#define GMODEREG1_A4000 0x0DD1022 // D31, (MSB)
+
+// Gayle IDE RW
+#define GDATA 0xda2000 // Data - 16 bit
+#define GSECTCNT 0xda2008 // SectorCount
+#define GSECTNUM 0xda200c // SectorNumber
+#define GCYLLOW 0xda2010 // CylinderLow
+#define GCYLHIGH 0xda2014 // CylinderHigh
+#define GDEVHEAD 0xda2018 // Device/Head
+#define GCTRL 0xda3018 // Control
+
+#define GDATA_A4000 GAYLE_IDE_BASE_A4000 // Data
+#define GSECTCNT_A4000 GAYLE_IDE_BASE_A4000 + 0x0a // SectorCount
+#define GSECTNUM_A4000 GAYLE_IDE_BASE_A4000 + 0x0e // SectorNumber
+#define GCYLLOW_A4000 GAYLE_IDE_BASE_A4000 + 0x12 // CylinderLow
+#define GCYLHIGH_A4000 GAYLE_IDE_BASE_A4000 + 0x16 // CylinderHigh
+#define GDEVHEAD_A4000 GAYLE_IDE_BASE_A4000 + 0x1a // Device/Head
+#define GCTRL_A4000 GAYLE_IDE_BASE_A4000 + 0x101a // Control
+
+// For A4000 there's no need to populate other areas, just GIRQ
+#define GIRQ_A4000 GAYLE_IDE_BASE_A4000 + 0x1000 // IRQ 0xDD3020
+
+// Gayle Ident
+#define GIDENT 0xDE1000
+
+// Gayle IRQ/CC
+#define GCS 0xDA8000 // Card Control
+#define GIRQ 0xDA9000 // IRQ
+#define GINT 0xDAA000 // Int enable
+#define GCONF 0xDAB000 // Gayle Config
+
+/* DA8000 */
+#define GAYLE_CS_IDE 0x80 /* IDE int status */
+#define GAYLE_CS_CCDET 0x40 /* credit card detect */
+#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
+#define GAYLE_CS_SC 0x20 /* credit card status change */
+#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
+#define GAYLE_CS_DA 0x10 /* digital audio */
+#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
+#define GAYLE_CS_BSY 0x04 /* credit card busy */
+#define GAYLE_CS_IRQ 0x04 /* interrupt request */
+#define GAYLE_CS_DAEN 0x02 /* enable digital audio */
+#define GAYLE_CS_DIS 0x01 /* disable PCMCIA slot */
+
+/* DA9000 */
+#define GAYLE_IRQ_IDE 0x80
+#define GAYLE_IRQ_CCDET 0x40 /* credit card detect */
+#define GAYLE_IRQ_BVD1 0x20 /* battery voltage detect 1 */
+#define GAYLE_IRQ_SC 0x20 /* credit card status change */
+#define GAYLE_IRQ_BVD2 0x10 /* battery voltage detect 2 */
+#define GAYLE_IRQ_DA 0x10 /* digital audio */
+#define GAYLE_IRQ_WR 0x08 /* write enable (1 == enabled) */
+#define GAYLE_IRQ_BSY 0x04 /* credit card busy */
+#define GAYLE_IRQ_IRQ 0x04 /* interrupt request */
+#define GAYLE_IRQ_RESET 0x02 /* reset machine after CCDET change */
+#define GAYLE_IRQ_BERR 0x01 /* generate bus error after CCDET change */
+
+/* DAA000 */
+#define GAYLE_INT_IDE 0x80 /* IDE interrupt enable */
+#define GAYLE_INT_CCDET 0x40 /* credit card detect change enable */
+#define GAYLE_INT_BVD1 0x20 /* battery voltage detect 1 change enable */
+#define GAYLE_INT_SC 0x20 /* credit card status change enable */
+#define GAYLE_INT_BVD2 0x10 /* battery voltage detect 2 change enable */
+#define GAYLE_INT_DA 0x10 /* digital audio change enable */
+#define GAYLE_INT_WR 0x08 /* write enable change enabled */
+#define GAYLE_INT_BSY 0x04 /* credit card busy */
+#define GAYLE_INT_IRQ 0x04 /* credit card interrupt request */
+#define GAYLE_INT_BVD_LEV 0x02 /* BVD int level, 0=lev2,1=lev6 */
+#define GAYLE_INT_BSY_LEV 0x01 /* BSY int level, 0=lev2,1=lev6 */
+
+#endif /* Gayle_h */
-#include "../platforms.h"
+#include "platforms/platforms.h"
#include "amiga-autoconf.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#define Z2_Z2 0xC
+#define Z2_FAST 0x2
+#define Z2_BOOTROM 0x1
+
static unsigned char ac_fast_ram_rom[] = {
- 0xe, AC_MEM_SIZE_8MB, // 00/02, link into memory free list, 8 MB
- 0x6, 0x9, // 04/06, product id
+ Z2_Z2 | Z2_FAST, AC_MEM_SIZE_8MB, // 00/02, link into memory free list, 8 MB
+ 0x6, 0x9, // 06/09, product id
0x8, 0x0, // 08/0a, preference to 8 MB space
0x0, 0x0, // 0c/0e, reserved
- 0x0, 0x7, 0xd, 0xb, // 10/12/14/16, mfg id
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x2, 0x0 // 18/.../26, serial
+ 0x0, 0x7, 0xD, 0xB, // 10/12/14/16, mfg id
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x2, 0x0, // 18/.../26, serial
+ 0x0, 0x0, 0x0, 0x0, // Optional BOOT ROM vector
+};
+
+unsigned char ac_piscsi_rom[] = {
+ Z2_Z2 | Z2_BOOTROM, AC_MEM_SIZE_64KB, // 00/01, Z2, bootrom, 64 KB
+ 0x6, 0xA, // 06/0A, product id
+ 0x0, 0x0, // 00/0a, any space where it fits
+ 0x0, 0x0, // 0c/0e, reserved
+ 0x0, 0x7, 0xD, 0xB, // 10/12/14/16, mfg id
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x2, 0x1, // 18/.../26, serial
+ 0x4, 0x0, 0x0, 0x0, // Optional BOOT ROM vector
};
static unsigned char ac_a314_rom[] = {
0x0, 0x0, // 08/0a, any space okay
0x0, 0x0, // 0c/0e, reserved
0x0, 0x7, 0xd, 0xb, // 10/12/14/16, mfg id
- 0xa, 0x3, 0x1, 0x4, 0x0, 0x0, 0x0, 0x0 // 18/.../26, serial
+ 0xa, 0x3, 0x1, 0x4, 0x0, 0x0, 0x0, 0x0, // 18/.../26, serial
+ 0x0, 0x0, 0x0, 0x0, // Optional BOOT ROM vector
};
int ac_z2_current_pic = 0;
int ac_z3_type[AC_PIC_LIMIT];
int ac_z3_index[AC_PIC_LIMIT];
+uint32_t piscsi_base = 0;
+extern uint8_t *piscsi_rom_ptr;
unsigned char get_autoconf_size(int size) {
if (size == 8 * SIZE_MEGA)
return AC_MEM_SIZE_EXT_64MB;
}
+extern void adjust_ranges_amiga(struct emulator_config *cfg);
+
unsigned int autoconfig_read_memory_z3_8(struct emulator_config *cfg, unsigned int address_) {
int address = address_ - AC_Z3_BASE;
int index = ac_z3_index[ac_z3_current_pic];
if (done) {
nib_latch = 0;
- printf("Address of Z3 autoconf RAM assigned to $%.8x\n", ac_base[ac_z3_current_pic]);
+ printf("Address of Z3 autoconf RAM assigned to $%.8x [B]\n", ac_base[ac_z3_current_pic]);
cfg->map_offset[index] = ac_base[ac_z3_current_pic];
+ cfg->map_high[index] = cfg->map_offset[index] + cfg->map_size[index];
+ m68k_add_ram_range(cfg->map_offset[index], cfg->map_high[index], cfg->map_data[index]);
ac_z3_current_pic++;
- if (ac_z3_current_pic == ac_z3_pic_count)
+ if (ac_z3_current_pic == ac_z3_pic_count) {
ac_z3_done = 1;
+ adjust_ranges_amiga(cfg);
+ }
}
return;
switch(address & 0xFF) {
case AC_Z3_REG_WR_ADDR_HI:
- // This is, as far as I know, the only regiter it should write a 16-bit value to.
+ // This is, as far as I know, the only register it should write a 16-bit value to.
ac_base[ac_z3_current_pic] = (ac_base[ac_z3_current_pic] & 0x00000000) | (val << 16);
done = 1;
break;
}
if (done) {
- printf("Address of Z3 autoconf RAM assigned to $%.8x\n", ac_base[ac_z3_current_pic]);
+ printf("Address of Z3 autoconf RAM assigned to $%.8x [W]\n", ac_base[ac_z3_current_pic]);
cfg->map_offset[index] = ac_base[ac_z3_current_pic];
+ cfg->map_high[index] = cfg->map_offset[index] + cfg->map_size[index];
+ m68k_add_ram_range(cfg->map_offset[index], cfg->map_high[index], cfg->map_data[index]);
ac_z3_current_pic++;
if (ac_z3_current_pic == ac_z3_pic_count)
ac_z3_done = 1;
case ACTYPE_A314:
rom = ac_a314_rom;
break;
+ case ACTYPE_PISCSI:
+ rom = ac_piscsi_rom;
+ break;
default:
return 0;
break;
}
-
+
if ((address & 1) == 0 && (address / 2) < (int)sizeof(ac_fast_ram_rom)) {
if (ac_z2_type[ac_z2_current_pic] == ACTYPE_MAPFAST_Z2 && address / 2 == 1) {
val = get_autoconf_size(cfg->map_size[ac_z2_index[ac_z2_current_pic]]);
//printf("Read byte %d from Z2 autoconf for PIC %d (%.2X).\n", address/2, ac_z2_current_pic, val);
}
val <<= 4;
- if (address != 0 && address != 2 && address != 40 && address != 42)
+ if (address != 0 && address != 2 && address != 0x40 && address != 0x42)
val ^= 0xff;
-
+
return (unsigned int)val;
}
void autoconfig_write_memory_8(struct emulator_config *cfg, unsigned int address_, unsigned int value) {
int address = address_ - AC_Z2_BASE;
int done = 0;
+ int index = ac_z2_index[ac_z2_current_pic];
unsigned int *base = NULL;
case ACTYPE_A314:
//base = &a314_base;
break;
+ case ACTYPE_PISCSI:
+ base = &piscsi_base;
+ break;
default:
break;
}
}
if (done) {
- printf("Address of Z2 autoconf RAM assigned to $%.8x\n", ac_base[ac_z2_current_pic]);
- cfg->map_offset[ac_z2_index[ac_z2_current_pic]] = ac_base[ac_z2_current_pic];
+ switch (ac_z2_type[ac_z2_current_pic]) {
+ case ACTYPE_MAPFAST_Z2:
+ cfg->map_offset[index] = ac_base[ac_z2_current_pic];
+ cfg->map_high[index] = cfg->map_offset[index] + cfg->map_size[index];
+ printf("Address of Z2 autoconf RAM assigned to $%.8x\n", ac_base[ac_z2_current_pic]);
+ m68k_add_ram_range(cfg->map_offset[index], cfg->map_high[index], cfg->map_data[index]);
+ printf("Z2 PIC %d at $%.8lX-%.8lX, Size: %d MB\n", ac_z2_current_pic, cfg->map_offset[index], cfg->map_high[index], cfg->map_size[index] / SIZE_MEGA);
+ break;
+ case ACTYPE_PISCSI:
+ printf("PiSCSI Z2 device assigned to $%.8x\n", piscsi_base);
+ //m68k_add_rom_range(piscsi_base + (16 * SIZE_KILO), piscsi_base + (32 * SIZE_KILO), piscsi_rom_ptr);
+ break;
+ default:
+ break;
+ }
ac_z2_current_pic++;
- if (ac_z2_current_pic == ac_z2_pic_count)
+ if (ac_z2_current_pic == ac_z2_pic_count) {
ac_z2_done = 1;
+ adjust_ranges_amiga(cfg);
+ }
}
}
+#include "config_file/config_file.h"
+
#define AC_Z2_BASE 0xE80000
#define AC_Z3_BASE 0xFF000000
#define AC_SIZE (64 * 1024)
ACTYPE_MAPFAST_Z2,
ACTYPE_MAPFAST_Z3,
ACTYPE_A314,
+ ACTYPE_PISCSI,
ACTYPE_NUM,
};
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include "../platforms.h"
+#include <ctype.h>
#include "amiga-autoconf.h"
#include "amiga-registers.h"
+#include "hunk-reloc.h"
+#include "net/pi-net-enums.h"
+#include "net/pi-net.h"
+#include "piscsi/piscsi-enums.h"
+#include "piscsi/piscsi.h"
+#include "platforms/platforms.h"
+#include "platforms/shared/rtc.h"
+#include "rtg/rtg.h"
int handle_register_read_amiga(unsigned int addr, unsigned char type, unsigned int *val);
int handle_register_write_amiga(unsigned int addr, unsigned int value, unsigned char type);
+int init_rtg_data();
+extern int ac_z2_current_pic;
extern int ac_z2_done;
extern int ac_z2_pic_count;
extern int ac_z2_type[AC_PIC_LIMIT];
extern int ac_z2_index[AC_PIC_LIMIT];
+extern int ac_z3_current_pic;
extern int ac_z3_pic_count;
extern int ac_z3_done;
extern int ac_z3_type[AC_PIC_LIMIT];
extern int ac_z3_index[AC_PIC_LIMIT];
+extern int gayle_emulation_enabled;
char *z2_autoconf_id = "z2_autoconf_fast";
char *z2_autoconf_zap_id = "^2_autoconf_fast";
char *z3_autoconf_zap_id = "^3_autoconf_fast";
extern const char *op_type_names[OP_TYPE_NUM];
+extern uint8_t cdtv_mode;
+extern uint8_t rtc_type;
+extern unsigned char cdtv_sram[32 * SIZE_KILO];
-int custom_read_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type) {
+#define min(a, b) (a < b) ? a : b
+#define max(a, b) (a > b) ? a : b
+
+static uint8_t rtg_enabled = 0, piscsi_enabled = 0, pinet_enabled = 0;
+
+extern uint32_t piscsi_base;
+
+extern void stop_cpu_emulation(uint8_t disasm_cur);
+
+inline int custom_read_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type) {
if (!ac_z2_done && addr >= AC_Z2_BASE && addr < AC_Z2_BASE + AC_SIZE) {
if (ac_z2_pic_count == 0) {
ac_z2_done = 1;
}
}
+ if (addr >= piscsi_base && addr < piscsi_base + (64 * SIZE_KILO)) {
+ //printf("[Amiga-Custom] %s read from PISCSI base @$%.8X.\n", op_type_names[type], addr);
+ //stop_cpu_emulation(1);
+ *val = handle_piscsi_read(addr, type);
+ return 1;
+ }
+
return -1;
}
-int custom_write_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int val, unsigned char type) {
+inline int custom_write_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int val, unsigned char type) {
if (!ac_z2_done && addr >= AC_Z2_BASE && addr < AC_Z2_BASE + AC_SIZE) {
if (type == OP_TYPE_BYTE) {
if (ac_z2_pic_count == 0) {
return -1;
}
- printf("Write to Z2 autoconf area.\n");
+ //printf("Write to Z2 autoconf area.\n");
autoconfig_write_memory_8(cfg, addr, val);
return 1;
}
}
}
+ if (addr >= piscsi_base && addr < piscsi_base + (64 * SIZE_KILO)) {
+ //printf("[Amiga-Custom] %s write to PISCSI base @$%.8x: %.8X\n", op_type_names[type], addr, val);
+ handle_piscsi_write(addr, val, type);
+ return 1;
+ }
+
return -1;
}
+void adjust_ranges_amiga(struct emulator_config *cfg) {
+ cfg->mapped_high = 0;
+ cfg->mapped_low = 0;
+ cfg->custom_high = 0;
+ cfg->custom_low = 0;
+
+ // Set up the min/max ranges for mapped reads/writes
+ for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i++) {
+ if (cfg->map_type[i] != MAPTYPE_NONE) {
+ if ((cfg->map_offset[i] != 0 && cfg->map_offset[i] < cfg->mapped_low) || cfg->mapped_low == 0)
+ cfg->mapped_low = cfg->map_offset[i];
+ if (cfg->map_offset[i] + cfg->map_size[i] > cfg->mapped_high)
+ cfg->mapped_high = cfg->map_offset[i] + cfg->map_size[i];
+ }
+ }
+
+ if (ac_z2_pic_count && !ac_z2_done) {
+ if (cfg->custom_low == 0)
+ cfg->custom_low = AC_Z2_BASE;
+ else
+ cfg->custom_low = min(cfg->custom_low, AC_Z2_BASE);
+ cfg->custom_high = max(cfg->custom_high, AC_Z2_BASE + AC_SIZE);
+ }
+ if (ac_z3_pic_count && !ac_z3_done) {
+ if (cfg->custom_low == 0)
+ cfg->custom_low = AC_Z3_BASE;
+ else
+ cfg->custom_low = min(cfg->custom_low, AC_Z3_BASE);
+ cfg->custom_high = max(cfg->custom_high, AC_Z3_BASE + AC_SIZE);
+ }
+ if (rtg_enabled) {
+ if (cfg->custom_low == 0)
+ cfg->custom_low = PIGFX_RTG_BASE;
+ else
+ cfg->custom_low = min(cfg->custom_low, PIGFX_RTG_BASE);
+ cfg->custom_high = max(cfg->custom_high, PIGFX_UPPER);
+ }
+ if (piscsi_enabled) {
+ if (cfg->custom_low == 0)
+ cfg->custom_low = PISCSI_OFFSET;
+ else
+ cfg->custom_low = min(cfg->custom_low, PISCSI_OFFSET);
+ cfg->custom_high = max(cfg->custom_high, PISCSI_UPPER);
+ if (piscsi_base != 0) {
+ cfg->custom_low = min(cfg->custom_low, piscsi_base);
+ }
+ }
+ if (pinet_enabled) {
+ if (cfg->custom_low == 0)
+ cfg->custom_low = PINET_OFFSET;
+ else
+ cfg->custom_low = min(cfg->custom_low, PINET_OFFSET);
+ cfg->custom_high = max(cfg->custom_high, PINET_UPPER);
+ }
+
+ printf("Platform custom range: %.8X-%.8X\n", cfg->custom_low, cfg->custom_high);
+ printf("Platform mapped range: %.8X-%.8X\n", cfg->mapped_low, cfg->mapped_high);
+}
+
int setup_platform_amiga(struct emulator_config *cfg) {
- if (cfg) {}
printf("Performing setup for Amiga platform.\n");
+
+ if (strlen(cfg->platform->subsys)) {
+ printf("Subsystem is [%s]\n", cfg->platform->subsys);
+ if (strcmp(cfg->platform->subsys, "4000") == 0 || strcmp(cfg->platform->subsys, "3000") == 0) {
+ printf("Adjusting Gayle accesses for A3000/4000 Kickstart.\n");
+ adjust_gayle_4000();
+ }
+ else if (strcmp(cfg->platform->subsys, "1200") == 0 || strcmp(cfg->platform->subsys, "cd32") == 0) {
+ printf("Adjusting Gayle accesses for A1200/CD32 Kickstart.\n");
+ adjust_gayle_1200();
+ }
+ else if (strcmp(cfg->platform->subsys, "cdtv") == 0) {
+ printf("Configuring platform for CDTV emulation.\n");
+ cdtv_mode = 1;
+ rtc_type = RTC_TYPE_MSM;
+ }
+ }
+ else
+ printf("No sub system specified.\n");
+
// Look for Z2 autoconf Fast RAM by id
int index = get_named_mapped_item(cfg, z2_autoconf_id);
more_z2_fast:;
index = get_named_mapped_item(cfg, z2_autoconf_id);
if (index != -1)
goto more_z2_fast;
-
+
for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i ++) {
// Restore any "zapped" autoconf items so they can be reinitialized if needed.
if (cfg->map_id[i] && strcmp(cfg->map_id[i], z2_autoconf_zap_id) == 0) {
index = get_named_mapped_item(cfg, z3_autoconf_id);
if (index != -1)
goto more_z3_fast;
- for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i ++) {
+ for (int i = 0; i < MAX_NUM_MAPPED_ITEMS; i++) {
if (cfg->map_id[i] && strcmp(cfg->map_id[i], z3_autoconf_zap_id) == 0) {
cfg->map_id[i][0] = z3_autoconf_id[0];
}
}
-
+
+ index = get_named_mapped_item(cfg, "cpu_slot_ram");
+ if (index != -1) {
+ m68k_add_ram_range((uint32_t)cfg->map_offset[index], (uint32_t)cfg->map_high[index], cfg->map_data[index]);
+ }
+
+ adjust_ranges_amiga(cfg);
+
+ if (cdtv_mode) {
+ FILE *in = fopen("data/cdtv.sram", "rb");
+ if (in != NULL) {
+ printf("Loaded CDTV SRAM.\n");
+ fread(cdtv_sram, 32 * SIZE_KILO, 1, in);
+ fclose(in);
+ }
+ }
+
return 0;
}
-void setvar_amiga(char *var, char *val) {
+void setvar_amiga(struct emulator_config *cfg, char *var, char *val) {
if (!var)
return;
if (val && strlen(val) != 0)
set_hard_drive_image_file_amiga(0, val);
}
+ if (strcmp(var, "hdd1") == 0) {
+ if (val && strlen(val) != 0)
+ set_hard_drive_image_file_amiga(1, val);
+ }
+ if (strcmp(var, "cdtv") == 0) {
+ printf("[AMIGA] CDTV mode enabled.\n");
+ cdtv_mode = 1;
+ }
+ if (strcmp(var, "rtg") == 0) {
+ if (init_rtg_data()) {
+ printf("[AMIGA] RTG Enabled.\n");
+ rtg_enabled = 1;
+ adjust_ranges_amiga(cfg);
+ }
+ else
+ printf("[AMIGA} Failed to enable RTG.\n");
+ }
+
+ // PiSCSI stuff
+ if (strcmp(var, "piscsi") == 0) {
+ printf("[AMIGA] PISCSI Interface Enabled.\n");
+ piscsi_enabled = 1;
+ piscsi_init();
+ ac_z2_type[ac_z2_pic_count] = ACTYPE_PISCSI;
+ ac_z2_pic_count++;
+ adjust_ranges_amiga(cfg);
+ }
+ if (piscsi_enabled) {
+ if (strcmp(var, "piscsi0") == 0) {
+ piscsi_map_drive(val, 0);
+ }
+ if (strcmp(var, "piscsi1") == 0) {
+ piscsi_map_drive(val, 1);
+ }
+ if (strcmp(var, "piscsi2") == 0) {
+ piscsi_map_drive(val, 2);
+ }
+ if (strcmp(var, "piscsi3") == 0) {
+ piscsi_map_drive(val, 3);
+ }
+ if (strcmp(var, "piscsi4") == 0) {
+ piscsi_map_drive(val, 4);
+ }
+ if (strcmp(var, "piscsi5") == 0) {
+ piscsi_map_drive(val, 5);
+ }
+ if (strcmp(var, "piscsi6") == 0) {
+ piscsi_map_drive(val, 6);
+ }
+ }
+
+ // Pi-Net stuff
+ if (strcmp(var, "pi-net") == 0) {
+ printf("[AMIGA] PI-NET Interface Enabled.\n");
+ pinet_enabled = 1;
+ pinet_init(val);
+ adjust_ranges_amiga(cfg);
+ }
+
+ // RTC stuff
+ if (strcmp(var, "rtc_type") == 0) {
+ if (val && strlen(val) != 0) {
+ if (strcmp(val, "msm") == 0) {
+ printf("[AMIGA] RTC type set to MSM.\n");
+ rtc_type = RTC_TYPE_MSM;
+ }
+ else {
+ printf("[AMIGA] RTC type set to Ricoh.\n");
+ rtc_type = RTC_TYPE_RICOH;
+ }
+ }
+ }
+}
+
+void handle_reset_amiga(struct emulator_config *cfg) {
+ ac_z3_done = 0;
+ ac_z2_done = 0;
+ ac_z2_current_pic = 0;
+ ac_z3_current_pic = 0;
+
+ if (piscsi_enabled)
+ piscsi_refresh_drives();
+
+ adjust_ranges_amiga(cfg);
+}
+
+void shutdown_platform_amiga(struct emulator_config *cfg) {
+ if (cfg) {}
+ if (cdtv_mode) {
+ FILE *out = fopen("data/cdtv.sram", "wb+");
+ if (out != NULL) {
+ printf("Saving CDTV SRAM.\n");
+ fwrite(cdtv_sram, 32 * SIZE_KILO, 1, out);
+ fclose(out);
+ }
+ else {
+ printf("Failed to write CDTV SRAM to disk.\n");
+ }
+ }
}
void create_platform_amiga(struct platform_config *cfg, char *subsys) {
cfg->custom_read = custom_read_amiga;
cfg->custom_write = custom_write_amiga;
cfg->platform_initial_setup = setup_platform_amiga;
+ cfg->handle_reset = handle_reset_amiga;
+ cfg->shutdown = shutdown_platform_amiga;
cfg->setvar = setvar_amiga;
+ cfg->id = PLATFORM_AMIGA;
if (subsys) {
cfg->subsys = malloc(strlen(subsys) + 1);
strcpy(cfg->subsys, subsys);
+ for (int i = 0; i < strlen(cfg->subsys); i++) {
+ cfg->subsys[i] = tolower(cfg->subsys[i]);
+ }
}
}
-#include "../../Gayle.h"
-#include "../../config_file/config_file.h"
-
-#define GAYLEBASE 0xD80000 // D7FFFF
-#define GAYLESIZE 0x6FFFF
-
-#define CLOCKBASE 0xDC0000
-#define CLOCKSIZE 0x010000
+#include "Gayle.h"
+#include "config_file/config_file.h"
+#include "amiga-registers.h"
uint8_t rtc_emulation_enabled = 1;
+extern int gayle_emulation_enabled;
void configure_rtc_emulation_amiga(uint8_t enabled) {
if (enabled == rtc_emulation_enabled)
}
int handle_register_read_amiga(unsigned int addr, unsigned char type, unsigned int *val) {
- if (!rtc_emulation_enabled && addr >= CLOCKBASE && addr < CLOCKBASE + CLOCKSIZE)
- return -1;
- if (addr >= GAYLEBASE && addr < GAYLEBASE + GAYLESIZE) {
- switch(type) {
- case OP_TYPE_BYTE:
- *val = readGayleB(addr);
- return 1;
- break;
- case OP_TYPE_WORD:
- *val = readGayle(addr);
- return 1;
- break;
- case OP_TYPE_LONGWORD:
- *val = readGayleL(addr);
- return 1;
- break;
- case OP_TYPE_MEM:
+ if (gayle_emulation_enabled) {
+ if (!rtc_emulation_enabled && addr >= CLOCKBASE && addr < CLOCKBASE + CLOCKSIZE)
return -1;
- break;
+ if (addr >= GAYLEBASE && addr < GAYLEBASE + GAYLESIZE) {
+ switch(type) {
+ case OP_TYPE_BYTE:
+ *val = readGayleB(addr);
+ return 1;
+ break;
+ case OP_TYPE_WORD:
+ *val = readGayle(addr);
+ return 1;
+ break;
+ case OP_TYPE_LONGWORD:
+ *val = readGayleL(addr);
+ return 1;
+ break;
+ case OP_TYPE_MEM:
+ return -1;
+ break;
+ }
}
}
return -1;
}
int handle_register_write_amiga(unsigned int addr, unsigned int value, unsigned char type) {
- if (!rtc_emulation_enabled && addr >= CLOCKBASE && addr < CLOCKBASE + CLOCKSIZE)
- return -1;
- if (addr >= GAYLEBASE && addr < GAYLEBASE + GAYLESIZE) {
- switch(type) {
- case OP_TYPE_BYTE:
- writeGayleB(addr, value);
- return 1;
- break;
- case OP_TYPE_WORD:
- writeGayle(addr, value);
- return 1;
- break;
- case OP_TYPE_LONGWORD:
- writeGayleL(addr, value);
- return 1;
- break;
- case OP_TYPE_MEM:
+ if (gayle_emulation_enabled) {
+ if (!rtc_emulation_enabled && addr >= CLOCKBASE && addr < CLOCKBASE + CLOCKSIZE)
return -1;
- break;
+ if (addr >= GAYLEBASE && addr < GAYLEBASE + GAYLESIZE) {
+ switch(type) {
+ case OP_TYPE_BYTE:
+ writeGayleB(addr, value);
+ return 1;
+ break;
+ case OP_TYPE_WORD:
+ writeGayle(addr, value);
+ return 1;
+ break;
+ case OP_TYPE_LONGWORD:
+ writeGayleL(addr, value);
+ return 1;
+ break;
+ case OP_TYPE_MEM:
+ return -1;
+ break;
+ }
}
}
return -1;
void configure_rtc_emulation_amiga(uint8_t enabled);
void set_hard_drive_image_file_amiga(uint8_t index, char *filename);
+int custom_read_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int *val, unsigned char type);
+int custom_write_amiga(struct emulator_config *cfg, unsigned int addr, unsigned int val, unsigned char type);
+
+void adjust_gayle_4000();
+void adjust_gayle_1200();
+
+#define GAYLEBASE 0xD80000
+#define GAYLESIZE 0x070000
+#define GAYLEMASK 0xDF0000
+
+#define CLOCKBASE 0xDC0000
+#define CLOCKSIZE 0x010000
+#define CLOCKMASK 0x00FFFF
/* GARY ADDRESSES */
#define GARY_REG0 0xDE0000
#define GARY_REG4 0xDE1001
#define GARY_REG5 0xDE1002
+#define INTENAR 0xDFF01C
+#define INTREQR 0xDFF01E
+#define INTENA 0xDFF09A
+#define INTREQ 0xDFF09C
+
+#define JOY0DAT 0xDFF00A
+#define JOY1DAT 0xDFF00C
+#define CIAAPRA 0xBFE001
+#define CIAADAT 0xBFEC01
+#define CIAAICR 0xBFED01
+#define POTGOR 0xDFF016
+
/* RAMSEY ADDRESSES */
#define RAMSEY_REG 0xDE0003 /* just a nibble, it should return 0x08 for defaults with 16MB */
#define RAMSEY_ID 0xDE0043 /* Either 0x0D or 0x0F (most recent version) */
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "config_file/config_file.h"
+
+uint8_t dmac_reg_idx = 0;
+uint8_t dmac_reg_values[0xFFFF];
+
+uint8_t cdtv_dmac_reg_idx_read() {
+ return dmac_reg_idx;
+}
+
+/* DMAC Registers
+R 0x06 [B] - Something
+
+ 0x40 [W] - ISTR
+RW 0x42 [W] - CNTR
+
+ 0x80 [L] - WTC
+ 0x84 [L] - ACR
+
+ 0x8E [B] - SASR
+W 0x8F [B] - Something
+ 0x90 - SCMD
+ 0x91 [B] - Something
+ 0x92 [B] - Something?
+RW 0x93 [B] - Something
+
+R 0xA2?[W?] - Some status thing?
+W 0xA4?[W?] - Something
+W 0xA6?[W?] - Something
+W 0xA8?[W?] - Something
+
+ 0xDE [W] - ST_DMA
+ 0xE0 [W] - SP_DMA
+ 0xE2 [W] - CINT
+ 0xE4 [W] - Something
+ 0xE4-0xE5 - Nothing
+ 0xE6 [W] - Flush
+*/
+
+void cdtv_dmac_reg_idx_write(uint8_t value) {
+ dmac_reg_idx = value;
+}
+
+uint32_t cdtv_dmac_read(uint32_t address, uint8_t type) {
+ uint32_t ret = 0;
+
+ switch (type) {
+ case OP_TYPE_BYTE:
+ return dmac_reg_values[address];
+ case OP_TYPE_WORD:
+ return be16toh(*((uint16_t *)&dmac_reg_values[address]));
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+void cdtv_dmac_write(uint32_t address, uint32_t value, uint8_t type) {
+ switch (type) {
+ case OP_TYPE_BYTE:
+ dmac_reg_values[address] = (uint8_t)value;
+ return ;
+ case OP_TYPE_WORD:
+ printf("Help, it's a scary word write.\n");
+ *((uint16_t *)&dmac_reg_values[address]) = htobe16(value);
+ return;
+ }
+}
#include <time.h>
#include <arpa/inet.h>
+#include "config_file/config_file.h"
#include "ide.h"
#define IDE_IDLE 0
#define IDE_CMD 1
#define IDE_DATA_IN 2
#define IDE_DATA_OUT 3
-
+
#define DCR_NIEN 2
#define DCR_SRST 4
#define IDE_CMD_IDENTIFY 0xEC
#define IDE_CMD_SETFEATURES 0xEF
-const uint8_t ide_magic[8] = {
- '1','D','E','D','1','5','C','0'
+const uint8_t ide_magic[9] = {
+ '1','D','E','D','1','5','C','0',0x00
};
static char *charmap(uint8_t v)
struct ide_drive *d = t->drive;
uint16_t cyl;
- if (t->lba4 & DEVH_LBA) {
-/* fprintf(stderr, "XLATE LBA %02X:%02X:%02X:%02X\n",
+ if (d->controller->lba4 & DEVH_LBA) {
+/* fprintf(stderr, "XLATE LBA %02X:%02X:%02X:%02X\n",
t->lba4, t->lba3, t->lba2, t->lba1);*/
if (d->lba)
- return 2 + (((t->lba4 & DEVH_HEAD) << 24) | (t->lba3 << 16) | (t->lba2 << 8) | t->lba1);
+ return ((d->header_present) ? 2 : 0) + (((t->drive->controller->lba4 & DEVH_HEAD) << 24) | (t->drive->controller->lba3 << 16) | (t->drive->controller->lba2 << 8) | t->drive->controller->lba1);
ide_fault(d, "LBA on non LBA drive");
}
/* Some well known software asks for 0/0/0 when it means 0/0/1. Drives appear
to interpret sector 0 as sector 1 */
- if (t->lba1 == 0) {
+ if (t->drive->controller->lba1 == 0) {
fprintf(stderr, "[Bug: request for sector offset 0].\n");
- t->lba1 = 1;
+ t->drive->controller->lba1 = 1;
}
- cyl = (t->lba3 << 8) | t->lba2;
+ cyl = (t->drive->controller->lba3 << 8) | t->drive->controller->lba2;
/* fprintf(stderr, "(H %d C %d S %d)\n", t->lba4 & DEVH_HEAD, cyl, t->lba1); */
- if (t->lba1 == 0 || t->lba1 > d->sectors || t->lba4 >= d->heads || cyl >= d->cylinders) {
+ if (t->drive->controller->lba1 == 0 || t->drive->controller->lba1 > d->sectors || t->drive->controller->lba4 >= d->heads || cyl >= d->cylinders) {
return -1;
}
/* Sector 1 is first */
/* Images generally go cylinder/head/sector. This also matters if we ever
implement more advanced geometry setting */
- return 1 + ((cyl * d->heads) + (t->lba4 & DEVH_HEAD)) * d->sectors + t->lba1;
+ //off_t ret = ((d->header_present) ? 1 : -1) + ((cyl * d->heads) + (t->drive->controller->lba4 & DEVH_HEAD)) * d->sectors + t->drive->controller->lba1;
+ //printf("Non-LBA xlate block %lX.\n", ret);
+ //printf("Cyl: %d Heads: %d Sectors: %d\n", cyl, d->heads, d->sectors);
+ //printf("LBA1: %.2X LBA2: %.2X LBA3: %.2X LBA4: %.2X\n", t->drive->controller->lba1, t->drive->controller->lba2, t->drive->controller->lba3, t->drive->controller->lba4);
+
+ return ((d->header_present) ? 1 : -1) + ((cyl * d->heads) + (t->drive->controller->lba4 & DEVH_HEAD)) * d->sectors + t->drive->controller->lba1;
}
/* Indicate the drive is ready */
static void edd_setup(struct ide_taskfile *tf)
{
tf->error = 0x01; /* All good */
- tf->lba1 = 0x01; /* EDD always updates drive 0 */
- tf->lba2 = 0x00;
- tf->lba3 = 0x00;
- tf->lba4 = 0x00;
+ tf->drive->controller->lba1 = 0x01; /* EDD always updates drive 0 */
+ tf->drive->controller->lba2 = 0x00;
+ tf->drive->controller->lba3 = 0x00;
+ tf->drive->controller->lba4 = 0x00;
tf->count = 0x01;
ready(tf);
}
c->drive[1].taskfile.status = ST_DRDY;
c->drive[1].eightbit = 0;
}
+ if (c->selected != 0) {
+ }
c->selected = 0;
}
c->drive[0].taskfile.status |= ST_BSY;
if (c->drive[1].present)
c->drive[1].taskfile.status |= ST_BSY;
-}
+}
static void ide_srst_end(struct ide_controller *c)
{
{
struct ide_drive *d = tf->drive;
/* We only support the current mapping */
- if (tf->count != d->sectors || (tf->lba4 & DEVH_HEAD) + 1 != d->heads) {
+ if (tf->count != d->sectors || (tf->drive->controller->lba4 & DEVH_HEAD) + 1 != d->heads) {
tf->status |= ST_ERR;
tf->error |= ERR_ABRT;
tf->drive->failed = 1; /* Report ID NF until fixed */
static void ide_set_error(struct ide_drive *d)
{
- d->taskfile.lba4 &= ~DEVH_HEAD;
+ d->controller->lba4 &= ~DEVH_HEAD;
- if (d->taskfile.lba4 & DEVH_LBA) {
- d->taskfile.lba1 = d->offset & 0xFF;
- d->taskfile.lba2 = (d->offset >> 8) & 0xFF;
- d->taskfile.lba3 = (d->offset >> 16) & 0xFF;
- d->taskfile.lba4 |= (d->offset >> 24) & DEVH_HEAD;
+ if (d->controller->lba4 & DEVH_LBA) {
+ d->controller->lba1 = d->offset & 0xFF;
+ d->controller->lba2 = (d->offset >> 8) & 0xFF;
+ d->controller->lba3 = (d->offset >> 16) & 0xFF;
+ d->controller->lba4 |= (d->offset >> 24) & DEVH_HEAD;
} else {
- d->taskfile.lba1 = d->offset % d->sectors + 1;
+ d->controller->lba1 = d->offset % d->sectors + 1;
d->offset /= d->sectors;
- d->taskfile.lba4 |= d->offset / (d->cylinders * d->sectors);
+ d->controller->lba4 |= d->offset / (d->cylinders * d->sectors);
d->offset %= (d->cylinders * d->sectors);
- d->taskfile.lba2 = d->offset & 0xFF;
- d->taskfile.lba3 = (d->offset >> 8) & 0xFF;
+ d->controller->lba2 = d->offset & 0xFF;
+ d->controller->lba3 = (d->offset >> 8) & 0xFF;
}
d->taskfile.count = d->length;
d->taskfile.status |= ST_ERR;
if (d->dptr == d->data + 512) {
if (ide_write_sector(d) < 0) {
ide_set_error(d);
- return;
+ return;
}
d->length--;
d->intrq = 1;
t->status |= ST_BSY;
t->error = 0;
t->drive->state = IDE_CMD;
-
+
/* We could complete with delays but don't do so yet */
switch(t->command) {
case IDE_CMD_EDD: /* 0x90 */
case ide_sec_count:
return t->count;
case ide_lba_low:
- return t->lba1;
+ return c->lba1;
case ide_lba_mid:
- return t->lba2;
+ return c->lba2;
case ide_lba_hi:
- return t->lba3;
+ return c->lba3;
case ide_lba_top:
- return t->lba4;
+ return c->lba4 | ((c->selected) ? 0x10 : 0x00);
case ide_status_r:
d->intrq = 0; /* Acked */
case ide_altst_r:
}
}
+ uint8_t ve;
+
switch(r) {
case ide_data:
ide_data_out(d, v, 1);
t->count = v;
break;
case ide_lba_low:
- t->lba1 = v;
+ c->lba1 = v;
break;
case ide_lba_mid:
- t->lba2 = v;
+ c->lba2 = v;
break;
case ide_lba_hi:
- t->lba3 = v;
+ c->lba3 = v;
break;
case ide_lba_top:
c->selected = (v & DEVH_DEV) ? 1 : 0;
- c->drive[c->selected].taskfile.lba4 = v & (DEVH_HEAD|DEVH_DEV|DEVH_LBA);
+ c->lba4 = v & (DEVH_HEAD|/*DEVH_DEV|*/DEVH_LBA);
break;
case ide_command_w:
- t->command = v;
+ t->command = v;
ide_issue_command(t);
break;
case ide_devctrl_w:
d->heads = d->identify[3];
d->sectors = d->identify[6];
d->cylinders = le16(d->identify[1]);
+ d->header_present = 1;
if (d->identify[49] & le16(1 << 9))
d->lba = 1;
else
return 0;
}
+// Attach a headerless HDD image to the controller
+int ide_attach_hdf(struct ide_controller *c, int drive, int fd)
+{
+ struct ide_drive *d = &c->drive[drive];
+ if (d->present) {
+ printf("[IDE/HDL] Drive already attached.\n");
+ return -1;
+ }
+
+ d->fd = fd;
+ d->present = 1;
+ d->lba = 0;
+
+ d->heads = 255;
+ d->sectors = 63;
+ d->header_present = 0;
+
+ uint64_t file_size = lseek(fd, 0, SEEK_END);
+ lseek(fd, 1024, SEEK_SET);
+
+ if (file_size < 504 * SIZE_MEGA) {
+ d->heads = 16;
+ }
+ else if (file_size < 1008 * SIZE_MEGA) {
+ d->heads = 32;
+ }
+ else if (file_size < 2016 * SIZE_MEGA) {
+ d->heads = 64;
+ }
+ else if (file_size < (uint64_t)4032 * SIZE_MEGA) {
+ d->heads = 128;
+ }
+
+ d->cylinders = (file_size / 512) / (d->sectors * d->heads);
+
+ printf("[IDE/HDL] Cylinders: %d Heads: %d Sectors: %d\n", d->cylinders, d->heads, d->sectors);
+
+ if (file_size >= 4 * 1000 * 1000) {
+ d->lba = 1;
+ }
+
+ ide_make_ident(d->cylinders, d->heads, d->sectors, "PISTORM HDD IMAGE v0.1", d->identify);
+
+ return 0;
+}
+
/*
* Detach an IDE device from the interface (not hot pluggable)
*/
/*
* Free up and release and IDE controller
- */
+ */
void ide_free(struct ide_controller *c)
{
if (c->drive[0].present)
}
if (reg == ide_data)
d |= (c->data_latch << 8);
- ide_write16(c, reg, d);
+ ide_write16(c, reg, d);
}
static void make_ascii(uint16_t *p, const char *t, int len)
*d = d[1];
d[1] = c;
d += 2;
- }
+ }
}
static void make_serial(uint16_t *p)
make_ascii(p, buf, 20);
}
+int ide_make_ident(uint16_t c, uint8_t h, uint8_t s, char *name, uint16_t *target)
+{
+ uint16_t *ident = target;
+ uint32_t sectors;
+
+ memset(ident, 0, 512);
+ memcpy(ident, ide_magic, 8);
+
+ memset(ident, 0, 8);
+ ident[0] = le16((1 << 15) | (1 << 6)); /* Non removable */
+ make_serial(ident + 10);
+ ident[47] = 0; /* no read multi for now */
+ ident[51] = le16(240 /* PIO2 */ << 8); /* PIO cycle time */
+ ident[53] = le16(1); /* Geometry words are valid */
+
+ make_ascii(ident + 23, "A001.001", 8);
+ make_ascii(ident + 27, name, 40);
+ ident[49] = le16(1 << 9); /* LBA */
+
+ ident[1] = le16(c);
+ ident[3] = le16(h);
+ ident[6] = le16(s);
+ ident[54] = ident[1];
+ ident[55] = ident[3];
+ ident[56] = ident[6];
+ sectors = c * h * s;
+ ident[57] = le16(sectors & 0xFFFF);
+ ident[58] = le16(sectors >> 16);
+ ident[60] = ident[57];
+ ident[61] = ident[58];
+
+ return 0;
+}
+
int ide_make_drive(uint8_t type, int fd)
{
uint8_t s, h;
if (type < 1 || type > MAX_DRIVE_TYPE)
return -2;
-
+
memset(ident, 0, 512);
memcpy(ident, ide_magic, 8);
if (write(fd, ident, 512) != 512)
ident[47] = 0; /* no read multi for now */
ident[51] = le16(240 /* PIO2 */ << 8); /* PIO cycle time */
ident[53] = le16(1); /* Geometry words are valid */
-
+
switch(type) {
case ACME_ROADRUNNER:
/* 504MB drive with LBA support */
make_ascii(ident + 23, "A001.001", 8);
make_ascii(ident + 27, "ACME ROADRUNNER v0.1", 40);
ident[49] = le16(1 << 9); /* LBA */
- break;
+ break;
case ACME_ULTRASONICUS:
/* 40MB drive with LBA support */
c = 977;
s = 16;
make_ascii(ident + 23, "A001.001", 8);
make_ascii(ident + 27, "ACME COYOTE v0.1", 40);
- break;
+ break;
case ACME_ACCELLERATTI:
c = 1024;
h = 16;
ident[61] = ident[58];
if (write(fd, ident, 512) != 512)
return -1;
-
+
memset(ident, 0xE5, 512);
while(sectors--)
if (write(fd, ident, 512) != 512)
- return -1;
+ return -1;
return 0;
}
#define ide_lba_mid 4
#define ide_cyl_hi 5
#define ide_lba_hi 5
-#define ide_dev_head 6
+#define ide_dev_head 6
#define ide_lba_top 6
#define ide_status_r 7
#define ide_command_w 7
uint8_t error;
uint8_t feature;
uint8_t count;
- uint8_t lba1;
- uint8_t lba2;
- uint8_t lba3;
- uint8_t lba4;
uint8_t status;
uint8_t command;
uint8_t devctrl;
int fd;
off_t offset;
int length;
+ uint8_t header_present;
};
struct ide_controller {
int selected;
const char *name;
uint16_t data_latch;
+ uint8_t lba1;
+ uint8_t lba2;
+ uint8_t lba3;
+ uint8_t lba4;
};
//extern ide_controller idectrl;
-extern const uint8_t ide_magic[8];
+extern const uint8_t ide_magic[9];
void ide_reset_begin(struct ide_controller *c);
uint8_t ide_read8(struct ide_controller *c, uint8_t r);
struct ide_controller *ide_allocate(const char *name);
int ide_attach(struct ide_controller *c, int drive, int fd);
+int ide_attach_hdf(struct ide_controller *c, int drive, int fd);
+int ide_make_ident(uint16_t c, uint8_t h, uint8_t s, char *name, uint16_t *target);
void ide_detach(struct ide_drive *d);
void ide_free(struct ide_controller *c);
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <endian.h>
+#include "hunk-reloc.h"
+
+#ifdef FAKESTORM
+#define lseek64 lseek
+#endif
+
+#define DEBUG(...)
+//#define DEBUG printf
+
+#define BE(val) be32toh(val)
+#define BE16(val) be16toh(val)
+
+#define READLW(a, b) fread(&a, 4, 1, b); a = be32toh(a);
+#define READW(a, b) fread(&a, 2, 1, b); a = be16toh(a);
+
+uint32_t lw = 0;
+static uint32_t file_offset = 0, add_size = 0;
+
+char *hunk_id_name(uint32_t index) {
+ switch (index) {
+ case HUNKTYPE_HEADER:
+ return "HUNK_HEADER";
+ case HUNKTYPE_CODE:
+ return "HUNK_CODE";
+ case HUNKTYPE_HUNK_RELOC32:
+ return "HUNK_RELOC32";
+ case HUNKTYPE_SYMBOL:
+ return "HUNK_SYMBOL";
+ case HUNKTYPE_BSS:
+ return "HUNK_BSS";
+ case HUNKTYPE_DATA:
+ return "HUNK_DATA";
+ case HUNKTYPE_END:
+ return "HUNK_END";
+ default:
+ return "UNKNOWN HUNK TYPE";
+ }
+}
+
+int process_hunk(uint32_t index, struct hunk_info *info, FILE *f, struct hunk_reloc *r) {
+ if (!f)
+ return -1;
+
+ uint32_t discard = 0, cur_hunk = 0, offs32 = 0;
+
+ switch (index) {
+ case HUNKTYPE_HEADER:
+ DEBUG("Processing hunk header.\n");
+ do {
+ READLW(discard, f);
+ if (discard) {
+ info->libnames[info->num_libs] = malloc(discard * 4);
+ fread(info->libnames[info->num_libs], discard, 4, f);
+ info->num_libs++;
+ }
+ } while (discard);
+
+ READLW(info->table_size, f);
+ DEBUG("Table size: %d\n", info->table_size);
+ READLW(info->first_hunk, f);
+ READLW(info->last_hunk, f);
+ info->num_hunks = (info->last_hunk - info->first_hunk) + 1;
+ DEBUG("First: %d Last: %d Num: %d\n", info->first_hunk, info->last_hunk, info->num_hunks);
+ info->hunk_sizes = malloc(info->num_hunks * 4);
+ info->hunk_offsets = malloc(info->num_hunks * 4);
+ for (uint32_t i = 0; i < info->table_size; i++) {
+ READLW(info->hunk_sizes[i], f);
+ DEBUG("Hunk %d: %d (%.8X)\n", i, info->hunk_sizes[i] * 4, info->hunk_sizes[i] * 4);
+ }
+ return 0;
+ break;
+ case HUNKTYPE_CODE:
+ DEBUG("Hunk %d: CODE.\n", info->current_hunk);
+ READLW(discard, f);
+ info->hunk_offsets[info->current_hunk] = ftell(f) - file_offset;
+ DEBUG("Code hunk size: %d (%.8X)\n", discard * 4, discard * 4);
+ fseek(f, discard * 4, SEEK_CUR);
+ return 0;
+ break;
+ case HUNKTYPE_HUNK_RELOC32:
+ DEBUG("Hunk %d: RELOC32.\n", info->current_hunk);
+ DEBUG("Processing Reloc32 hunk.\n");
+ do {
+ READLW(discard, f);
+ if (discard && discard != 0xFFFFFFFF) {
+ READLW(cur_hunk, f);
+ DEBUG("Relocating %d offsets pointing to hunk %d.\n", discard, cur_hunk);
+ for(uint32_t i = 0; i < discard; i++) {
+ READLW(offs32, f);
+ DEBUG("#%d: @%.8X in hunk %d\n", i + 1, offs32, cur_hunk);
+ r[info->reloc_hunks].offset = offs32;
+ r[info->reloc_hunks].src_hunk = info->current_hunk;
+ r[info->reloc_hunks].target_hunk = cur_hunk;
+ info->reloc_hunks++;
+ }
+ }
+ } while(discard);
+ return 0;
+ break;
+ case HUNKTYPE_SYMBOL:
+ DEBUG("Hunk %d: SYMBOL.\n", info->current_hunk);
+ DEBUG("Processing Symbol hunk.\n");
+ READLW(discard, f);
+ do {
+ if (discard) {
+ char sstr[256];
+ memset(sstr, 0x00, 256);
+ fread(sstr, discard, 4, f);
+ READLW(discard, f);
+ DEBUG("Symbol: %s - %.8X\n", sstr, discard);
+ }
+ READLW(discard, f);
+ } while (discard);
+ return 0;
+ break;
+ case HUNKTYPE_BSS:
+ DEBUG("Hunk %d: BSS.\n", info->current_hunk);
+ READLW(discard, f);
+ info->hunk_offsets[info->current_hunk] = ftell(f) - file_offset;
+ DEBUG("Skipping BSS hunk. Size: %d\n", discard * 4);
+ add_size += (discard * 4);
+ return 0;
+ case HUNKTYPE_DATA:
+ DEBUG("Hunk %d: DATA.\n", info->current_hunk);
+ READLW(discard, f);
+ info->hunk_offsets[info->current_hunk] = ftell(f) - file_offset;
+ DEBUG("Skipping data hunk. Size: %d.\n", discard * 4);
+ fseek(f, discard * 4, SEEK_CUR);
+ return 0;
+ break;
+ case HUNKTYPE_END:
+ DEBUG("END: Ending hunk %d.\n", info->current_hunk);
+ info->current_hunk++;
+ return 0;
+ break;
+ default:
+ DEBUG("Unknown hunk type %.8X! Can't process!\n", index);
+ break;
+ }
+
+ return -1;
+}
+
+void reloc_hunk(struct hunk_reloc *h, uint8_t *buf, struct hunk_info *i) {
+ uint32_t rel = i->hunk_offsets[h->target_hunk];
+ uint32_t *src_ptr = (uint32_t *)(&buf[i->hunk_offsets[h->src_hunk] + h->offset]);
+
+ uint32_t src = be32toh(*src_ptr);
+ uint32_t dst = src + i->base_offset + rel;
+ DEBUG("%.8X -> %.8X\n", src, dst);
+ *src_ptr = htobe32(dst);
+}
+
+void process_hunks(FILE *in, struct hunk_info *h_info, struct hunk_reloc *r, uint32_t offset) {
+ READLW(lw, in);
+ DEBUG("Hunk ID: %.8X (%s)\n", lw, hunk_id_name(lw));
+
+ file_offset = offset;
+ add_size = 0;
+
+ while (!feof(in) && process_hunk(lw, h_info, in, r) != -1) {
+ READLW(lw, in);
+ if (feof(in)) goto end_parse;
+ DEBUG("Hunk ID: %.8X (%s)\n", lw, hunk_id_name(lw));
+ DEBUG("File pos: %.8lX\n", ftell(in) - file_offset);
+ }
+ end_parse:;
+ DEBUG("Done processing hunks.\n");
+}
+
+void reloc_hunks(struct hunk_reloc *r, uint8_t *buf, struct hunk_info *h_info) {
+ DEBUG("Relocating %d offsets.\n", h_info->reloc_hunks);
+ for (uint32_t i = 0; i < h_info->reloc_hunks; i++) {
+ DEBUG("Relocating offset %d.\n", i);
+ reloc_hunk(&r[i], buf, h_info);
+ }
+ DEBUG("Done relocating offsets.\n");
+}
+
+struct LoadSegBlock {
+ uint32_t lsb_ID;
+ uint32_t lsb_SummedLongs;
+ int32_t lsb_ChkSum;
+ uint32_t lsb_HostID;
+ uint32_t lsb_Next;
+ uint32_t lsb_LoadData[123]; // Assumes 512 byte blocks
+};
+#define LOADSEG_IDENTIFIER 0x4C534547
+
+int load_lseg(int fd, uint8_t **buf_p, struct hunk_info *i, struct hunk_reloc *relocs) {
+ if (fd == -1)
+ return -1;
+
+ uint8_t *block = malloc(512);
+ uint32_t next_blk = 0;
+ struct LoadSegBlock *lsb = (struct LoadSegBlock *)block;
+
+ read(fd, block, 512);
+ if (BE(lsb->lsb_ID) != LOADSEG_IDENTIFIER) {
+ DEBUG("[LOAD_LSEG] Attempted to load a non LSEG-block: %.8X", BE(lsb->lsb_ID));
+ goto fail;
+ }
+
+ char *filename = "data/lsegout.bin";
+ FILE *out = fopen(filename, "wb+");
+
+ DEBUG("[LOAD_LSEG] LSEG data:\n");
+ DEBUG("[LOAD_LSEG] Longs: %d HostID: %d\n", BE(lsb->lsb_SummedLongs), BE(lsb->lsb_HostID));
+ DEBUG("[LOAD_LSEG] Next: %d LoadData: %p\n", BE(lsb->lsb_Next), (void *)lsb->lsb_LoadData);
+ next_blk = BE(lsb->lsb_Next);
+ do {
+ next_blk = BE(lsb->lsb_Next);
+ fwrite(lsb->lsb_LoadData, 4, 123, out);
+ lseek64(fd, next_blk * 512, SEEK_SET);
+ read(fd, block, 512);
+ } while (next_blk != 0xFFFFFFFF);
+
+ uint32_t file_size = ftell(out);
+ fseek(out, 0, SEEK_SET);
+ uint8_t *buf = malloc(file_size + 1024);
+ fread(buf, file_size, 1, out);
+ fseek(out, 0, SEEK_SET);
+ process_hunks(out, i, relocs, 0x0);
+
+ fclose(out);
+ *buf_p = buf;
+ i->byte_size = file_size;
+ i->alloc_size = file_size + add_size;
+
+ return 0;
+
+fail:;
+ if (block)
+ free(block);
+
+ return -1;
+}
--- /dev/null
+#ifndef _HUNK_RELOC_H
+#define _HUNK_RELOC_H
+
+struct hunk_reloc {
+ uint32_t src_hunk;
+ uint32_t target_hunk;
+ uint32_t offset;
+};
+
+struct hunk_info {
+ uint16_t current_hunk;
+ uint16_t num_libs;
+ uint8_t *libnames[256];
+ uint32_t table_size, byte_size, alloc_size;
+ uint32_t base_offset;
+ uint32_t first_hunk, last_hunk, num_hunks;
+ uint32_t reloc_hunks;
+ uint32_t *hunk_offsets;
+ uint32_t *hunk_sizes;
+};
+
+enum hunk_types {
+ HUNKTYPE_CODE = 0x3E9,
+ HUNKTYPE_DATA = 0x3EA,
+ HUNKTYPE_BSS = 0x3EB,
+ HUNKTYPE_HUNK_RELOC32 = 0x3EC,
+ HUNKTYPE_SYMBOL = 0x3F0,
+ HUNKTYPE_END = 0x3F2,
+ HUNKTYPE_HEADER = 0x3F3,
+};
+
+int process_hunk(uint32_t index, struct hunk_info *info, FILE *f, struct hunk_reloc *r);
+int load_lseg(int fd, uint8_t **buf_p, struct hunk_info *i, struct hunk_reloc *relocs);
+
+void reloc_hunk(struct hunk_reloc *h, uint8_t *buf, struct hunk_info *i);
+void process_hunks(FILE *in, struct hunk_info *h_info, struct hunk_reloc *r, uint32_t offset);
+void reloc_hunks(struct hunk_reloc *r, uint8_t *buf, struct hunk_info *h_info);
+
+#endif /* _HUNK_RELOC_H */
--- /dev/null
+m68k-amigaos-gcc -m68020 -O2 -o pi-net.device -ramiga-dev -noixemul -fbaserel pi-net-amiga.c -ldebug -lamiga
--- /dev/null
+#include <exec/resident.h>
+#include <exec/memory.h>
+#include <exec/alerts.h>
+#include <exec/io.h>
+#include <exec/execbase.h>
+#include <libraries/expansion.h>
+#include <dos/filehandler.h>
+#include <proto/exec.h>
+#include <proto/utility.h>
+#include <proto/dos.h>
+#include <proto/expansion.h>
+#include <clib/exec_protos.h>
+#include <clib/alib_protos.h>
+#include <dos/dostags.h>
+#include <utility/tagitem.h>
+#include <exec/lists.h>
+#include <exec/errors.h>
+#include <exec/interrupts.h>
+#include <exec/tasks.h>
+#include <hardware/intbits.h>
+#include <string.h>
+#include "sana2.h"
+#include "../pi-net-enums.h"
+
+#include <clib/debug_protos.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#define WRITESHORT(cmd, val) *(unsigned short *)((unsigned long)(PINET_OFFSET + cmd)) = val;
+#define WRITELONG(cmd, val) *(unsigned long *)((unsigned long)(PINET_OFFSET + cmd)) = val;
+#define WRITEBYTE(cmd, val) *(unsigned char *)((unsigned long)(PINET_OFFSET + cmd)) = val;
+
+#define READBYTE(cmd, var) var = *(volatile unsigned char *)(PINET_OFFSET + cmd);
+#define READSHORT(cmd, var) var = *(volatile unsigned short *)(PINET_OFFSET + cmd);
+#define READLONG(cmd, var) var = *(volatile unsigned long *)(PINET_OFFSET + cmd);
+
+//typedef BOOL (*BMFunc)(void* a __asm("a0"), void* b __asm("a1"), long c __asm("d0"));
+
+typedef struct BufferManagement
+{
+ struct MinNode bm_Node;
+ BOOL (*bm_CopyFromBuffer)(void* a __asm("a0"), void* b __asm("a1"), long c __asm("d0"));
+ BOOL (*bm_CopyToBuffer)(void* a __asm("a0"), void* b __asm("a1"), long c __asm("d0"));
+} BufferManagement;
+
+#pragma pack(4)
+struct pinet_base {
+ struct Device* pi_dev;
+ struct Unit unit;
+ uint8_t MAC[6];
+ uint8_t IP[4];
+
+ struct List read_list;
+ struct SignalSemaphore read_list_sem;
+};
+
+struct ExecBase* SysBase = NULL;
+
+const char DevName[] = "pi-net.device";
+const char DevIdString[] = "Pi-NET 0.1";
+
+const UWORD DevVersion = 1;
+const UWORD DevRevision = 0;
+
+#include "stabs.h"
+
+struct pinet_base *dev_base = NULL;
+
+struct WBStartup *_WBenchMsg = NULL;
+
+//#define exit(...)
+//#define debug(...)
+//#define KPrintF(...)
+
+uint32_t __UserDevInit(struct Device* dev) {
+ uint8_t *p;
+ uint32_t i;
+ int32_t ok;
+
+ SysBase = *(struct ExecBase **)4L;
+
+ KPrintF("Initializing net device.\n");
+
+ dev_base = AllocMem(sizeof(struct pinet_base), MEMF_PUBLIC | MEMF_CLEAR);
+ dev_base->pi_dev = dev;
+
+ KPrintF("Grabbing MAC.\n");
+ for (int i = 0; i < 6; i++) {
+ READBYTE((PINET_CMD_MAC + i), dev_base->MAC[i]);
+ }
+ KPrintF("Grabbing IP.\n");
+ for (int i = 0; i < 4; i++) {
+ READBYTE((PINET_CMD_IP + i), dev_base->IP[i]);
+ }
+
+ return (uint32_t)dev;
+}
+
+uint32_t __UserDevCleanup(void) {
+ KPrintF("Cleaning up.\n");
+ FreeMem(dev_base, sizeof(struct pinet_base));
+ return 0;
+}
+
+uint32_t __UserDevOpen(struct IORequest *io, uint32_t num, uint32_t flags) {
+ struct IOSana2Req *ioreq = (struct IOSana2Req *)io;
+ uint32_t ok = 0, ret = IOERR_OPENFAIL;
+ struct BufferManagement *bm;
+
+ KPrintF("Opening net device %ld.\n", num);
+ dev_base->unit.unit_OpenCnt++;
+
+ if (num == 0 && dev_base->unit.unit_OpenCnt == 1) {
+ //KPrintF("Trying to alloc buffer management.\n");
+ //if ((bm = (struct BufferManagement*)AllocVec(sizeof(struct BufferManagement), MEMF_CLEAR | MEMF_PUBLIC))) {
+ //KPrintF("Setting up buffer copy funcs (1).\n");
+ //bm->bm_CopyToBuffer = (BOOL *)GetTagData(S2_CopyToBuff, 0, (struct TagItem *)ioreq->ios2_BufferManagement);
+ //KPrintF("Setting up buffer copy funcs (2).\n");
+ //bm->bm_CopyFromBuffer = (BOOL *)GetTagData(S2_CopyFromBuff, 0, (struct TagItem *)ioreq->ios2_BufferManagement);
+
+ KPrintF("Doing more things.\n");
+ ioreq->ios2_BufferManagement = NULL;//(VOID *)bm;
+ ioreq->ios2_Req.io_Error = 0;
+ ioreq->ios2_Req.io_Unit = (struct Unit *)&dev_base->unit;
+ ioreq->ios2_Req.io_Device = (struct Device *)dev_base->pi_dev;
+
+ KPrintF("New list.\n");
+
+ NewList(&dev_base->read_list);
+ InitSemaphore(&dev_base->read_list_sem);
+
+ ret = 0;
+ ok = 1;
+ //}
+ }
+
+ if (ret == IOERR_OPENFAIL) {
+ KPrintF("Failed to open device. Already open?\n");
+ }
+ else {
+ KPrintF("Device opened, yay.\n");
+ }
+ ioreq->ios2_Req.io_Message.mn_Node.ln_Type = NT_REPLYMSG;
+
+ KPrintF("Opened device, return code: %ld\n", ret);
+
+ return ret;
+}
+
+uint32_t __UserDevClose(struct IORequest *io) {
+ return 0;
+}
+
+uint32_t pinet_read_frame(struct IOSana2Req *ioreq) {
+ uint32_t datasize;
+ uint8_t *frame_ptr;
+ uint8_t broadcast;
+ uint32_t err = 0;
+ struct BufferManagement *bm;
+
+ /*uint8_t* frm = (uint8_t *)(PINET_OFFSET + PINET_CMD_FRAME);
+ uint32_t sz = ((uint32_t)frm[0] << 8) | ((uint32_t)frm[1]);
+ uint32_t ser = ((uint32_t)frm[2] << 8) | ((uint32_t)frm[3]);
+ uint16_t tp = ((uint16_t)frm[16] << 8) | ((uint16_t)frm[17]);
+
+ if (req->ios2_Req.io_Flags & SANA2IOF_RAW) {
+ frame_ptr = frm + 4;
+ datasize = sz;
+ req->ios2_Req.io_Flags = SANA2IOF_RAW;
+ }
+ else {
+ frame_ptr = frm + 4 + ETH_HDR_SIZE;
+ datasize = sz - ETH_HDR_SIZE;
+ req->ios2_Req.io_Flags = 0;
+ }
+
+ req->ios2_DataLength = datasize;
+
+ //D(("datasize: %lx\n",datasize));
+ //D(("frame_ptr: %lx\n",frame_ptr));
+ //D(("ios2_Data: %lx\n",req->ios2_Data));
+ //D(("bufmgmt: %lx\n",req->ios2_BufferManagement));
+
+ // copy frame to device user (probably tcp/ip system)
+ bm = (struct BufferManagement *)req->ios2_BufferManagement;
+ if (!(*bm->bm_CopyToBuffer)(req->ios2_Data, frame_ptr, datasize)) {
+ //D(("rx copybuf error\n"));
+ req->ios2_Req.io_Error = S2ERR_SOFTWARE;
+ req->ios2_WireError = S2WERR_BUFF_ERROR;
+ err = 1;
+ }
+ else {
+ req->ios2_Req.io_Error = req->ios2_WireError = 0;
+ err = 0;
+ }
+
+ memcpy(req->ios2_SrcAddr, frame+4+6, HW_ADDRFIELDSIZE);
+ memcpy(req->ios2_DstAddr, frame+4, HW_ADDRFIELDSIZE);
+
+ //D(("RXSZ %ld\n",(LONG)sz));
+ //D(("RXPT %ld\n",(LONG)tp));
+
+ //D(("RXSER %ld\n",(LONG)ser));
+ //D(("RXDST %lx...\n",*((ULONG*)(req->ios2_DstAddr))));
+ //D(("RXSRC %lx\n",*((ULONG*)(req->ios2_SrcAddr))));
+ //D(("RXSRC %lx\n",*((ULONG*)(frame_ptr))));
+
+ broadcast = TRUE;
+ for (int i=0; i<HW_ADDRFIELDSIZE; i++) {
+ if (frame[i+4] != 0xff) {
+ broadcast = FALSE;
+ break;
+ }
+ }
+ if (broadcast) {
+ req->ios2_Req.io_Flags |= SANA2IOF_BCAST;
+ }
+
+ req->ios2_PacketType = tp;*/
+
+ return err;
+}
+
+void pinet_write_frame(struct IOSana2Req *ioreq) {
+
+}
+
+void exit(int status) { }
+
+ADDTABL_1(__BeginIO,a1);
+void __BeginIO(struct IORequest *io) {
+ struct IOSana2Req *ioreq = (struct IOSana2Req *)io;
+ ULONG unit = (ULONG)ioreq->ios2_Req.io_Unit;
+ int mtu;
+
+ ioreq->ios2_Req.io_Message.mn_Node.ln_Type = NT_MESSAGE;
+ ioreq->ios2_Req.io_Error = S2ERR_NO_ERROR;
+ ioreq->ios2_WireError = S2WERR_GENERIC_ERROR;
+
+ //D(("BeginIO command %ld unit %ld\n",(LONG)ioreq->ios2_Req.io_Command,unit));
+
+ switch( ioreq->ios2_Req.io_Command ) {
+ case CMD_READ:
+ KPrintF("Read\n");
+ if (pinet_read_frame(ioreq) != 0) {
+ ioreq->ios2_Req.io_Error = S2ERR_BAD_ARGUMENT;
+ ioreq->ios2_WireError = S2WERR_BUFF_ERROR;
+ }
+ ioreq = NULL;
+ break;
+ case S2_BROADCAST:
+ KPrintF("Broadcast\n");
+ if (ioreq->ios2_DstAddr) {
+ for (int i = 0; i < ADDRFIELDSIZE; i++) {
+ ioreq->ios2_DstAddr[i] = 0xFF;
+ }
+ } else {
+ KPrintF("Invalid ios2_DstAddr\n");
+ }
+ /* Fallthrough */
+ case CMD_WRITE: {
+ KPrintF("Write\n");
+ pinet_write_frame(ioreq);
+ break;
+ }
+
+ case S2_READORPHAN:
+ ioreq->ios2_Req.io_Flags &= ~SANA2IOF_QUICK;
+ ioreq = NULL;
+ break;
+ case S2_ONLINE:
+ case S2_OFFLINE:
+ case S2_CONFIGINTERFACE: /* forward request */
+ break;
+
+ case S2_GETSTATIONADDRESS:
+ for (int i = 0; i < ADDRFIELDSIZE; i++) {
+ ioreq->ios2_SrcAddr[i] = dev_base->MAC[i];
+ ioreq->ios2_DstAddr[i] = dev_base->MAC[i];
+ }
+ break;
+ case S2_DEVICEQUERY: {
+ struct Sana2DeviceQuery *devquery;
+
+ devquery = ioreq->ios2_StatData;
+ devquery->DevQueryFormat = 0;
+ devquery->DeviceLevel = 0;
+
+ if (devquery->SizeAvailable >= 18)
+ devquery->AddrFieldSize = ADDRFIELDSIZE * 8;
+ if (devquery->SizeAvailable >= 22)
+ devquery->MTU = 1500;
+ if (devquery->SizeAvailable >= 26)
+ devquery->BPS = 1000 * 1000 * 100;
+ if (devquery->SizeAvailable >= 30)
+ devquery->HardwareType = S2WireType_Ethernet;
+
+ devquery->SizeSupplied = (devquery->SizeAvailable < 30) ? devquery->SizeAvailable : 30;
+ break;
+ }
+ case S2_GETSPECIALSTATS: {
+ struct Sana2SpecialStatHeader *s2ssh = (struct Sana2SpecialStatHeader *)ioreq->ios2_StatData;
+ s2ssh->RecordCountSupplied = 0;
+ break;
+ }
+ default: {
+ uint8_t cmd = ioreq->ios2_Req.io_Command;
+ KPrintF("Unknown/unhandled IO command %lx\n", cmd);
+ ioreq->ios2_Req.io_Error = S2ERR_NOT_SUPPORTED;
+ ioreq->ios2_WireError = S2WERR_GENERIC_ERROR;
+ break;
+ }
+ }
+
+ if (ioreq) {
+ if (!(ioreq->ios2_Req.io_Flags & SANA2IOF_QUICK)) {
+ ReplyMsg((struct Message *)ioreq);
+ } else {
+ ioreq->ios2_Req.io_Message.mn_Node.ln_Type = NT_REPLYMSG;
+ }
+ }
+}
+
+ADDTABL_1(__AbortIO,a1);
+void __AbortIO(struct IORequest* ioreq) {
+ struct IOSana2Req* ios2 = (struct IOSana2Req*)ioreq;
+
+ if (!ioreq) return;
+ ioreq->io_Error = IOERR_ABORTED;
+ ios2->ios2_WireError = 0;
+}
+
+ADDTABL_1(__TermIO,a1);
+void __TermIO(struct IORequest *ioreq) {
+ struct IOSana2Req* ios2 = (struct IOSana2Req*)ioreq;
+
+ if (!(ios2->ios2_Req.io_Flags & SANA2IOF_QUICK)) {
+ ReplyMsg((struct Message *)ioreq);
+ } else {
+ ioreq->io_Message.mn_Node.ln_Type = NT_REPLYMSG;
+ }
+}
+
+/*ULONG get_frame_serial(UBYTE* frame) {
+ UBYTE* frm = (UBYTE*)frame;
+ ULONG ser = ((ULONG)frm[2]<<8)|((ULONG)frm[3]);
+ return ser;
+}
+
+ULONG read_frame(struct IOSana2Req *req, volatile UBYTE *frame)
+{
+ ULONG datasize;
+ BYTE *frame_ptr;
+ BOOL broadcast;
+ ULONG err = 0;
+ struct BufferManagement *bm;
+
+ UBYTE* frm = (UBYTE*)frame;
+ ULONG sz = ((ULONG)frm[0]<<8)|((ULONG)frm[1]);
+ ULONG ser = ((ULONG)frm[2]<<8)|((ULONG)frm[3]);
+ USHORT tp = ((USHORT)frm[16]<<8)|((USHORT)frm[17]);
+
+ if (req->ios2_Req.io_Flags & SANA2IOF_RAW) {
+ frame_ptr = frm+4;
+ datasize = sz;
+ req->ios2_Req.io_Flags = SANA2IOF_RAW;
+ }
+ else {
+ frame_ptr = frm+4+HW_ETH_HDR_SIZE;
+ datasize = sz-HW_ETH_HDR_SIZE;
+ req->ios2_Req.io_Flags = 0;
+ }
+
+ req->ios2_DataLength = datasize;
+
+ //D(("datasize: %lx\n",datasize));
+ //D(("frame_ptr: %lx\n",frame_ptr));
+ //D(("ios2_Data: %lx\n",req->ios2_Data));
+ //D(("bufmgmt: %lx\n",req->ios2_BufferManagement));
+
+ // copy frame to device user (probably tcp/ip system)
+ bm = (struct BufferManagement *)req->ios2_BufferManagement;
+ if (!(*bm->bm_CopyToBuffer)(req->ios2_Data, frame_ptr, datasize)) {
+ //D(("rx copybuf error\n"));
+ req->ios2_Req.io_Error = S2ERR_SOFTWARE;
+ req->ios2_WireError = S2WERR_BUFF_ERROR;
+ err = 1;
+ }
+ else {
+ req->ios2_Req.io_Error = req->ios2_WireError = 0;
+ err = 0;
+ }
+
+ memcpy(req->ios2_SrcAddr, frame+4+6, HW_ADDRFIELDSIZE);
+ memcpy(req->ios2_DstAddr, frame+4, HW_ADDRFIELDSIZE);
+
+ //D(("RXSZ %ld\n",(LONG)sz));
+ //D(("RXPT %ld\n",(LONG)tp));
+
+ //D(("RXSER %ld\n",(LONG)ser));
+ //D(("RXDST %lx...\n",*((ULONG*)(req->ios2_DstAddr))));
+ //D(("RXSRC %lx\n",*((ULONG*)(req->ios2_SrcAddr))));
+ //D(("RXSRC %lx\n",*((ULONG*)(frame_ptr))));
+
+ broadcast = TRUE;
+ for (int i=0; i<HW_ADDRFIELDSIZE; i++) {
+ if (frame[i+4] != 0xff) {
+ broadcast = FALSE;
+ break;
+ }
+ }
+ if (broadcast) {
+ req->ios2_Req.io_Flags |= SANA2IOF_BCAST;
+ }
+
+ req->ios2_PacketType = tp;
+
+ return err;
+}
+
+ULONG write_frame(struct IOSana2Req *req, UBYTE *frame)
+{
+ ULONG rc=0;
+ struct BufferManagement *bm;
+ USHORT sz=0;
+
+ if (req->ios2_Req.io_Flags & SANA2IOF_RAW) {
+ sz = req->ios2_DataLength;
+ } else {
+ sz = req->ios2_DataLength + HW_ETH_HDR_SIZE;
+ *((USHORT*)(frame+6+6)) = (USHORT)req->ios2_PacketType;
+ memcpy(frame, req->ios2_DstAddr, HW_ADDRFIELDSIZE);
+ memcpy(frame+6, HW_MAC, HW_ADDRFIELDSIZE);
+ frame+=HW_ETH_HDR_SIZE;
+ }
+
+ if (sz>0) {
+ bm = (struct BufferManagement *)req->ios2_BufferManagement;
+
+ if (!(*bm->bm_CopyFromBuffer)(frame, req->ios2_Data, req->ios2_DataLength)) {
+ rc = 1; // FIXME error code
+ //D(("tx copybuf err\n"));
+ }
+ else {
+ // buffer was copied to zz9000, send it
+ volatile USHORT* reg = (volatile USHORT*)(ZZ9K_REGS+0x80); // FIXME send_frame reg
+ *reg = sz;
+
+ // get feedback
+ rc = *reg;
+ if (rc!=0) {
+ D(("tx err: %d\n",rc));
+ }
+ }
+ }
+
+ return rc;
+}*/
+
+ADDTABL_END();
--- /dev/null
+#ifndef SANA2_SANA2DEVICE_H
+#define SANA2_SANA2DEVICE_H 1
+/*
+** $Filename: devices/sana2.h $
+** $Revision: 4.1 $
+** $Date: 1994/10/03 20:55:10 $
+**
+** Structure definitions for SANA-II devices.
+**
+** (C) Copyright 1991 Commodore-Amiga Inc.
+** All Rights Reserved
+*/
+
+
+#ifndef EXEC_TYPES_H
+#include <exec/types.h>
+#endif
+
+#ifndef EXEC_PORTS_H
+#include <exec/ports.h>
+#endif
+
+#ifndef EXEC_IO_H
+#include <exec/io.h>
+#endif
+
+#ifndef EXEC_ERRORS_H
+#include <exec/errors.h>
+#endif
+
+#ifndef DEVICES_TIMER_H
+#include <devices/timer.h>
+#endif
+
+#ifndef UTILITY_TAGITEM_H
+#include <utility/tagitem.h>
+#endif
+
+
+#define SANA2_MAX_ADDR_BITS (128)
+#define SANA2_MAX_ADDR_BYTES ((SANA2_MAX_ADDR_BITS+7)/8)
+
+struct IOSana2Req
+{
+ struct IORequest ios2_Req;
+ ULONG ios2_WireError; /* wire type specific error */
+ ULONG ios2_PacketType; /* packet type */
+ UBYTE ios2_SrcAddr[SANA2_MAX_ADDR_BYTES]; /* source addr */
+ UBYTE ios2_DstAddr[SANA2_MAX_ADDR_BYTES]; /* dest address */
+ ULONG ios2_DataLength; /* length of packet data */
+ VOID *ios2_Data; /* packet data */
+ VOID *ios2_StatData; /* statistics data pointer */
+ VOID *ios2_BufferManagement; /* see SANA-II OpenDevice adoc */
+};
+
+
+/*
+** defines for the io_Flags field
+*/
+#define SANA2IOB_RAW (7) /* raw packet IO requested */
+#define SANA2IOF_RAW (1<<SANA2IOB_RAW)
+
+#define SANA2IOB_BCAST (6) /* broadcast packet (received) */
+#define SANA2IOF_BCAST (1<<SANA2IOB_BCAST)
+
+#define SANA2IOB_MCAST (5) /* multicast packet (received) */
+#define SANA2IOF_MCAST (1<<SANA2IOB_MCAST)
+
+#define SANA2IOB_QUICK (IOB_QUICK) /* quick IO requested (0) */
+#define SANA2IOF_QUICK (IOF_QUICK)
+
+
+/*
+** defines for OpenDevice() flags
+*/
+#define SANA2OPB_MINE (0) /* exclusive access requested */
+#define SANA2OPF_MINE (1<<SANA2OPB_MINE)
+
+#define SANA2OPB_PROM (1) /* promiscuous mode requested */
+#define SANA2OPF_PROM (1<<SANA2OPB_PROM)
+
+
+/*
+** defines for OpenDevice() tags
+*/
+#define S2_Dummy (TAG_USER + 0xB0000)
+
+#define S2_CopyToBuff (S2_Dummy + 1)
+#define S2_CopyFromBuff (S2_Dummy + 2)
+#define S2_PacketFilter (S2_Dummy + 3)
+
+struct Sana2DeviceQuery
+{
+/*
+** Standard information
+*/
+ ULONG SizeAvailable; /* bytes available */
+ ULONG SizeSupplied; /* bytes supplied */
+ ULONG DevQueryFormat; /* this is type 0 */
+ ULONG DeviceLevel; /* this document is level 0 */
+/*
+** Common information
+*/
+ UWORD AddrFieldSize; /* address size in bits */
+ ULONG MTU; /* maximum packet data size */
+ ULONG BPS; /* line rate (bits/sec) */
+ ULONG HardwareType; /* what the wire is */
+/*
+** Format specific information
+*/
+};
+
+
+/*
+** defined Hardware types
+**
+** If your hardware type isn't listed below contact CATS to get a new
+** type number added for your hardware.
+*/
+#define S2WireType_Ethernet 1
+#define S2WireType_IEEE802 6
+#define S2WireType_Arcnet 7
+#define S2WireType_LocalTalk 11
+#define S2WireType_DyLAN 12
+
+#define S2WireType_AmokNet 200 /* Amiga Floppy Port hardware */
+
+#define S2WireType_Liana 202 /* Villate Tronic parallel port hw */
+
+#define S2WireType_PPP 253
+#define S2WireType_SLIP 254
+#define S2WireType_CSLIP 255 /* Compressed SLIP */
+
+#define S2WireType_PLIP 420 /* SLIP over a parallel port */
+
+struct Sana2PacketTypeStats
+{
+ ULONG PacketsSent; /* transmitted count */
+ ULONG PacketsReceived; /* received count */
+ ULONG BytesSent; /* bytes transmitted count */
+ ULONG BytesReceived; /* bytes received count */
+ ULONG PacketsDropped; /* packets dropped count */
+};
+
+
+struct Sana2SpecialStatRecord
+{
+ ULONG Type; /* statistic identifier */
+ ULONG Count; /* the statistic */
+ char *String; /* statistic name */
+};
+
+
+struct Sana2SpecialStatHeader
+{
+ ULONG RecordCountMax; /* room available */
+ ULONG RecordCountSupplied; /* number supplied */
+ /* struct Sana2SpecialStatRecord[RecordCountMax]; */
+};
+
+
+struct Sana2DeviceStats
+{
+ ULONG PacketsReceived; /* received count */
+ ULONG PacketsSent; /* transmitted count */
+ ULONG BadData; /* bad packets received */
+ ULONG Overruns; /* hardware miss count */
+ ULONG Unused; /* Unused field */
+ ULONG UnknownTypesReceived; /* orphan count */
+ ULONG Reconfigurations; /* network reconfigurations */
+ struct timeval LastStart; /* time of last online */
+};
+
+
+/*
+** Device Commands
+*/
+#define S2_START (CMD_NONSTD)
+
+#define S2_DEVICEQUERY (S2_START+ 0)
+#define S2_GETSTATIONADDRESS (S2_START+ 1)
+#define S2_CONFIGINTERFACE (S2_START+ 2)
+#define S2_ADDMULTICASTADDRESS (S2_START+ 5)
+#define S2_DELMULTICASTADDRESS (S2_START+ 6)
+#define S2_MULTICAST (S2_START+ 7)
+#define S2_BROADCAST (S2_START+ 8)
+#define S2_TRACKTYPE (S2_START+ 9)
+#define S2_UNTRACKTYPE (S2_START+10)
+#define S2_GETTYPESTATS (S2_START+11)
+#define S2_GETSPECIALSTATS (S2_START+12)
+#define S2_GETGLOBALSTATS (S2_START+13)
+#define S2_ONEVENT (S2_START+14)
+#define S2_READORPHAN (S2_START+15)
+#define S2_ONLINE (S2_START+16)
+#define S2_OFFLINE (S2_START+17)
+
+#define S2_END (S2_START+18)
+
+
+/*
+** defined errors for io_Error (see also <exec/errors.h>)
+*/
+#define S2ERR_NO_ERROR 0 /* peachy-keen */
+#define S2ERR_NO_RESOURCES 1 /* resource allocation failure */
+#define S2ERR_BAD_ARGUMENT 3 /* garbage somewhere */
+#define S2ERR_BAD_STATE 4 /* inappropriate state */
+#define S2ERR_BAD_ADDRESS 5 /* who? */
+#define S2ERR_MTU_EXCEEDED 6 /* too much to chew */
+#define S2ERR_NOT_SUPPORTED 8 /* hardware can't support cmd */
+#define S2ERR_SOFTWARE 9 /* software error detected */
+#define S2ERR_OUTOFSERVICE 10 /* driver is OFFLINE */
+#define S2ERR_TX_FAILURE 11 /* Transmission attempt failed */
+/*
+** From <exec/errors.h>
+**
+** IOERR_OPENFAIL (-1) * device/unit failed to open *
+** IOERR_ABORTED (-2) * request terminated early [after AbortIO()] *
+** IOERR_NOCMD (-3) * command not supported by device *
+** IOERR_BADLENGTH (-4) * not a valid length (usually IO_LENGTH) *
+** IOERR_BADADDRESS (-5) * invalid address (misaligned or bad range) *
+** IOERR_UNITBUSY (-6) * device opens ok, but requested unit is busy *
+** IOERR_SELFTEST (-7) * hardware failed self-test *
+*/
+
+/*
+** defined errors for ios2_WireError
+*/
+#define S2WERR_GENERIC_ERROR 0 /* no specific info available */
+#define S2WERR_NOT_CONFIGURED 1 /* unit not configured */
+#define S2WERR_UNIT_ONLINE 2 /* unit is currently online */
+#define S2WERR_UNIT_OFFLINE 3 /* unit is currently offline */
+#define S2WERR_ALREADY_TRACKED 4 /* protocol already tracked */
+#define S2WERR_NOT_TRACKED 5 /* protocol not tracked */
+#define S2WERR_BUFF_ERROR 6 /* buff mgt func returned error */
+#define S2WERR_SRC_ADDRESS 7 /* source address problem */
+#define S2WERR_DST_ADDRESS 8 /* destination address problem */
+#define S2WERR_BAD_BROADCAST 9 /* broadcast address problem */
+#define S2WERR_BAD_MULTICAST 10 /* multicast address problem */
+#define S2WERR_MULTICAST_FULL 11 /* multicast address list full */
+#define S2WERR_BAD_EVENT 12 /* unsupported event class */
+#define S2WERR_BAD_STATDATA 13 /* statdata failed sanity check */
+#define S2WERR_IS_CONFIGURED 15 /* attempt to config twice */
+#define S2WERR_NULL_POINTER 16 /* null pointer detected */
+#define S2WERR_TOO_MANY_RETIRES 17 /* tx failed - too many retries */
+#define S2WERR_RCVREL_HDW_ERR 18 /* Driver fixable HW error */
+
+
+/*
+** defined events
+*/
+#define S2EVENT_ERROR (1L<<0) /* error catch all */
+#define S2EVENT_TX (1L<<1) /* transmitter error catch all */
+#define S2EVENT_RX (1L<<2) /* receiver error catch all */
+#define S2EVENT_ONLINE (1L<<3) /* unit is in service */
+#define S2EVENT_OFFLINE (1L<<4) /* unit is not in service */
+#define S2EVENT_BUFF (1L<<5) /* buff mgt function error */
+#define S2EVENT_HARDWARE (1L<<6) /* hardware error catch all */
+#define S2EVENT_SOFTWARE (1L<<7) /* software error catch all */
+
+
+#endif /* SANA2_SANA2DEVICE_H */
--- /dev/null
+#define PINET_OFFSET 0x80010000
+#define PINET_REGSIZE 0x00010000
+#define PINET_UPPER 0x80020000
+
+/*enum piscsi_stuff {
+ PISCSI_BLOCK_SIZE = 512,
+ PISCSI_TRACK_SECTORS = 2048,
+};*/
+
+#define ADDRFIELDSIZE 6
+#define ETH_HDR_SIZE 14
+
+enum pinet_cmds {
+ PINET_CMD_WRITE = 0x00,
+ PINET_CMD_READ = 0x02,
+ PINET_CMD_MAC = 0x04,
+ PINET_CMD_IP = 0x0A,
+ PINET_CMD_BEEF = 0x0E,
+ PINET_CMD_ADDR1 = 0x10,
+ PINET_CMD_ADDR2 = 0x14,
+ PINET_CMD_ADDR3 = 0x18,
+ PINET_CMD_ADDR4 = 0x1C,
+ PINET_CMD_FRAME = 0x1000,
+};
\ No newline at end of file
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <endian.h>
+#include "pi-net.h"
+#include "pi-net-enums.h"
+#include "config_file/config_file.h"
+#include "gpio/ps_protocol.h"
+
+uint32_t pinet_u32[4];
+static const char *op_type_names[4] = {
+ "BYTE",
+ "WORD",
+ "LONGWORD",
+ "MEM",
+};
+
+void pinet_init(char *dev) {
+ // Initialize them nets.
+}
+
+uint8_t PI_MAC[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+uint8_t PI_IP[4] = { 192, 168, 1, 9 };
+
+void handle_pinet_write(uint32_t addr, uint32_t val, uint8_t type) {
+ int32_t r;
+
+ switch (addr & 0xFFFF) {
+ case PINET_CMD_READ:
+ printf("[PI-NET] Read.\n");
+ break;
+ case PINET_CMD_WRITE:
+ printf("[PI-NET] Write.\n");
+ break;
+ case PINET_CMD_ADDR1:
+ pinet_u32[0] = val;
+ printf("[PI-NET] Write to ADDR1: %.8x\n", pinet_u32[0]);
+ break;
+ case PINET_CMD_ADDR2:
+ pinet_u32[1] = val;
+ printf("[PI-NET] Write to ADDR2: %.8x\n", pinet_u32[1]);
+ break;
+ case PINET_CMD_ADDR3:
+ pinet_u32[2] = val;
+ printf("[PI-NET] Write to ADDR3: %.8x\n", pinet_u32[2]);
+ break;
+ case PINET_CMD_ADDR4:
+ pinet_u32[3] = val;
+ printf("[PI-NET] Write to ADDR4: %.8x\n", pinet_u32[3]);
+ break;
+ default:
+ printf("[PI-NET] Unhandled %s register write to %.8X: %d\n", op_type_names[type], addr, val);
+ break;
+ }
+}
+
+uint32_t handle_pinet_read(uint32_t addr_, uint8_t type) {
+ uint32_t addr = addr_ & 0xFFFF;
+
+ if (addr >= PINET_CMD_MAC && addr < PINET_CMD_IP) {
+ printf("[PI-NET] Read from MAC: %.2X. (%.8X)\n", PI_MAC[addr - PINET_CMD_MAC], addr_);
+ return PI_MAC[addr - PINET_CMD_MAC];
+ }
+ if (addr >= PINET_CMD_IP && addr < PINET_CMD_BEEF) {
+ printf("[PI-NET] Read from IP: %.2X. (%.8X)\n", PI_IP[addr - PINET_CMD_IP], addr_);
+ return PI_IP[addr - PINET_CMD_IP];
+ }
+
+ switch (addr & 0xFFFF) {
+ default:
+ printf("[PI-NET] Unhandled %s register read from %.8X\n", op_type_names[type], addr);
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+void pinet_init(char *dev);
+void handle_pinet_write(uint32_t addr, uint32_t val, uint8_t type);
+uint32_t handle_pinet_read(uint32_t addr, uint8_t type);
--- /dev/null
+**
+** Sample autoboot code fragment
+**
+** These are the calling conventions for the Diag routine
+**
+** A7 -- points to at least 2K of stack
+** A6 -- ExecBase
+** A5 -- ExpansionBase
+** A3 -- your board's ConfigDev structure
+** A2 -- Base of diag/init area that was copied
+** A0 -- Base of your board
+**
+** Your Diag routine should return a non-zero value in D0 for success.
+** If this value is NULL, then the diag/init area that was copied
+** will be returned to the free memory pool.
+**
+
+ INCLUDE "exec/types.i"
+ INCLUDE "exec/nodes.i"
+ INCLUDE "exec/resident.i"
+ INCLUDE "libraries/configvars.i"
+
+ ; LVO's resolved by linking with library amiga.lib
+ XREF _LVOFindResident
+
+ROMINFO EQU 0
+ROMOFFS EQU $4000
+
+* ROMINFO defines whether you want the AUTOCONFIG information in
+* the beginning of your ROM (set to 0 if you instead have PALS
+* providing the AUTOCONFIG information instead)
+*
+* ROMOFFS is the offset from your board base where your ROMs appear.
+* Your ROMs might appear at offset 0 and contain your AUTOCONFIG
+* information in the high nibbles of the first $40 words ($80 bytes).
+* Or, your autoconfig ID information may be in a PAL, with your
+* ROMs possibly being addressed at some offset (for example $2000)
+* from your board base. This ROMOFFS constant will be used as an
+* additional offset from your configured board address when patching
+* structures which require absolute pointers to ROM code or data.
+
+*----- We'll store Version and Revision in serial number
+VERSION EQU 37 ; also the high word of serial number
+REVISION EQU 1 ; also the low word of serial number
+
+* See the Addison-Wesley Amiga Hardware Manual for more info.
+
+MANUF_ID EQU 2011 ; CBM assigned (2011 for hackers only)
+PRODUCT_ID EQU 1 ; Manufacturer picks product ID
+
+BOARDSIZE EQU $10000 ; How much address space board decodes
+SIZE_FLAG EQU 3 ; Autoconfig 3-bit flag for BOARDSIZE
+ ; 0=$800000(8meg) 4=$80000(512K)
+ ; 1=$10000(64K) 5=$100000(1meg)
+ ; 2=$20000(128K) 6=$200000(2meg)
+ ; 3=$40000(256K) 7=$400000(4meg)
+ CODE
+
+; Exec stuff
+AllocMem EQU -198
+InitResident EQU -102
+FindResident EQU -96
+OpenLibrary EQU -552
+CloseLibrary EQU -414
+OpenResource EQU -$1F2
+AddResource EQU -$1E6
+
+; Expansion stuff
+MakeDosNode EQU -144
+AddDosNode EQU -150
+AddBootNode EQU -36
+
+; PiSCSI stuff
+PiSCSIAddr1 EQU $80000010
+PiSCSIAddr2 EQU $80000014
+PiSCSIAddr3 EQU $80000018
+PiSCSIAddr4 EQU $8000001C
+PiSCSIDebugMe EQU $80000020
+PiSCSIDriver EQU $80000040
+PiSCSINextPart EQU $80000044
+PiSCSIGetPart EQU $80000048
+PiSCSIGetPrio EQU $8000004C
+PiSCSIGetFS EQU $80000060
+PiSCSINextFS EQU $80000064
+PiSCSICopyFS EQU $80000068
+PiSCSIFSSize EQU $8000006C
+PiSCSISetFSH EQU $80000070
+PiSCSIDbg1 EQU $80001010
+PiSCSIDbg2 EQU $80001014
+PiSCSIDbg3 EQU $80001018
+PiSCSIDbg4 EQU $8000101C
+PiSCSIDbg5 EQU $80001020
+PiSCSIDbg6 EQU $80001024
+PiSCSIDbg7 EQU $80001028
+PiSCSIDbg8 EQU $8000102C
+PiSCSIDbgMsg EQU $80001000
+
+******* RomStart ***************************************************
+**********************************************************************
+
+RomStart:
+
+******* DiagStart **************************************************
+DiagStart: ; This is the DiagArea structure whose relative offset from
+ ; your board base appears as the Init Diag vector in your
+ ; autoconfig ID information. This structure is designed
+ ; to use all relative pointers (no patching needed).
+ dc.b DAC_WORDWIDE+DAC_CONFIGTIME ; da_Config
+ dc.b 0 ; da_Flags
+ dc.w $4000 ; da_Size
+ dc.w DiagEntry-DiagStart ; da_DiagPoint
+ dc.w BootEntry-DiagStart ; da_BootPoint
+ dc.w DevName-DiagStart ; da_Name
+ dc.w 0 ; da_Reserved01
+ dc.w 0 ; da_Reserved02
+
+******* Resident Structure *****************************************
+Romtag:
+ dc.w RTC_MATCHWORD ; UWORD RT_MATCHWORD
+rt_Match: dc.l Romtag-DiagStart ; APTR RT_MATCHTAG
+rt_End: dc.l EndCopy-DiagStart ; APTR RT_ENDSKIP
+ dc.b RTW_COLDSTART ; UBYTE RT_FLAGS
+ dc.b VERSION ; UBYTE RT_VERSION
+ dc.b NT_DEVICE ; UBYTE RT_TYPE
+ dc.b 20 ; BYTE RT_PRI
+rt_Name: dc.l DevName-DiagStart ; APTR RT_NAME
+rt_Id: dc.l IdString-DiagStart ; APTR RT_IDSTRING
+rt_Init: dc.l Init-RomStart ; APTR RT_INIT
+
+
+******* Strings referenced in Diag Copy area ************************
+DevName: dc.b 'pi-scsi.device',0,0 ; Name string
+IdString dc.b 'PISCSI v0.8',0 ; Id string
+
+DosName: dc.b 'dos.library',0 ; DOS library name
+ExpansionName: dc.b "expansion.library",0
+LibName: dc.b "pi-scsi.device",0,0
+
+DosDevName: dc.b 'ABC',0 ; dos device name for MakeDosNode()
+ ; (dos device will be ABC:)
+
+ ds.w 0 ; word align
+
+******* DiagEntry **************************************************
+**********************************************************************
+*
+* success = DiagEntry(BoardBase,DiagCopy, configDev)
+* d0 a0 a2 a3
+*
+* Called by expansion architecture to relocate any pointers
+* in the copied diagnostic area. We will patch the romtag.
+* If you have pre-coded your MakeDosNode packet, BootNode,
+* or device initialization structures, they would also need
+* to be within this copy area, and patched by this routine.
+*
+**********************************************************************
+
+DiagEntry:
+ align 2
+ nop
+ nop
+ nop
+ move.l #1,PiSCSIDebugMe
+ move.l a3,PiSCSIAddr1
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ lea patchTable-RomStart(a0),a1 ; find patch table
+ adda.l #ROMOFFS,a1 ; adjusting for ROMOFFS
+
+* Patch relative pointers to labels within DiagCopy area
+* by adding Diag RAM copy address. These pointers were coded as
+* long relative offsets from base of the DiagArea structure.
+*
+dpatches:
+ move.l a2,d1 ;d1=base of ram Diag copy
+dloop:
+ move.w (a1)+,d0 ;d0=word offs. into Diag needing patch
+ bmi.s bpatches ;-1 is end of word patch offset table
+ add.l d1,0(a2,d0.w) ;add DiagCopy addr to coded rel. offset
+ bra.s dloop
+
+* Patches relative pointers to labels within the ROM by adding
+* the board base address + ROMOFFS. These pointers were coded as
+* long relative offsets from RomStart.
+*
+bpatches:
+ move.l a0,d1 ;d1 = board base address
+ add.l #ROMOFFS,d1 ;add offset to where your ROMs are
+rloop:
+ move.w (a1)+,d0 ;d0=word offs. into Diag needing patch
+ bmi.s endpatches ;-1 is end of patch offset table
+ add.l d1,0(a2,d0.w) ;add ROM address to coded relative offset
+ bra.s rloop
+
+endpatches:
+ moveq.l #1,d0 ; indicate "success"
+ rts
+
+
+******* BootEntry **************************************************
+**********************************************************************
+
+BootEntry:
+ align 2
+ move.l #2,PiSCSIDebugMe
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ lea DosName(PC),a1 ; 'dos.library',0
+ jsr FindResident(a6) ; find the DOS resident tag
+ move.l d0,a0 ; in order to bootstrap
+ move.l RT_INIT(A0),a0 ; set vector to DOS INIT
+ jsr (a0) ; and initialize DOS
+ rts
+
+*
+* End of the Diag copy area which is copied to RAM
+*
+EndCopy:
+*************************************************************************
+
+*************************************************************************
+*
+* Beginning of ROM driver code and data that is accessed only in
+* the ROM space. This must all be position-independent.
+*
+
+patchTable:
+* Word offsets into Diag area where pointers need Diag copy address added
+ dc.w rt_Match-DiagStart
+ dc.w rt_End-DiagStart
+ dc.w rt_Name-DiagStart
+ dc.w rt_Id-DiagStart
+ dc.w -1
+
+* Word offsets into Diag area where pointers need boardbase+ROMOFFS added
+ dc.w rt_Init-DiagStart
+ dc.w -1
+
+******* Romtag InitEntry **********************************************
+*************************************************************************
+
+Init: ; After Diag patching, our romtag will point to this
+ ; routine in ROM so that it can be called at Resident
+ ; initialization time.
+ ; This routine will be similar to a normal expansion device
+ ; initialization routine, but will MakeDosNode then set up a
+ ; BootNode, and Enqueue() on eb_MountList.
+ ;
+ align 2
+ move.l a6,-(a7) ; Push A6 to stack
+ move.w #$00B8,$dff09a ; Disable interrupts during init
+ move.l #3,PiSCSIDebugMe
+
+ move.l #11,PiSCSIDebugMe
+ movea.l 4,a6
+ lea LibName(pc),a1
+ jsr FindResident(a6)
+ move.l #10,PiSCSIDebugMe
+ cmp.l #0,d0
+ bne.s SkipDriverLoad ; Library is already loaded, jump straight to partitions
+
+ move.l #4,PiSCSIDebugMe
+ movea.l 4,a6
+ move.l #$40000,d0
+ moveq #0,d1
+ jsr AllocMem(a6) ; Allocate memory for the PiStorm to copy the driver to
+
+ move.l d0,PiSCSIDriver ; Copy the PiSCSI driver to allocated memory and patch offsets
+
+ move.l #5,PiSCSIDebugMe
+ move.l d0,a1
+ move.l #0,d1
+ movea.l 4,a6
+ add.l #$02c,a1
+ jsr InitResident(a6) ; Initialize the PiSCSI driver
+
+SkipDriverLoad:
+ move.l #9,PiSCSIDebugMe
+ bra.w LoadFileSystems
+
+FSLoadExit:
+ lea ExpansionName(pc),a1
+ moveq #0,d0
+ jsr OpenLibrary(a6) ; Open expansion.library to make this work, somehow
+ move.l d0,a6
+
+ move.l #7,PiSCSIDebugMe
+PartitionLoop:
+ move.l PiSCSIGetPart,d0 ; Get the available partition in the current slot
+ beq.s EndPartitions ; If the next partition returns 0, there's no additional partitions
+ move.l d0,a0
+ jsr MakeDosNode(a6)
+ move.l d0,PiSCSISetFSH
+ move.l d0,a0
+ move.l PiSCSIGetPrio,d0
+ move.l #0,d1
+ move.l PiSCSIAddr1,a1
+ jsr AddBootNode(a6)
+ move.l #1,PiSCSINextPart ; Switch to the next partition
+ bra.w PartitionLoop
+
+
+EndPartitions:
+ move.l #8,PiSCSIDebugMe
+ move.l a6,a1
+ move.l #800,PiSCSIDebugMe
+ movea.l 4,a6
+ move.l #801,PiSCSIDebugMe
+ jsr CloseLibrary(a6)
+ move.l #802,PiSCSIDebugMe
+
+ move.l (a7)+,a6 ; Pop A6 from stack
+ move.l #803,PiSCSIDebugMe
+
+ move.w #$80B8,$dff09a ; Re-enable interrupts
+ move.l #804,PiSCSIDebugMe
+ moveq.l #1,d0 ; indicate "success"
+ move.l #805,PiSCSIDebugMe
+ rts
+
+ align 4
+FileSysName dc.b 'FileSystem.resource',0
+FileSysCreator dc.b 'PiStorm',0
+
+CurFS: dc.l $0
+FSResource: dc.l $0
+
+ align 2
+LoadFileSystems:
+ movem.l d0-d7/a0-a6,-(sp) ; Push registers to stack
+ move.l #30,PiSCSIDebugMe
+ lea FileSysName(pc),a1
+ jsr OpenResource(a6)
+ tst.l d0
+ bne FSRExists
+
+ move.l #33,PiSCSIDebugMe ; FileSystem.resource isn't open, create it
+ lea FSRes(pc),a1
+ move.l a1,-(a7)
+ jsr AddResource(a6)
+ move.l (a7)+,a0
+ move.l a0,d0
+
+FSRExists:
+ move.l d0,PiSCSIAddr2 ; PiSCSIAddr2 is now FileSystem.resource
+ move.l #31,PiSCSIDebugMe
+ move.l PiSCSIAddr2,a0
+ move.l PiSCSIGetFS,d0
+ cmp.l #0,d0
+ beq.w FSDone
+ move.l d0,d7
+
+FSNext:
+ move.l #45,PiSCSIDebugMe
+ lea fsr_FileSysEntries(a0),a0
+ move.l a0,d2
+ move.l LH_HEAD(a0),d0
+ beq.w NoEntries
+
+FSLoop:
+ move.l #34,PiSCSIDebugMe
+ move.l d0,a1
+ move.l #35,PiSCSIDebugMe
+ cmp.l fse_DosType(a1),d7
+ move.l #36,PiSCSIDebugMe
+ beq.w AlreadyLoaded
+ move.l #37,PiSCSIDebugMe
+ move.l LN_SUCC(a1),d0
+ bne.w FSLoop
+ move.l #390,PiSCSIDebugMe
+ bra.w NoEntries
+
+ align 2
+NoEntries:
+ move.l #39,PiSCSIDebugMe
+ move.l PiSCSIFSSize,d0
+ move.l #40,PiSCSIDebugMe
+ move.l #0,d1
+ move.l #41,PiSCSIDebugMe
+ jsr AllocMem(a6)
+ move.l d0,PiSCSIAddr3
+ move.l #1,PiSCSICopyFS
+
+AlreadyLoaded:
+ move.l #480,PiSCSIDebugMe
+ move.l PiSCSIAddr2,a0
+ move.l #1,PiSCSINextFS
+ move.l PiSCSIGetFS,d0
+ move.l d0,d7
+ cmp.l #0,d0
+ bne.w FSNext
+
+FSDone: move.l #37,PiSCSIDebugMe
+ move.l #32,PiSCSIDebugMe ; Couldn't open FileSystem.resource, Kick 1.2/1.3?
+
+ movem.l (sp)+,d0-d7/a0-a6 ; Pop registers from stack
+ bra.w FSLoadExit
+
+FileSysRes
+ dc.l 0
+ dc.l 0
+ dc.b NT_RESOURCE
+ dc.b 0
+ dc.l FileSysName
+ dc.l FileSysCreator
+.Head
+ dc.l .Tail
+.Tail
+ dc.l 0
+ dc.l .Head
+ dc.b NT_RESOURCE
+ dc.b 0
--- /dev/null
+#m68k-amigaos-gcc piscsi-amiga.c -ramiga-dev -noixemul -fbaserel -O2 -o pi-scsi.device -ldebug -lamiga -m68020
+#m68k-amigaos-gcc -m68020 -O2 -o pi-scsi.device -ramiga-dev -noixemul -fbaserel piscsi-amiga.c -ldebug -lamiga
+#m68k-amigaos-gcc -m68020 -O2 -o scsi.device -ramiga-dev -noixemul -fbaserel piscsi-amiga.c -ldebug -lamiga -D_FSCSIDEV
+#m68k-amigaos-gcc -m68020 -O2 -o 2nd.scsi.device -ramiga-dev -noixemul -fbaserel piscsi-amiga.c -ldebug -lamiga -D_FSCSI2ND
+vasmm68k_mot.exe -m68000 -Fhunk -I$VBCC/NDK39/include/include_i bootrom.s -o bootrom
+#m68k-amigaos-as -m68020 bootrom.s &&
+#m68k-amigaos-objcopy --strip-all ./a.out ./bootrom
+#rm ./a.out
--- /dev/null
+m68k-amigaos-gcc piscsi-amiga-2.c -m68020 -O2 -o pi-scsi.device -m68000 -Wall -Wextra -Wno-unused-parameter -fomit-frame-pointer -nostdlib -nostartfiles
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#define BOOTLDR_SIZE 0x1000
+#define DIAG_TOTAL_SIZE 0x4000
+
+char *rombuf, *zerobuf, *devicebuf;
+
+int main(int argc, char *argv[]) {
+ FILE *rom = fopen("bootrom", "rb");
+ if (!rom) {
+ printf("Could not open file bootrom for reading.\n");
+ return 1;
+ }
+ FILE *out = fopen("../piscsi.rom", "wb+");
+ if (!out) {
+ printf("Could not open file piscsi.rom for writing.\n");
+ fclose(rom);
+ return 1;
+ }
+ FILE *device = NULL;
+ if (argc > 1) {
+ device = fopen(argv[1], "rb");
+ }
+ else {
+ device = fopen("pi-scsi.device", "rb");
+ }
+ if (!device) {
+ printf("Could not open device file for reading.\n");
+ fclose(rom);
+ fclose(out);
+ return 1;
+ }
+
+ fseek(device, 0, SEEK_END);
+ fseek(rom, 0, SEEK_END);
+ uint32_t rom_size = ftell(rom);
+ uint32_t device_size = ftell(device);
+ fseek(rom, 0, SEEK_SET);
+ fseek(device, 0, SEEK_SET);
+
+ uint32_t pad_size = BOOTLDR_SIZE - rom_size;
+
+ rombuf = malloc(rom_size);
+ devicebuf = malloc(device_size);
+ zerobuf = malloc(pad_size);
+ memset(zerobuf, 0x00, pad_size);
+
+ fread(rombuf, rom_size, 1, rom);
+ fread(devicebuf, device_size, 1, device);
+
+ fwrite(rombuf, rom_size, 1, out);
+ fwrite(zerobuf, pad_size, 1, out);
+ fwrite(devicebuf, device_size, 1, out);
+
+ free(zerobuf);
+ zerobuf = malloc(DIAG_TOTAL_SIZE - (rom_size + pad_size + device_size));
+ memset(zerobuf, 0x00, DIAG_TOTAL_SIZE - (rom_size + pad_size + device_size));
+ fwrite(zerobuf, DIAG_TOTAL_SIZE - (rom_size + pad_size + device_size), 1, out);
+
+ printf("piscsi.rom successfully created.\n");
+
+ free(rombuf);
+ free(zerobuf);
+ free(devicebuf);
+
+ fclose(out);
+ fclose(device);
+ fclose(rom);
+
+ return 0;
+}
--- /dev/null
+#ifndef DEVICES_NEWSTYLE_H
+#define DEVICES_NEWSTYLE_H
+/*------------------------------------------------------------------------*/
+/*
+ * $Id: newstyle.h 1.1 1997/05/15 18:53:15 heinz Exp $
+ *
+ * Support header for the New Style Device standard
+ *
+ * (C)1996-1997 by Amiga International, Inc.
+ *
+ */
+/*------------------------------------------------------------------------*/
+
+/*
+ * At the moment there is just a single new style general command:
+ */
+
+#define NSCMD_DEVICEQUERY 0x4000
+
+struct NSDeviceQueryResult {
+ /*
+ ** Standard information, must be reset for every query
+ */
+ ULONG DevQueryFormat; /* this is type 0 */
+ ULONG SizeAvailable; /* bytes available */
+
+ /*
+ ** Common information (READ ONLY!)
+ */
+ UWORD DeviceType; /* what the device does */
+ UWORD DeviceSubType; /* depends on the main type */
+ UWORD *SupportedCommands; /* 0 terminated list of cmd's */
+
+ /* May be extended in the future! Check SizeAvailable! */
+};
+
+
+#define NSDEVTYPE_UNKNOWN 0 /* No suitable category, anything */
+#define NSDEVTYPE_GAMEPORT 1 /* like gameport.device */
+#define NSDEVTYPE_TIMER 2 /* like timer.device */
+#define NSDEVTYPE_KEYBOARD 3 /* like keyboard.device */
+#define NSDEVTYPE_INPUT 4 /* like input.device */
+#define NSDEVTYPE_TRACKDISK 5 /* like trackdisk.device */
+#define NSDEVTYPE_CONSOLE 6 /* like console.device */
+#define NSDEVTYPE_SANA2 7 /* A >=SANA2R2 networking device */
+#define NSDEVTYPE_AUDIO 8 /* like audio.device */
+#define NSDEVTYPE_CLIPBOARD 9 /* like clipboard.device */
+#define NSDEVTYPE_PRINTER 10 /* like printer.device */
+#define NSDEVTYPE_SERIAL 11 /* like serial.device */
+#define NSDEVTYPE_PARALLEL 12 /* like parallel.device */
+
+
+/*------------------------------------------------------------------------*/
+/* The following defines should really be part of device specific
+ * includes. So we protect them from being redefined.
+ */
+#ifndef NSCMD_TD_READ64
+/*
+ * An early new style trackdisk like device can also return this
+ * new identifier for TD_GETDRIVETYPE. This should no longer
+ * be the case though for newly written or updated NSD devices.
+ * This identifier is ***OBSOLETE***
+ */
+
+#define DRIVE_NEWSTYLE (0x4E535459L) /* 'NSTY' */
+
+
+/*
+ * At the moment, only four new style commands in the device
+ * specific range and their ETD counterparts may be implemented.
+ */
+
+#define NSCMD_TD_READ64 0xC000
+#define NSCMD_TD_WRITE64 0xC001
+#define NSCMD_TD_SEEK64 0xC002
+#define NSCMD_TD_FORMAT64 0xC003
+
+#define NSCMD_ETD_READ64 0xE000
+#define NSCMD_ETD_WRITE64 0xE001
+#define NSCMD_ETD_SEEK64 0xE002
+#define NSCMD_ETD_FORMAT64 0xE003
+#endif /* NSCMD_TD_READ64 */
+
+/*------------------------------------------------------------------------*/
+
+#endif /* DEVICES_NEWSTYLE_H */
--- /dev/null
+#include <exec/resident.h>
+#include <exec/errors.h>
+#include <exec/memory.h>
+#include <exec/lists.h>
+#include <exec/alerts.h>
+#include <exec/tasks.h>
+#include <exec/io.h>
+#include <exec/execbase.h>
+
+#include <libraries/expansion.h>
+
+#include <devices/trackdisk.h>
+#include <devices/timer.h>
+#include <devices/scsidisk.h>
+
+#include <dos/filehandler.h>
+
+#include <proto/exec.h>
+#include <proto/disk.h>
+#include <proto/expansion.h>
+
+#include "newstyle.h"
+
+#include "../piscsi-enums.h"
+#include <stdint.h>
+
+#define STR(s) #s
+#define XSTR(s) STR(s)
+
+#define DEVICE_NAME "pi-scsi.device"
+#define DEVICE_DATE "(3 Feb 2021)"
+#define DEVICE_ID_STRING "PiSCSI " XSTR(DEVICE_VERSION) "." XSTR(DEVICE_REVISION) " " DEVICE_DATE
+#define DEVICE_VERSION 43
+#define DEVICE_REVISION 20
+#define DEVICE_PRIORITY 0
+
+#pragma pack(4)
+struct piscsi_base {
+ struct Device* pi_dev;
+ struct piscsi_unit {
+ struct Unit unit;
+ uint32_t regs_ptr;
+
+ uint8_t enabled;
+ uint8_t present;
+ uint8_t valid;
+ uint8_t read_only;
+ uint8_t motor;
+ uint8_t unit_num;
+ uint16_t scsi_num;
+ uint16_t h, s;
+ uint32_t c;
+
+ uint32_t change_num;
+ } units[NUM_UNITS];
+};
+
+struct ExecBase *SysBase;
+uint8_t *saved_seg_list;
+uint8_t is_open;
+
+#define WRITESHORT(cmd, val) *(unsigned short *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+#define WRITELONG(cmd, val) *(unsigned long *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+#define WRITEBYTE(cmd, val) *(unsigned char *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+
+#define READSHORT(cmd, var) var = *(volatile unsigned short *)(PISCSI_OFFSET + cmd);
+#define READLONG(cmd, var) var = *(volatile unsigned long *)(PISCSI_OFFSET + cmd);
+
+int __attribute__((no_reorder)) _start()
+{
+ return -1;
+}
+
+asm("romtag: \n"
+ " dc.w "XSTR(RTC_MATCHWORD)" \n"
+ " dc.l romtag \n"
+ " dc.l endcode \n"
+ " dc.b "XSTR(RTF_AUTOINIT)" \n"
+ " dc.b "XSTR(DEVICE_VERSION)" \n"
+ " dc.b "XSTR(NT_DEVICE)" \n"
+ " dc.b "XSTR(DEVICE_PRIORITY)" \n"
+ " dc.l _device_name \n"
+ " dc.l _device_id_string \n"
+ " dc.l _auto_init_tables \n"
+ "endcode: \n");
+
+char device_name[] = DEVICE_NAME;
+char device_id_string[] = DEVICE_ID_STRING;
+
+uint8_t piscsi_perform_io(struct piscsi_unit *u, struct IORequest *io);
+uint8_t piscsi_rw(struct piscsi_unit *u, struct IORequest *io);
+uint8_t piscsi_scsi(struct piscsi_unit *u, struct IORequest *io);
+
+#define debug(...)
+#define debugval(...)
+//#define debug(c, v) WRITESHORT(c, v)
+//#define debugval(c, v) WRITELONG(c, v)
+
+struct piscsi_base *dev_base = NULL;
+
+static struct Library __attribute__((used)) *init_device(uint8_t *seg_list asm("a0"), struct Library *dev asm("d0"))
+{
+ SysBase = *(struct ExecBase **)4L;
+
+ debug(PISCSI_DBG_MSG, DBG_INIT);
+
+ dev_base = AllocMem(sizeof(struct piscsi_base), MEMF_PUBLIC | MEMF_CLEAR);
+ dev_base->pi_dev = (struct Device *)dev;
+
+ for (int i = 0; i < NUM_UNITS; i++) {
+ uint16_t r = 0;
+ WRITESHORT(PISCSI_CMD_DRVNUM, (i * 10));
+ dev_base->units[i].regs_ptr = PISCSI_OFFSET;
+ READSHORT(PISCSI_CMD_DRVTYPE, r);
+ dev_base->units[i].enabled = r;
+ dev_base->units[i].present = r;
+ dev_base->units[i].valid = r;
+ dev_base->units[i].unit_num = i;
+ dev_base->units[i].scsi_num = i * 10;
+ if (dev_base->units[i].present) {
+ READLONG(PISCSI_CMD_CYLS, dev_base->units[i].c);
+ READSHORT(PISCSI_CMD_HEADS, dev_base->units[i].h);
+ READSHORT(PISCSI_CMD_SECS, dev_base->units[i].s);
+
+ debugval(PISCSI_DBG_VAL1, dev_base->units[i].c);
+ debugval(PISCSI_DBG_VAL2, dev_base->units[i].h);
+ debugval(PISCSI_DBG_VAL3, dev_base->units[i].s);
+ debug(PISCSI_DBG_MSG, DBG_CHS);
+ }
+ dev_base->units[i].change_num++;
+ }
+
+ return dev;
+}
+
+static uint8_t* __attribute__((used)) expunge(struct Library *dev asm("a6"))
+{
+ debug(PISCSI_DBG_MSG, DBG_CLEANUP);
+ /*if (dev_base->open_count)
+ return 0;
+ FreeMem(dev_base, sizeof(struct piscsi_base));*/
+ return 0;
+}
+
+static void __attribute__((used)) open(struct Library *dev asm("a6"), struct IOExtTD *iotd asm("a1"), uint32_t num asm("d0"), uint32_t flags asm("d1"))
+{
+ //struct Node* node = (struct Node*)iotd;
+ int io_err = IOERR_OPENFAIL;
+
+ //WRITESHORT(PISCSI_CMD_DEBUGME, 1);
+
+ int unit_num = 0;
+ WRITELONG(PISCSI_CMD_DRVNUM, num);
+ READLONG(PISCSI_CMD_DRVNUM, unit_num);
+
+ debugval(PISCSI_DBG_VAL1, unit_num);
+ debugval(PISCSI_DBG_VAL2, flags);
+ debugval(PISCSI_DBG_VAL3, num);
+ debug(PISCSI_DBG_MSG, DBG_OPENDEV);
+
+ if (iotd && unit_num < NUM_UNITS) {
+ if (dev_base->units[unit_num].enabled && dev_base->units[unit_num].present) {
+ io_err = 0;
+ iotd->iotd_Req.io_Unit = (struct Unit*)&dev_base->units[unit_num].unit;
+ iotd->iotd_Req.io_Unit->unit_flags = UNITF_ACTIVE;
+ iotd->iotd_Req.io_Unit->unit_OpenCnt = 1;
+ }
+ }
+
+ iotd->iotd_Req.io_Error = io_err;
+ ((struct Library *)dev_base->pi_dev)->lib_OpenCnt++;
+}
+
+static uint8_t* __attribute__((used)) close(struct Library *dev asm("a6"), struct IOExtTD *iotd asm("a1"))
+{
+ ((struct Library *)dev_base->pi_dev)->lib_OpenCnt--;
+ return 0;
+}
+
+static void __attribute__((used)) begin_io(struct Library *dev asm("a6"), struct IORequest *io asm("a1"))
+{
+ if (dev_base == NULL || io == NULL)
+ return;
+
+ struct piscsi_unit *u;
+ struct Node* node = (struct Node*)io;
+ u = (struct piscsi_unit *)io->io_Unit;
+
+ if (node == NULL || u == NULL)
+ return;
+
+ debugval(PISCSI_DBG_VAL1, io->io_Command);
+ debugval(PISCSI_DBG_VAL2, io->io_Flags);
+ debugval(PISCSI_DBG_VAL3, (io->io_Flags & IOF_QUICK));
+ debug(PISCSI_DBG_MSG, DBG_BEGINIO);
+ io->io_Error = piscsi_perform_io(u, io);
+
+ if (!(io->io_Flags & IOF_QUICK)) {
+ ReplyMsg(&io->io_Message);
+ }
+}
+
+static uint32_t __attribute__((used)) abort_io(struct Library *dev asm("a6"), struct IORequest *io asm("a1"))
+{
+ debug(PISCSI_DBG_MSG, DBG_ABORTIO);
+ if (!io) return IOERR_NOCMD;
+ io->io_Error = IOERR_ABORTED;
+
+ return IOERR_ABORTED;
+}
+
+uint8_t piscsi_rw(struct piscsi_unit *u, struct IORequest *io) {
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct IOExtTD *iotd = (struct IOExtTD *)io;
+
+ uint8_t* data;
+ uint32_t len;
+ //uint32_t block, num_blocks;
+ uint8_t sderr = 0;
+
+ data = iotd->iotd_Req.io_Data;
+ len = iotd->iotd_Req.io_Length;
+
+ if (data == 0) {
+ return IOERR_BADADDRESS;
+ }
+ if (len < PISCSI_BLOCK_SIZE) {
+ iostd->io_Actual = 0;
+ return IOERR_BADLENGTH;
+ }
+
+ switch (io->io_Command) {
+ case TD_WRITE64:
+ case NSCMD_TD_WRITE64:
+ case TD_FORMAT64:
+ case NSCMD_TD_FORMAT64:
+ WRITELONG(PISCSI_CMD_ADDR1, iostd->io_Offset);
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITELONG(PISCSI_CMD_ADDR4, iostd->io_Actual);
+ WRITESHORT(PISCSI_CMD_WRITE64, u->unit_num);
+ break;
+ case TD_READ64:
+ case NSCMD_TD_READ64:
+ WRITELONG(PISCSI_CMD_ADDR1, iostd->io_Offset);
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITELONG(PISCSI_CMD_ADDR4, iostd->io_Actual);
+ WRITESHORT(PISCSI_CMD_READ64, u->unit_num);
+ break;
+ case TD_FORMAT:
+ case CMD_WRITE:
+ WRITELONG(PISCSI_CMD_ADDR1, (iostd->io_Offset >> 9));
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_WRITE, u->unit_num);
+ break;
+ case CMD_READ:
+ WRITELONG(PISCSI_CMD_ADDR1, (iostd->io_Offset >> 9));
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_READ, u->unit_num);
+ break;
+ }
+
+ if (sderr) {
+ iostd->io_Actual = 0;
+
+ if (sderr & SCSIERR_TIMEOUT)
+ return TDERR_DiskChanged;
+ if (sderr & SCSIERR_PARAM)
+ return TDERR_SeekError;
+ if (sderr & SCSIERR_ADDRESS)
+ return TDERR_SeekError;
+ if (sderr & (SCSIERR_ERASESEQ | SCSIERR_ERASERES))
+ return TDERR_BadSecPreamble;
+ if (sderr & SCSIERR_CRC)
+ return TDERR_BadSecSum;
+ if (sderr & SCSIERR_ILLEGAL)
+ return TDERR_TooFewSecs;
+ if (sderr & SCSIERR_IDLE)
+ return TDERR_PostReset;
+
+ return TDERR_SeekError;
+ } else {
+ iostd->io_Actual = iotd->iotd_Req.io_Length;
+ }
+
+ return 0;
+}
+
+#define PISCSI_ID_STRING "PISTORM Fake SCSI Disk 0.1 1111111111111111"
+
+uint8_t piscsi_scsi(struct piscsi_unit *u, struct IORequest *io)
+{
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct SCSICmd *scsi = iostd->io_Data;
+ //uint8_t* registers = sdu->sdu_Registers;
+ uint8_t *data = (uint8_t *)scsi->scsi_Data;
+ uint32_t i, block = 0, blocks = 0, maxblocks = 0;
+ uint8_t err = 0;
+ uint8_t write = 0;
+
+ debugval(PISCSI_DBG_VAL1, iostd->io_Length);
+ debugval(PISCSI_DBG_VAL2, scsi->scsi_Command[0]);
+ debugval(PISCSI_DBG_VAL3, scsi->scsi_Command[1]);
+ debugval(PISCSI_DBG_VAL4, scsi->scsi_Command[2]);
+ debugval(PISCSI_DBG_VAL5, scsi->scsi_CmdLength);
+ debug(PISCSI_DBG_MSG, DBG_SCSICMD);
+
+ //maxblocks = u->s * u->c * u->h;
+
+ if (scsi->scsi_CmdLength < 6) {
+ return IOERR_BADLENGTH;
+ }
+
+ if (scsi->scsi_Command == NULL) {
+ return IOERR_BADADDRESS;
+ }
+
+ scsi->scsi_Actual = 0;
+ //iostd->io_Actual = sizeof(*scsi);
+
+ switch (scsi->scsi_Command[0]) {
+ case SCSICMD_TEST_UNIT_READY:
+ err = 0;
+ break;
+
+ case SCSICMD_INQUIRY:
+ for (i = 0; i < scsi->scsi_Length; i++) {
+ uint8_t val = 0;
+
+ switch (i) {
+ case 0: // SCSI device type: direct-access device
+ val = (0 << 5) | 0;
+ break;
+ case 1: // RMB = 1
+ val = (1 << 7);
+ break;
+ case 2: // VERSION = 0
+ val = 0;
+ break;
+ case 3: // NORMACA=0, HISUP = 0, RESPONSE_DATA_FORMAT = 2
+ val = (0 << 5) | (0 << 4) | 2;
+ break;
+ case 4: // ADDITIONAL_LENGTH = 44 - 4
+ val = 44 - 4;
+ break;
+ default:
+ if (i >= 8 && i < 44)
+ val = PISCSI_ID_STRING[i - 8];
+ else
+ val = 0;
+ break;
+ }
+ data[i] = val;
+ }
+ scsi->scsi_Actual = i;
+ err = 0;
+ break;
+
+ case SCSICMD_WRITE_6:
+ write = 1;
+ case SCSICMD_READ_6:
+ //block = *(uint32_t *)(&scsi->scsi_Command[0]) & 0x001FFFFF;
+ block = scsi->scsi_Command[1] & 0x1f;
+ block = (block << 8) | scsi->scsi_Command[2];
+ block = (block << 8) | scsi->scsi_Command[3];
+ blocks = scsi->scsi_Command[4];
+ debugval(PISCSI_DBG_VAL1, (uint32_t)scsi->scsi_Command);
+ debug(PISCSI_DBG_MSG, DBG_SCSICMD_RW6);
+ goto scsireadwrite;
+ case SCSICMD_WRITE_10:
+ write = 1;
+ case SCSICMD_READ_10:
+ debugval(PISCSI_DBG_VAL1, (uint32_t)scsi->scsi_Command);
+ debug(PISCSI_DBG_MSG, DBG_SCSICMD_RW10);
+ //block = *(uint32_t *)(&scsi->scsi_Command[2]);
+ block = scsi->scsi_Command[2];
+ block = (block << 8) | scsi->scsi_Command[3];
+ block = (block << 8) | scsi->scsi_Command[4];
+ block = (block << 8) | scsi->scsi_Command[5];
+
+ //blocks = *(uint16_t *)(&scsi->scsi_Command[7]);
+ blocks = scsi->scsi_Command[7];
+ blocks = (blocks << 8) | scsi->scsi_Command[8];
+
+scsireadwrite:;
+ WRITESHORT(PISCSI_CMD_DRVNUM, (u->scsi_num));
+ READLONG(PISCSI_CMD_BLOCKS, maxblocks);
+ if (block + blocks > maxblocks || blocks == 0) {
+ err = IOERR_BADADDRESS;
+ break;
+ }
+ if (data == NULL) {
+ err = IOERR_BADADDRESS;
+ break;
+ }
+
+ if (write == 0) {
+ WRITELONG(PISCSI_CMD_ADDR1, block);
+ WRITELONG(PISCSI_CMD_ADDR2, (blocks << 9));
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_READ, u->unit_num);
+ }
+ else {
+ WRITELONG(PISCSI_CMD_ADDR1, block);
+ WRITELONG(PISCSI_CMD_ADDR2, (blocks << 9));
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_WRITE, u->unit_num);
+ }
+
+ scsi->scsi_Actual = scsi->scsi_Length;
+ err = 0;
+ break;
+
+ case SCSICMD_READ_CAPACITY_10:
+ if (scsi->scsi_CmdLength < 10) {
+ err = HFERR_BadStatus;
+ break;
+ }
+
+ if (scsi->scsi_Length < 8) {
+ err = IOERR_BADLENGTH;
+ break;
+ }
+
+ WRITESHORT(PISCSI_CMD_DRVNUM, (u->scsi_num));
+ READLONG(PISCSI_CMD_BLOCKS, blocks);
+ ((uint32_t*)data)[0] = blocks - 1;
+ ((uint32_t*)data)[1] = PISCSI_BLOCK_SIZE;
+
+ scsi->scsi_Actual = 8;
+ err = 0;
+
+ break;
+ case SCSICMD_MODE_SENSE_6:
+ data[0] = 3 + 8 + 0x16;
+ data[1] = 0; // MEDIUM TYPE
+ data[2] = 0;
+ data[3] = 8;
+
+ debugval(PISCSI_DBG_VAL1, ((uint32_t)scsi->scsi_Command));
+ debug(PISCSI_DBG_MSG, DBG_SCSI_DEBUG_MODESENSE_6);
+
+ WRITESHORT(PISCSI_CMD_DRVNUM, (u->scsi_num));
+ READLONG(PISCSI_CMD_BLOCKS, maxblocks);
+ (blocks = (maxblocks - 1) & 0xFFFFFF);
+
+ *((uint32_t *)&data[4]) = blocks;
+ *((uint32_t *)&data[8]) = PISCSI_BLOCK_SIZE;
+
+ switch (((UWORD)scsi->scsi_Command[2] << 8) | scsi->scsi_Command[3]) {
+ case 0x0300: { // Format Device Mode
+ debug(PISCSI_DBG_MSG, DBG_SCSI_FORMATDEVICE);
+ uint8_t *datext = data + 12;
+ datext[0] = 0x03;
+ datext[1] = 0x16;
+ datext[2] = 0x00;
+ datext[3] = 0x01;
+ *((uint32_t *)&datext[4]) = 0;
+ *((uint32_t *)&datext[8]) = 0;
+ *((uint16_t *)&datext[10]) = u->s;
+ *((uint16_t *)&datext[12]) = PISCSI_BLOCK_SIZE;
+ datext[14] = 0x00;
+ datext[15] = 0x01;
+ *((uint32_t *)&datext[16]) = 0;
+ datext[20] = 0x80;
+
+ scsi->scsi_Actual = data[0] + 1;
+ err = 0;
+ break;
+ }
+ case 0x0400: // Rigid Drive Geometry
+ debug(PISCSI_DBG_MSG, DBG_SCSI_RDG);
+ uint8_t *datext = data + 12;
+ datext[0] = 0x04;
+ *((uint32_t *)&datext[1]) = u->c;
+ datext[1] = 0x16;
+ datext[5] = u->h;
+ datext[6] = 0x00;
+ *((uint32_t *)&datext[6]) = 0;
+ *((uint32_t *)&datext[10]) = 0;
+ *((uint32_t *)&datext[13]) = u->c;
+ datext[17] = 0;
+ *((uint32_t *)&datext[18]) = 0;
+ *((uint16_t *)&datext[20]) = 5400;
+
+ scsi->scsi_Actual = data[0] + 1;
+ err = 0;
+ break;
+
+ default:
+ debugval(PISCSI_DBG_VAL1, (((UWORD)scsi->scsi_Command[2] << 8) | scsi->scsi_Command[3]));
+ debug(PISCSI_DBG_MSG, DBG_SCSI_UNKNOWN_MODESENSE);
+ err = HFERR_BadStatus;
+ break;
+ }
+ break;
+
+ case SCSICMD_READ_DEFECT_DATA_10:
+ break;
+ case SCSICMD_CHANGE_DEFINITION:
+ break;
+
+ default:
+ debugval(PISCSI_DBG_VAL1, scsi->scsi_Command[0]);
+ debug(PISCSI_DBG_MSG, DBG_SCSI_UNKNOWN_COMMAND);
+ err = HFERR_BadStatus;
+ break;
+ }
+
+ if (err != 0) {
+ debugval(PISCSI_DBG_VAL1, err);
+ debug(PISCSI_DBG_MSG, DBG_SCSIERR);
+ scsi->scsi_Actual = 0;
+ }
+
+ return err;
+}
+
+uint16_t ns_support[] = {
+ NSCMD_DEVICEQUERY,
+ CMD_RESET,
+ CMD_READ,
+ CMD_WRITE,
+ CMD_UPDATE,
+ CMD_CLEAR,
+ CMD_START,
+ CMD_STOP,
+ CMD_FLUSH,
+ TD_MOTOR,
+ TD_SEEK,
+ TD_FORMAT,
+ TD_REMOVE,
+ TD_CHANGENUM,
+ TD_CHANGESTATE,
+ TD_PROTSTATUS,
+ TD_GETDRIVETYPE,
+ TD_GETGEOMETRY,
+ TD_ADDCHANGEINT,
+ TD_REMCHANGEINT,
+ HD_SCSICMD,
+ NSCMD_TD_READ64,
+ NSCMD_TD_WRITE64,
+ NSCMD_TD_SEEK64,
+ NSCMD_TD_FORMAT64,
+ 0,
+};
+
+#define DUMMYCMD iostd->io_Actual = 0; break;
+uint8_t piscsi_perform_io(struct piscsi_unit *u, struct IORequest *io) {
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct IOExtTD *iotd = (struct IOExtTD *)io;
+
+ //uint8_t *data;
+ //uint32_t len;
+ //uint32_t offset;
+ //struct DriveGeometry *geom;
+ uint8_t err = 0;
+
+ if (!u->enabled) {
+ return IOERR_OPENFAIL;
+ }
+
+ //data = iotd->iotd_Req.io_Data;
+ //len = iotd->iotd_Req.io_Length;
+
+ if (io->io_Error == IOERR_ABORTED) {
+ return io->io_Error;
+ }
+
+ debugval(PISCSI_DBG_VAL1, io->io_Command);
+ debugval(PISCSI_DBG_VAL2, io->io_Flags);
+ debugval(PISCSI_DBG_VAL3, iostd->io_Length);
+ debug(PISCSI_DBG_MSG, DBG_IOCMD);
+
+ switch (io->io_Command) {
+ case NSCMD_DEVICEQUERY: {
+ struct NSDeviceQueryResult *res = (struct NSDeviceQueryResult *)iotd->iotd_Req.io_Data;
+ res->DevQueryFormat = 0;
+ res->SizeAvailable = 16;;
+ res->DeviceType = NSDEVTYPE_TRACKDISK;
+ res->DeviceSubType = 0;
+ res->SupportedCommands = ns_support;
+
+ iostd->io_Actual = 16;
+ return 0;
+ break;
+ }
+ case CMD_CLEAR:
+ /* Invalidate read buffer */
+ DUMMYCMD;
+ case CMD_UPDATE:
+ /* Flush write buffer */
+ DUMMYCMD;
+ case TD_PROTSTATUS:
+ DUMMYCMD;
+ case TD_CHANGENUM:
+ iostd->io_Actual = u->change_num;
+ break;
+ case TD_REMOVE:
+ DUMMYCMD;
+ case TD_CHANGESTATE:
+ DUMMYCMD;
+ case TD_GETDRIVETYPE:
+ iostd->io_Actual = DG_DIRECT_ACCESS;
+ break;
+ case TD_MOTOR:
+ iostd->io_Actual = u->motor;
+ u->motor = iostd->io_Length ? 1 : 0;
+ break;
+
+ case TD_FORMAT:
+ case TD_FORMAT64:
+ case NSCMD_TD_FORMAT64:
+ case TD_READ64:
+ case NSCMD_TD_READ64:
+ case TD_WRITE64:
+ case NSCMD_TD_WRITE64:
+ case CMD_WRITE:
+ case CMD_READ:
+ err = piscsi_rw(u, io);
+ break;
+ case HD_SCSICMD:
+ //err = 0;
+ err = piscsi_scsi(u, io);
+ break;
+ default: {
+ //int cmd = io->io_Command;
+ debug(PISCSI_DBG_MSG, DBG_IOCMD_UNHANDLED);
+ err = IOERR_NOCMD;
+ break;
+ }
+ }
+
+ return err;
+}
+#undef DUMMYCMD
+
+static uint32_t device_vectors[] = {
+ (uint32_t)open,
+ (uint32_t)close,
+ (uint32_t)expunge,
+ 0, //extFunc not used here
+ (uint32_t)begin_io,
+ (uint32_t)abort_io,
+ -1
+};
+
+const uint32_t auto_init_tables[4] = {
+ sizeof(struct Library),
+ (uint32_t)device_vectors,
+ 0,
+ (uint32_t)init_device
+};
--- /dev/null
+/*
+ * Based on:
+ * Amiga ZZ9000 USB Storage Driver (ZZ9000USBStorage.device)
+ * Copyright (C) 2016-2020, Lukas F. Hartmann <lukas@mntre.com>
+ * Based on code Copyright (C) 2016, Jason S. McMullan <jason.mcmullan@gmail.com>
+ * All rights reserved.
+ *
+ * Licensed under the MIT License:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <exec/resident.h>
+#include <exec/errors.h>
+#include <exec/memory.h>
+#include <exec/lists.h>
+#include <exec/alerts.h>
+#include <exec/tasks.h>
+#include <exec/io.h>
+#include <exec/execbase.h>
+
+#include <libraries/expansion.h>
+
+#include <devices/trackdisk.h>
+#include <devices/timer.h>
+#include <devices/scsidisk.h>
+
+#include <dos/filehandler.h>
+
+#include <proto/exec.h>
+#include <proto/disk.h>
+#include <proto/expansion.h>
+
+#include <clib/debug_protos.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "../piscsi-enums.h"
+
+#define WRITESHORT(cmd, val) *(unsigned short *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+#define WRITELONG(cmd, val) *(unsigned long *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+#define WRITEBYTE(cmd, val) *(unsigned char *)((unsigned long)(PISCSI_OFFSET+cmd)) = val;
+
+#define READSHORT(cmd, var) var = *(volatile unsigned short *)(PISCSI_OFFSET + cmd);
+#define READLONG(cmd, var) var = *(volatile unsigned long *)(PISCSI_OFFSET + cmd);
+
+#pragma pack(4)
+struct piscsi_base {
+ struct Device* pi_dev;
+ struct piscsi_unit {
+ struct Unit unit;
+ uint32_t regs_ptr;
+
+ uint8_t enabled;
+ uint8_t present;
+ uint8_t valid;
+ uint8_t read_only;
+ uint8_t motor;
+ uint8_t unit_num;
+ uint16_t h, s;
+ uint32_t c;
+
+ uint32_t change_num;
+ } units[NUM_UNITS];
+};
+
+struct ExecBase* SysBase = NULL;
+
+#ifdef _FSCSIDEV
+const char DevName[] = "scsi.device";
+#elif _FSCSI2ND
+const char DevName[] = "2nd.scsi.device";
+#else
+const char DevName[] = "pi-scsi.device";
+#endif
+const char DevIdString[] = "Pi-SCSI 0.1";
+
+const UWORD DevVersion = 43;
+const UWORD DevRevision = 10;
+
+#include "stabs.h"
+
+struct piscsi_base *dev_base = NULL;
+
+struct WBStartup *_WBenchMsg = NULL;
+
+//#define exit(...)
+//#define debug(...)
+#define KPrintF(...)
+#define debug(...)
+#define debugval(...)
+//#define debug(c, v) WRITESHORT(c, v)
+//#define debugval(c, v) WRITELONG(c, v)
+
+//#define bug(x,args...) KPrintF(x ,##args);
+//#define debug(x,args...) bug("%s:%ld " x "\n", __func__, (unsigned long)__LINE__ ,##args)
+
+uint8_t piscsi_perform_io(struct piscsi_unit *u, struct IORequest *io);
+uint8_t piscsi_rw(struct piscsi_unit *u, struct IORequest *io, uint32_t offset, uint8_t write);
+uint8_t piscsi_scsi(struct piscsi_unit *u, struct IORequest *io);
+
+extern void* DOSBase[2];
+
+uint32_t __UserDevInit(struct Device* dev) {
+ //uint8_t* registers = NULL;
+ SysBase = *(struct ExecBase **)4L;
+
+ KPrintF("Initializing devices.\n");
+ debug(PISCSI_DBG_MSG, DBG_INIT);
+
+ dev_base = AllocMem(sizeof(struct piscsi_base), MEMF_PUBLIC | MEMF_CLEAR);
+ dev_base->pi_dev = dev;
+
+ for (int i = 0; i < NUM_UNITS; i++) {
+ uint16_t r = 0;
+ WRITESHORT(PISCSI_CMD_DRVNUM, i);
+ dev_base->units[i].regs_ptr = PISCSI_OFFSET;
+ READSHORT(PISCSI_CMD_DRVTYPE, r);
+ dev_base->units[i].enabled = r;
+ dev_base->units[i].present = r;
+ dev_base->units[i].valid = r;
+ dev_base->units[i].unit_num = i;
+ if (dev_base->units[i].present) {
+ READLONG(PISCSI_CMD_CYLS, dev_base->units[i].c);
+ READSHORT(PISCSI_CMD_HEADS, dev_base->units[i].h);
+ READSHORT(PISCSI_CMD_SECS, dev_base->units[i].s);
+ KPrintF("C/H/S: %ld / %ld / %ld\n", dev_base->units[i].c, dev_base->units[i].h, dev_base->units[i].s);
+
+ debugval(PISCSI_DBG_VAL1, dev_base->units[i].c);
+ debugval(PISCSI_DBG_VAL2, dev_base->units[i].h);
+ debugval(PISCSI_DBG_VAL3, dev_base->units[i].s);
+ debug(PISCSI_DBG_MSG, DBG_CHS);
+ }
+ dev_base->units[i].change_num++;
+ // Send any reset signal to the "SCSI" device here.
+ }
+
+ return 1;
+}
+
+uint32_t __UserDevCleanup(void) {
+ KPrintF("Cleaning up.\n");
+ debug(PISCSI_DBG_MSG, DBG_CLEANUP);
+ FreeMem(dev_base, sizeof(struct piscsi_base));
+ return 0;
+}
+
+uint32_t __UserDevOpen(struct IOExtTD *iotd, uint32_t num, uint32_t flags) {
+ struct Node* node = (struct Node*)iotd;
+ int io_err = IOERR_OPENFAIL;
+
+ //WRITESHORT(PISCSI_CMD_DEBUGME, 1);
+
+ int unit_num = 0;
+ WRITELONG(PISCSI_CMD_DRVNUM, num);
+ READLONG(PISCSI_CMD_DRVNUM, unit_num);
+
+ debugval(PISCSI_DBG_VAL1, unit_num);
+ debugval(PISCSI_DBG_VAL2, flags);
+ debugval(PISCSI_DBG_VAL3, num);
+ debug(PISCSI_DBG_MSG, DBG_OPENDEV);
+ KPrintF("Opening device %ld Flags: %ld (%lx)\n", unit_num, flags, flags);
+
+ if (iotd && unit_num < NUM_UNITS) {
+ if (dev_base->units[unit_num].enabled && dev_base->units[unit_num].present) {
+ io_err = 0;
+ iotd->iotd_Req.io_Unit = (struct Unit*)&dev_base->units[unit_num].unit;
+ iotd->iotd_Req.io_Unit->unit_flags = UNITF_ACTIVE;
+ iotd->iotd_Req.io_Unit->unit_OpenCnt = 1;
+ }
+ }
+
+skip:;
+ iotd->iotd_Req.io_Error = io_err;
+
+ return io_err;
+}
+
+uint32_t __UserDevClose(struct IOExtTD *iotd) {
+ return 0;
+}
+
+void exit(int status) { }
+
+ADDTABL_1(__BeginIO,a1);
+void __BeginIO(struct IORequest *io) {
+ if (dev_base == NULL || io == NULL)
+ return;
+
+ struct piscsi_unit *u;
+ struct Node* node = (struct Node*)io;
+ u = (struct piscsi_unit *)io->io_Unit;
+
+ if (node == NULL || u == NULL)
+ return;
+
+ debugval(PISCSI_DBG_VAL1, io->io_Command);
+ debugval(PISCSI_DBG_VAL2, io->io_Flags);
+ debugval(PISCSI_DBG_VAL3, (io->io_Flags & IOF_QUICK));
+ debug(PISCSI_DBG_MSG, DBG_BEGINIO);
+ KPrintF("io_Command = %ld, io_Flags = 0x%lx quick = %lx\n", io->io_Command, io->io_Flags, (io->io_Flags & IOF_QUICK));
+ io->io_Error = piscsi_perform_io(u, io);
+
+ if (!(io->io_Flags & IOF_QUICK)) {
+ ReplyMsg(&io->io_Message);
+ }
+}
+
+ADDTABL_1(__AbortIO,a1);
+void __AbortIO(struct IORequest* io) {
+ debug(PISCSI_DBG_MSG, DBG_ABORTIO);
+ KPrintF("AbortIO!\n");
+ if (!io) return;
+ io->io_Error = IOERR_ABORTED;
+}
+
+uint8_t piscsi_rw(struct piscsi_unit *u, struct IORequest *io, uint32_t offset, uint8_t write) {
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct IOExtTD *iotd = (struct IOExtTD *)io;
+
+ uint8_t* data;
+ uint32_t len, num_blocks;
+ uint32_t block, max_addr;
+ uint8_t sderr;
+
+ data = iotd->iotd_Req.io_Data;
+ len = iotd->iotd_Req.io_Length;
+ //uint32_t offset2 = iostd->io_Offset;
+
+ max_addr = 0xffffffff;
+
+ // well... if we had 64 bits this would make sense
+ if ((offset > max_addr) || (offset+len > max_addr))
+ return IOERR_BADADDRESS;
+ if (data == 0)
+ return IOERR_BADADDRESS;
+ if (len < PISCSI_BLOCK_SIZE) {
+ iostd->io_Actual = 0;
+ return IOERR_BADLENGTH;
+ }
+
+ //block = offset;// >> SD_SECTOR_SHIFT;
+ //num_blocks = len;// >> SD_SECTOR_SHIFT;
+ sderr = 0;
+
+ if (write) {
+ //uint32_t retries = 10;
+ //KPrintF("Write %lx -> %lx %lx\n", (uint32_t)data, offset, len);
+ WRITELONG(PISCSI_CMD_ADDR1, (offset >> 9));
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_WRITE, u->unit_num);
+ } else {
+ //KPrintF("read %lx %lx -> %lx\n", offset, len, (uint32_t)data);
+ WRITELONG(PISCSI_CMD_ADDR1, (offset >> 9));
+ WRITELONG(PISCSI_CMD_ADDR2, len);
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_READ, u->unit_num);
+ }
+
+ if (sderr) {
+ iostd->io_Actual = 0;
+
+ if (sderr & SCSIERR_TIMEOUT)
+ return TDERR_DiskChanged;
+ if (sderr & SCSIERR_PARAM)
+ return TDERR_SeekError;
+ if (sderr & SCSIERR_ADDRESS)
+ return TDERR_SeekError;
+ if (sderr & (SCSIERR_ERASESEQ | SCSIERR_ERASERES))
+ return TDERR_BadSecPreamble;
+ if (sderr & SCSIERR_CRC)
+ return TDERR_BadSecSum;
+ if (sderr & SCSIERR_ILLEGAL)
+ return TDERR_TooFewSecs;
+ if (sderr & SCSIERR_IDLE)
+ return TDERR_PostReset;
+
+ return TDERR_SeekError;
+ } else {
+ iostd->io_Actual = len;
+ }
+
+ return 0;
+}
+
+#define PISCSI_ID_STRING "PISTORM Fake SCSI Disk 0.1 1111111111111111"
+
+uint8_t piscsi_scsi(struct piscsi_unit *u, struct IORequest *io)
+{
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct SCSICmd *scsi = iostd->io_Data;
+ //uint8_t* registers = sdu->sdu_Registers;
+ uint8_t *data = (uint8_t *)scsi->scsi_Data;
+ uint32_t i, block, blocks, maxblocks;
+ uint8_t err = 0;
+
+ KPrintF("SCSI len=%ld, cmd = %02lx %02lx %02lx ... (%ld)\n",
+ iostd->io_Length, scsi->scsi_Command[0],
+ scsi->scsi_Command[1], scsi->scsi_Command[2],
+ scsi->scsi_CmdLength);
+
+ debugval(PISCSI_DBG_VAL1, iostd->io_Length);
+ debugval(PISCSI_DBG_VAL2, scsi->scsi_Command[0]);
+ debugval(PISCSI_DBG_VAL3, scsi->scsi_Command[1]);
+ debugval(PISCSI_DBG_VAL4, scsi->scsi_Command[2]);
+ debugval(PISCSI_DBG_VAL5, scsi->scsi_CmdLength);
+ debug(PISCSI_DBG_MSG, DBG_SCSICMD);
+
+ //maxblocks = u->s * u->c * u->h;
+
+ if (scsi->scsi_CmdLength < 6) {
+ //KPrintF("SCSICMD BADLENGTH2");
+ return IOERR_BADLENGTH;
+ }
+
+ if (scsi->scsi_Command == NULL) {
+ //KPrintF("SCSICMD IOERR_BADADDRESS1");
+ return IOERR_BADADDRESS;
+ }
+
+ scsi->scsi_Actual = 0;
+ //iostd->io_Actual = sizeof(*scsi);
+
+ switch (scsi->scsi_Command[0]) {
+ case 0x00: // TEST_UNIT_READY
+ err = 0;
+ break;
+
+ case 0x12: // INQUIRY
+ for (i = 0; i < scsi->scsi_Length; i++) {
+ uint8_t val = 0;
+
+ switch (i) {
+ case 0: // SCSI device type: direct-access device
+ val = (0 << 5) | 0;
+ break;
+ case 1: // RMB = 1
+ val = (1 << 7);
+ break;
+ case 2: // VERSION = 0
+ val = 0;
+ break;
+ case 3: // NORMACA=0, HISUP = 0, RESPONSE_DATA_FORMAT = 2
+ val = (0 << 5) | (0 << 4) | 2;
+ break;
+ case 4: // ADDITIONAL_LENGTH = 44 - 4
+ val = 44 - 4;
+ break;
+ default:
+ if (i >= 8 && i < 44)
+ val = PISCSI_ID_STRING[i - 8];
+ else
+ val = 0;
+ break;
+ }
+ data[i] = val;
+ }
+ scsi->scsi_Actual = i;
+ err = 0;
+ break;
+
+ case 0x08: // READ (6)
+ case 0x0a: // WRITE (6)
+ block = scsi->scsi_Command[1] & 0x1f;
+ block = (block << 8) | scsi->scsi_Command[2];
+ block = (block << 8) | scsi->scsi_Command[3];
+ blocks = scsi->scsi_Command[4];
+
+ READLONG(PISCSI_CMD_BLOCKS, maxblocks);
+ if (block + blocks > maxblocks) {
+ err = IOERR_BADADDRESS;
+ break;
+ }
+ /*if (scsi->scsi_Length < (blocks << SD_SECTOR_SHIFT)) {
+ err = IOERR_BADLENGTH;
+ break;
+ }*/
+ if (data == NULL) {
+ err = IOERR_BADADDRESS;
+ break;
+ }
+
+ if (scsi->scsi_Command[0] == 0x08) {
+ //KPrintF("scsi_read %lx %lx\n",block,blocks);
+ //KPrintF("SCSI read %lx %lx -> %lx\n", block, blocks, (uint32_t)data);
+ WRITELONG(PISCSI_CMD_ADDR2, block);
+ WRITELONG(PISCSI_CMD_ADDR2, (blocks << 9));
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_READ, u->unit_num);
+ }
+ else {
+ //KPrintF("scsi_write %lx %lx\n",block,blocks);
+ //KPrintF("SCSI write %lx -> %lx %lx\n", (uint32_t)data, block, blocks);
+ WRITELONG(PISCSI_CMD_ADDR2, block);
+ WRITELONG(PISCSI_CMD_ADDR2, (blocks << 9));
+ WRITELONG(PISCSI_CMD_ADDR3, (uint32_t)data);
+ WRITESHORT(PISCSI_CMD_WRITE, u->unit_num);
+ }
+
+ scsi->scsi_Actual = scsi->scsi_Length;
+ err = 0;
+ break;
+
+ case 0x25: // READ CAPACITY (10)
+ //KPrintF("SCSI command: Read Capacity.\n");
+ if (scsi->scsi_CmdLength < 10) {
+ err = HFERR_BadStatus;
+ break;
+ }
+
+ block = *((uint32_t*)&scsi->scsi_Command[2]);
+
+ /*if ((scsi->scsi_Command[8] & 1) || block != 0) {
+ // PMI Not supported
+ KPrintF("PMI not supported.\n");
+ err = HFERR_BadStatus;
+ break;
+ }*/
+
+ if (scsi->scsi_Length < 8) {
+ err = IOERR_BADLENGTH;
+ break;
+ }
+
+ READLONG(PISCSI_CMD_BLOCKS, blocks);
+ ((uint32_t*)data)[0] = blocks - 1;
+ ((uint32_t*)data)[1] = PISCSI_BLOCK_SIZE;
+
+ scsi->scsi_Actual = 8;
+ err = 0;
+
+ break;
+ case 0x1a: // MODE SENSE (6)
+ //KPrintF("SCSI command: Mode Sense.\n");
+ data[0] = 3 + 8 + 0x16;
+ data[1] = 0; // MEDIUM TYPE
+ data[2] = 0;
+ data[3] = 8;
+
+ READLONG(PISCSI_CMD_BLOCKS, maxblocks);
+ (blocks = (maxblocks - 1) & 0xFFFFFF);
+
+ *((uint32_t *)&data[4]) = blocks;
+ *((uint32_t *)&data[8]) = PISCSI_BLOCK_SIZE;
+
+ switch (((UWORD)scsi->scsi_Command[2] << 8) | scsi->scsi_Command[3]) {
+ case 0x0300: { // Format Device Mode
+ KPrintF("Grabbing SCSI format device mode data.\n");
+ debug(PISCSI_DBG_MSG, DBG_SCSI_FORMATDEVICE);
+ uint8_t *datext = data + 12;
+ datext[0] = 0x03;
+ datext[1] = 0x16;
+ datext[2] = 0x00;
+ datext[3] = 0x01;
+ *((uint32_t *)&datext[4]) = 0;
+ *((uint32_t *)&datext[8]) = 0;
+ *((uint16_t *)&datext[10]) = u->s;
+ *((uint16_t *)&datext[12]) = PISCSI_BLOCK_SIZE;
+ datext[14] = 0x00;
+ datext[15] = 0x01;
+ *((uint32_t *)&datext[16]) = 0;
+ datext[20] = 0x80;
+
+ scsi->scsi_Actual = data[0] + 1;
+ err = 0;
+ break;
+ }
+ case 0x0400: // Rigid Drive Geometry
+ KPrintF("Grabbing SCSI rigid drive geometry.\n");
+ debug(PISCSI_DBG_MSG, DBG_SCSI_RDG);
+ uint8_t *datext = data + 12;
+ datext[0] = 0x04;
+ *((uint32_t *)&datext[1]) = u->c;
+ datext[1] = 0x16;
+ datext[5] = u->h;
+ datext[6] = 0x00;
+ *((uint32_t *)&datext[6]) = 0;
+ *((uint32_t *)&datext[10]) = 0;
+ *((uint32_t *)&datext[13]) = u->c;
+ datext[17] = 0;
+ *((uint32_t *)&datext[18]) = 0;
+ *((uint16_t *)&datext[20]) = 5400;
+
+ scsi->scsi_Actual = data[0] + 1;
+ err = 0;
+ break;
+
+ default:
+ KPrintF("[WARN] Unhandled mode sense thing: %lx\n", ((UWORD)scsi->scsi_Command[2] << 8) | scsi->scsi_Command[3]);
+ debugval(PISCSI_DBG_VAL1, (((UWORD)scsi->scsi_Command[2] << 8) | scsi->scsi_Command[3]));
+ debug(PISCSI_DBG_MSG, DBG_SCSI_UNKNOWN_MODESENSE);
+ err = HFERR_BadStatus;
+ break;
+ }
+ break;
+
+ case 0x37: // READ DEFECT DATA (10)
+
+ break;
+
+ default:
+ debugval(PISCSI_DBG_VAL1, scsi->scsi_Command[0]);
+ debug(PISCSI_DBG_MSG, DBG_SCSI_UNKNOWN_COMMAND);
+ KPrintF("Unknown/unhandled SCSI command %lx.\n", scsi->scsi_Command[0]);
+ err = HFERR_BadStatus;
+ break;
+ }
+
+ if (err != 0) {
+ debugval(PISCSI_DBG_VAL1, err);
+ debug(PISCSI_DBG_MSG, DBG_SCSIERR);
+ KPrintF("Some SCSI error occured: %ld\n", err);
+ scsi->scsi_Actual = 0;
+ }
+
+ return err;
+}
+
+#define DUMMYCMD iostd->io_Actual = 0; break;
+uint8_t piscsi_perform_io(struct piscsi_unit *u, struct IORequest *io) {
+ struct IOStdReq *iostd = (struct IOStdReq *)io;
+ struct IOExtTD *iotd = (struct IOExtTD *)io;
+
+ uint8_t *data;
+ uint32_t len;
+ uint32_t offset;
+ //struct DriveGeometry *geom;
+ uint8_t err = 0;
+
+ if (!u->enabled) {
+ return IOERR_OPENFAIL;
+ }
+
+ data = iotd->iotd_Req.io_Data;
+ len = iotd->iotd_Req.io_Length;
+
+ if (io->io_Error == IOERR_ABORTED) {
+ return io->io_Error;
+ }
+
+ debugval(PISCSI_DBG_VAL1, io->io_Command);
+ debugval(PISCSI_DBG_VAL2, io->io_Flags);
+ debugval(PISCSI_DBG_VAL3, iostd->io_Length);
+ debug(PISCSI_DBG_MSG, DBG_IOCMD);
+ //KPrintF("cmd: %s\n",cmd_name(io->io_Command));
+ //KPrintF("IO %lx Start, io_Flags = %ld, io_Command = %ld\n", io, io->io_Flags, io->io_Command);
+
+ switch (io->io_Command) {
+ case CMD_CLEAR:
+ /* Invalidate read buffer */
+ DUMMYCMD;
+ case CMD_UPDATE:
+ /* Flush write buffer */
+ DUMMYCMD;
+ case TD_PROTSTATUS:
+ DUMMYCMD;
+ case TD_CHANGENUM:
+ iostd->io_Actual = u->change_num;
+ break;
+ case TD_REMOVE:
+ DUMMYCMD;
+ case TD_CHANGESTATE:
+ DUMMYCMD;
+ case TD_GETDRIVETYPE:
+ iostd->io_Actual = DG_DIRECT_ACCESS;
+ break;
+ case TD_MOTOR:
+ iostd->io_Actual = u->motor;
+ u->motor = iostd->io_Length ? 1 : 0;
+ break;
+
+ case TD_FORMAT:
+ offset = iotd->iotd_Req.io_Offset;
+ //err = 0;
+ err = piscsi_rw(u, io, offset, 1);
+ break;
+ case CMD_WRITE:
+ offset = iotd->iotd_Req.io_Offset;
+ //err = 0;
+ err = piscsi_rw(u, io, offset, 1);
+ break;
+ case CMD_READ:
+ offset = iotd->iotd_Req.io_Offset;
+ //err = 0;
+ err = piscsi_rw(u, io, offset, 0);
+ break;
+ case HD_SCSICMD:
+ //err = 0;
+ err = piscsi_scsi(u, io);
+ break;
+ default: {
+ int cmd = io->io_Command;
+ debug(PISCSI_DBG_MSG, DBG_IOCMD_UNHANDLED);
+ err = IOERR_NOCMD;
+ break;
+ }
+ }
+
+ return err;
+}
+#undef DUMMYCMD
+
+ADDTABL_END();
--- /dev/null
+#define NUM_UNITS 7
+#define PISCSI_OFFSET 0x80000000
+#define PISCSI_REGSIZE 0x00010000
+#define PISCSI_UPPER 0x80010000
+
+#define SCSIERR_TIMEOUT (1 << 7)
+#define SCSIERR_PARAM (1 << 6)
+#define SCSIERR_ADDRESS (1 << 5)
+#define SCSIERR_ERASESEQ (1 << 4)
+#define SCSIERR_CRC (1 << 3)
+#define SCSIERR_ILLEGAL (1 << 2)
+#define SCSIERR_ERASERES (1 << 1)
+#define SCSIERR_IDLE (1 << 0)
+
+enum piscsi_stuff {
+ PISCSI_BLOCK_SIZE = 512,
+ PISCSI_TRACK_SECTORS = 2048,
+};
+
+enum piscsi_cmds {
+ PISCSI_CMD_WRITE = 0x00,
+ PISCSI_CMD_READ = 0x02,
+ PISCSI_CMD_DRVNUM = 0x04,
+ PISCSI_CMD_DRVTYPE = 0x06,
+ PISCSI_CMD_BLOCKS = 0x08,
+ PISCSI_CMD_CYLS = 0x0A,
+ PISCSI_CMD_HEADS = 0x0C,
+ PISCSI_CMD_SECS = 0x0E,
+ PISCSI_CMD_ADDR1 = 0x10,
+ PISCSI_CMD_ADDR2 = 0x14,
+ PISCSI_CMD_ADDR3 = 0x18,
+ PISCSI_CMD_ADDR4 = 0x1C,
+ PISCSI_CMD_DEBUGME = 0x20,
+ PISCSI_CMD_DRIVER = 0x40,
+ PISCSI_CMD_NEXTPART = 0x44,
+ PISCSI_CMD_GETPART = 0x48,
+ PISCSI_CMD_GETPRIO = 0x4C,
+ PISCSI_CMD_WRITE64 = 0x50,
+ PISCSI_CMD_READ64 = 0x52,
+ PISCSI_CMD_CHECKFS = 0x60,
+ PISCSI_CMD_NEXTFS = 0x64,
+ PISCSI_CMD_COPYFS = 0x68,
+ PISCSI_CMD_FSSIZE = 0x6C,
+ PISCSI_CMD_SETFSH = 0x70,
+ PISCSI_DBG_MSG = 0x1000,
+ PISCSI_DBG_VAL1 = 0x1010,
+ PISCSI_DBG_VAL2 = 0x1014,
+ PISCSI_DBG_VAL3 = 0x1018,
+ PISCSI_DBG_VAL4 = 0x101C,
+ PISCSI_DBG_VAL5 = 0x1020,
+ PISCSI_DBG_VAL6 = 0x1024,
+ PISCSI_DBG_VAL7 = 0x1028,
+ PISCSI_DBG_VAL8 = 0x102C,
+ PISCSI_CMD_ROM = 0x4000,
+};
+
+enum piscsi_dbg_msgs {
+ DBG_INIT,
+ DBG_OPENDEV,
+ DBG_CLOSEDEV,
+ DBG_CHS,
+ DBG_IOCMD,
+ DBG_CLEANUP,
+ DBG_BEGINIO,
+ DBG_ABORTIO,
+ DBG_SCSICMD,
+ DBG_SCSI_FORMATDEVICE,
+ DBG_SCSI_RDG,
+ DBG_SCSI_UNKNOWN_MODESENSE,
+ DBG_SCSI_UNKNOWN_COMMAND,
+ DBG_SCSIERR,
+ DBG_IOCMD_UNHANDLED,
+ DBG_SCSI_DEBUG_MODESENSE_6,
+ DBG_SCSI_DEBUG_MODESENSE_10,
+ DBG_SCSICMD_RW6,
+ DBG_SCSICMD_RW10,
+};
+
+enum scsi_commands {
+ SCSICMD_TEST_UNIT_READY = 0x00,
+ SCSICMD_REWIND = 0x01,
+ SCSICMD_REQUEST_SENSE = 0x03,
+ SCSICMD_FORMAT = 0x04,
+ SCSICMD_READ_BLOCK_LIMITS = 0x05,
+ SCSICMD_REASSIGN_BLOCKS = 0x07,
+ SCSICMD_INITIALIZE_ELEMENT_STATUS = 0x07,
+ SCSICMD_READ_6 = 0x08,
+ SCSICMD_WRITE_6 = 0x0A,
+ SCSICMD_SEEK_6 = 0x0B,
+ SCSICMD_READ_REVERSE_6 = 0x0F,
+ SCSICMD_WRITE_FILEMARKS_6 = 0x10,
+ SCSICMD_SPACE_6 = 0x11,
+ SCSICMD_INQUIRY = 0x12,
+ SCSICMD_VERIFY_6 = 0x13,
+ SCSICMD_RECOVER_BUFFERED_DATA = 0x14,
+ SCSICMD_MODE_SELECT_6 = 0x15,
+ SCSICMD_RESERVE_6 = 0x16,
+ SCSICMD_RELEASE_6 = 0x17,
+ SCSICMD_COPY = 0x18,
+ SCSICMD_ERASE_6 = 0x19,
+ SCSICMD_MODE_SENSE_6 = 0x1A,
+ SCSICMD_START_STOP_UNIT = 0x1B,
+ SCSICMD_LOAD_UNLOAD = 0x1B,
+ SCSICMD_RECEIVE_DIAGNOSTIC_RESULTS = 0x1C,
+ SCSICMD_SEND_DIAGNOSTIC = 0x1D,
+ SCSICMD_PREVENT_ALLOW_MEDIUM_REMOVAL = 0x1E,
+ SCSICMD_READ_FORMAT_CAPACITIES = 0x23,
+ SCSICMD_READ_CAPACITY_10 = 0x25,
+ SCSICMD_READ_10 = 0x28,
+ SCSICMD_READ_GENERATION = 0x29,
+ SCSICMD_WRITE_10 = 0x2A,
+ SCSICMD_SEEK_10 = 0x2B,
+ SCSICMD_LOCATE_10 = 0x2B,
+ SCSICMD_ERASE_10 = 0x2C,
+ SCSICMD_READ_UPDATED_BLOCK = 0x2D,
+ SCSICMD_WRITE_AND_VERIFY_10 = 0x2E,
+ SCSICMD_VERIFY_10 = 0x2F,
+ SCSICMD_SET_LIMITS_10 = 0x33,
+ SCSICMD_PREFETCH_10 = 0x34,
+ SCSICMD_READ_POSITION = 0x34,
+ SCSICMD_SYNCHRONIZE_CACHE_10 = 0x35,
+ SCSICMD_LOCK_UNLOCK_CACHE_10 = 0x36,
+ SCSICMD_READ_DEFECT_DATA_10 = 0x37,
+ SCSICMD_INITIALIZE_ELEMENT_STATUS_WITH_RANGE = 0x37,
+ SCSICMD_MEDIUM_SCAN = 0x38,
+ SCSICMD_COMPARE = 0x39,
+ SCSICMD_COPY_AND_VERIFY = 0x3A,
+ SCSICMD_WRITE_BUFFER = 0x3B,
+ SCSICMD_READ_BUFFER = 0x3C,
+ SCSICMD_UPDATE_BLOCK = 0x3D,
+ SCSICMD_READ_LONG_10 = 0x3E,
+ SCSICMD_WRITE_LONG_10 = 0x3F,
+ SCSICMD_CHANGE_DEFINITION = 0x40,
+ SCSICMD_WRITE_SAME_10 = 0x41,
+ SCSICMD_UNMAP = 0x42,
+ SCSICMD_READ_TOC_PMA_ATIP = 0x43,
+ SCSICMD_REPORT_DENSITY_SUPPORT = 0x44,
+ SCSICMD_PLAY_AUDIO_10 = 0x45,
+ SCSICMD_GET_CONFIGURATION = 0x46,
+ SCSICMD_PLAY_AUDIO_MSF = 0x47,
+ SCSICMD_SANITIZE = 0x48,
+ SCSICMD_GET_EVENT_STATUS_NOTIFICATION = 0x4A,
+ SCSICMD_PAUSE_RESUME = 0x4B,
+ SCSICMD_LOG_SELECT = 0x4C,
+ SCSICMD_LOG_SENSE = 0x4D,
+ SCSICMD_XDWRITE_10 = 0x50,
+ SCSICMD_XPWRITE_10 = 0x51,
+ SCSICMD_READ_DISC_INFORMATION = 0x51,
+ SCSICMD_XDREAD_10 = 0x52,
+ SCSICMD_XDWRITEREAD_10 = 0x53,
+ SCSICMD_SEND_OPC_INFORMATION = 0x54,
+ SCSICMD_MODE_SELECT_10 = 0x55,
+ SCSICMD_RESERVE_10 = 0x56,
+ SCSICMD_RELEASE_10 = 0x57,
+ SCSICMD_REPAIR_TRACK = 0x58,
+ SCSICMD_MODE_SENSE_10 = 0x5A,
+ SCSICMD_CLOSE_TRACK_SESSION = 0x5B,
+ SCSICMD_READ_BUFFER_CAPACITY = 0x5C,
+ SCSICMD_SEND_CUE_SHEET = 0x5D,
+ SCSICMD_PERSISTENT_RESERVE_IN = 0x5E,
+ SCSICMD_PERSISTENT_RESERVE_OUT = 0x5F,
+ SCSICMD_EXTENDED_CDB = 0x7E,
+ SCSICMD_VARIABLELENGTH_CDB = 0x7F,
+ SCSICMD_XDWRITE_EXTENDED_16 = 0x80,
+ SCSICMD_WRITE_FILEMARKS_16 = 0x80,
+ SCSICMD_READ_REVERSE_16 = 0x81,
+ SCSICMD_3RDPARTY_COPY_OUT_CMDS = 0x83,
+ SCSICMD_3RDPARTY_COPY_IN_CMDS = 0x84,
+ SCSICMD_ATA_PASSTHROUGH_16 = 0x85,
+ SCSICMD_ACCESS_CONTROL_IN = 0x86,
+ SCSICMD_ACCESS_CONTROL_OUT = 0x87,
+ SCSICMD_READ_16 = 0x88,
+ SCSICMD_COMPARE_AND_WRITE = 0x89,
+ SCSICMD_WRITE_16 = 0x8A,
+ SCSICMD_ORWRITE = 0x8B,
+ SCSICMD_READ_ATTRIBUTE = 0x8C,
+ SCSICMD_WRITE_ATTRIBUTE = 0x8D,
+ SCSICMD_WRITE_AND_VERIFY_16 = 0x8E,
+ SCSICMD_VERIFY_16 = 0x8F,
+ SCSICMD_PREFETCH_16 = 0x90,
+ SCSICMD_SYNCHRONIZE_CACHE_16 = 0x91,
+ SCSICMD_SPACE_16 = 0x91,
+ SCSICMD_LOCK_UNLOCK_CACHE_16 = 0x92,
+ SCSICMD_LOCATE_16 = 0x92,
+ SCSICMD_WRITE_SAME_16 = 0x93,
+ SCSICMD_ERASE_16 = 0x93,
+ SCSICMD_SERVICE_ACTION_BIDIRECTIONAL = 0x9D,
+ SCSICMD_SERVICE_ACTION_IN_16 = 0x9E,
+ SCSICMD_SERVICE_ACTION_OUT_16 = 0x9F,
+ SCSICMD_REPORT_LUNS = 0xA0,
+ SCSICMD_ATA_PASSTHROUGH_12 = 0xA1,
+ SCSICMD_SECURITY_PROTOCOL_IN = 0xA2,
+ SCSICMD_MAINTENANCE_IN = 0xA3,
+ SCSICMD_MAINTENANCE_OUT = 0xA4,
+ SCSICMD_REPORT_KEY = 0xA4,
+ SCSICMD_MOVE_MEDIUM = 0xA5,
+ SCSICMD_PLAY_AUDIO_12 = 0xA5,
+ SCSICMD_EXCHANGE_MEDIUM = 0xA6,
+ SCSICMD_MOVE_MEDIUM_ATTACHED = 0xA7,
+ SCSICMD_READ_12 = 0xA8,
+ SCSICMD_SERVICE_ACTION_OUT_12 = 0xA9,
+ SCSICMD_WRITE_12 = 0xAA,
+ SCSICMD_SERVICE_ACTION_IN_12 = 0xAB,
+ SCSICMD_ERASE_12 = 0xAC,
+ SCSICMD_READ_DVD_STRUCTURE = 0xAD,
+ SCSICMD_WRITE_AND_VERIFY_12 = 0xAE,
+ SCSICMD_VERIFY_12 = 0xAF,
+ SCSICMD_SEARCH_DATA_HIGH_12 = 0xB0,
+ SCSICMD_SEARCH_DATA_EQUAL_12 = 0xB1,
+ SCSICMD_SEARCH_DATA_LOW_12 = 0xB2,
+ SCSICMD_SET_LIMITS_12 = 0xB3,
+ SCSICMD_READ_ELEMENT_STATUS_ATTACHED = 0xB4,
+ SCSICMD_SECURITY_PROTOCOL_OUT = 0xB5,
+ SCSICMD_SEND_VOLUME_TAG = 0xB6,
+ SCSICMD_READ_DEFECT_DATA_12 = 0xB7,
+ SCSICMD_READ_ELEMENT_STATUS = 0xB8,
+ SCSICMD_READ_CD_MSF = 0xB9,
+ SCSICMD_REDUNDANCY_GROUP_IN = 0xBA,
+ SCSICMD_REDUNDANCY_GROUP_OUT = 0xBB,
+ SCSICMD_SPARE_IN = 0xBC,
+ SCSICMD_SPARE_OUT = 0xBD,
+ SCSICMD_VOLUME_SET_IN = 0xBE,
+ SCSICMD_VOLUME_SET_OUT = 0xBF,
+};
+
+#define TD_READ64 24
+#define TD_WRITE64 25
+#define TD_SEEK64 26
+#define TD_FORMAT64 27
+
+#define NSCMD_TD_READ64 0xC000
+#define NSCMD_TD_WRITE64 0xC001
+#define NSCMD_TD_SEEK64 0xC002
+#define NSCMD_TD_FORMAT64 0xC003
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <endian.h>
+
+#include "config_file/config_file.h"
+#include "gpio/ps_protocol.h"
+#include "piscsi-enums.h"
+#include "piscsi.h"
+#include "platforms/amiga/hunk-reloc.h"
+
+#define BE(val) be32toh(val)
+#define BE16(val) be16toh(val)
+
+// Uncomment the line below to enable debug output
+//#define PISCSI_DEBUG
+
+#ifdef PISCSI_DEBUG
+#define DEBUG printf
+//#define DEBUG_TRIVIAL printf
+#define DEBUG_TRVIAL(...)
+
+extern void stop_cpu_emulation(uint8_t disasm_cur);
+
+static const char *op_type_names[4] = {
+ "BYTE",
+ "WORD",
+ "LONGWORD",
+ "MEM",
+};
+#else
+#define DEBUG(...)
+#define DEBUG_TRIVIAL(...)
+#define stop_cpu_emulation(...)
+#endif
+
+#ifdef FAKESTORM
+#define lseek64 lseek
+#endif
+
+extern struct emulator_config *cfg;
+
+struct piscsi_dev devs[8];
+struct piscsi_fs filesystems[NUM_FILESYSTEMS];
+
+uint8_t piscsi_num_fs = 0;
+
+uint8_t piscsi_cur_drive = 0;
+uint32_t piscsi_u32[4];
+uint32_t piscsi_dbg[8];
+uint32_t piscsi_rom_size = 0;
+uint8_t *piscsi_rom_ptr;
+
+uint32_t rom_partitions[128];
+uint32_t rom_partition_prio[128];
+uint32_t rom_partition_dostype[128];
+uint32_t rom_cur_partition = 0, rom_cur_fs = 0;
+
+extern unsigned char ac_piscsi_rom[];
+
+//static const char *partition_marker = "PART";
+
+struct hunk_info piscsi_hinfo;
+struct hunk_reloc piscsi_hreloc[256];
+
+void piscsi_init() {
+ for (int i = 0; i < 8; i++) {
+ devs[i].fd = -1;
+ devs[i].lba = 0;
+ devs[i].c = devs[i].h = devs[i].s = 0;
+ }
+
+ FILE *in = fopen("./platforms/amiga/piscsi/piscsi.rom", "rb");
+ if (in == NULL) {
+ printf("[PISCSI] Could not open PISCSI Boot ROM file for reading!\n");
+ // Zero out the boot ROM offset from the autoconfig ROM.
+ ac_piscsi_rom[20] = 0;
+ ac_piscsi_rom[21] = 0;
+ ac_piscsi_rom[22] = 0;
+ ac_piscsi_rom[23] = 0;
+ return;
+ }
+ fseek(in, 0, SEEK_END);
+ piscsi_rom_size = ftell(in);
+ fseek(in, 0, SEEK_SET);
+ piscsi_rom_ptr = malloc(piscsi_rom_size);
+ fread(piscsi_rom_ptr, piscsi_rom_size, 1, in);
+
+ fseek(in, PISCSI_DRIVER_OFFSET, SEEK_SET);
+ process_hunks(in, &piscsi_hinfo, piscsi_hreloc, PISCSI_DRIVER_OFFSET);
+
+ fclose(in);
+ printf("[PISCSI] Loaded Boot ROM.\n");
+}
+
+void piscsi_find_partitions(struct piscsi_dev *d) {
+ int fd = d->fd;
+ int cur_partition = 0;
+ uint8_t tmp;
+
+ for (int i = 0; i < 16; i++) {
+ if (d->pb[i]) {
+ free(d->pb[i]);
+ d->pb[i] = NULL;
+ }
+ }
+
+ if (!d->rdb || d->rdb->rdb_PartitionList == 0) {
+ DEBUG("[PISCSI] No partitions on disk.\n");
+ return;
+ }
+
+ char *block = malloc(512);
+
+ lseek(fd, BE(d->rdb->rdb_PartitionList) * 512, SEEK_SET);
+next_partition:;
+ read(fd, block, 512);
+
+ uint32_t first = be32toh(*((uint32_t *)&block[0]));
+ if (first != PART_IDENTIFIER) {
+ DEBUG("Entry at block %d is not a valid partition. Aborting.\n", BE(d->rdb->rdb_PartitionList));
+ return;
+ }
+
+ struct PartitionBlock *pb = (struct PartitionBlock *)block;
+ tmp = pb->pb_DriveName[0];
+ pb->pb_DriveName[tmp + 1] = 0x00;
+ DEBUG("[PISCSI] Partition %d: %s\n", cur_partition, pb->pb_DriveName + 1);
+ DEBUG("Checksum: %.8X HostID: %d\n", BE(pb->pb_ChkSum), BE(pb->pb_HostID));
+ DEBUG("Flags: %d (%.8X) Devflags: %d (%.8X)\n", BE(pb->pb_Flags), BE(pb->pb_Flags), BE(pb->pb_DevFlags), BE(pb->pb_DevFlags));
+ d->pb[cur_partition] = pb;
+
+ if (d->pb[cur_partition]->pb_Next != 0xFFFFFFFF) {
+ uint64_t next = be32toh(pb->pb_Next);
+ block = malloc(512);
+ lseek64(fd, next * 512, SEEK_SET);
+ cur_partition++;
+ DEBUG("[PISCSI] Next partition at block %d.\n", be32toh(pb->pb_Next));
+ goto next_partition;
+ }
+ DEBUG("[PISCSI] No more partitions on disk.\n");
+ d->num_partitions = cur_partition + 1;
+ d->fshd_offs = lseek64(fd, 0, SEEK_CUR);
+
+ return;
+}
+
+int piscsi_parse_rdb(struct piscsi_dev *d) {
+ int fd = d->fd;
+ int i = 0;
+ uint8_t *block = malloc(512);
+
+ lseek(fd, 0, SEEK_SET);
+ for (i = 0; i < RDB_BLOCK_LIMIT; i++) {
+ read(fd, block, 512);
+ uint32_t first = be32toh(*((uint32_t *)&block[0]));
+ if (first == RDB_IDENTIFIER)
+ goto rdb_found;
+ }
+ goto no_rdb_found;
+rdb_found:;
+ struct RigidDiskBlock *rdb = (struct RigidDiskBlock *)block;
+ DEBUG("[PISCSI] RDB found at block %d.\n", i);
+ d->c = be32toh(rdb->rdb_Cylinders);
+ d->h = be32toh(rdb->rdb_Heads);
+ d->s = be32toh(rdb->rdb_Sectors);
+ d->num_partitions = 0;
+ DEBUG("[PISCSI] RDB - first partition at block %d.\n", be32toh(rdb->rdb_PartitionList));
+ if (d->rdb)
+ free(d->rdb);
+ d->rdb = rdb;
+ sprintf(d->rdb->rdb_DriveInitName, "pi-scsi.device");
+ return 0;
+
+no_rdb_found:;
+ if (block)
+ free(block);
+
+ return -1;
+}
+
+void piscsi_refresh_drives() {
+ piscsi_num_fs = 0;
+
+ for (int i = 0; i < NUM_FILESYSTEMS; i++) {
+ if (filesystems[i].binary_data) {
+ free(filesystems[i].binary_data);
+ filesystems[i].binary_data = NULL;
+ }
+ if (filesystems[i].fhb) {
+ free(filesystems[i].fhb);
+ filesystems[i].fhb = NULL;
+ }
+ filesystems[i].h_info.current_hunk = 0;
+ filesystems[i].h_info.reloc_hunks = 0;
+ filesystems[i].FS_ID = 0;
+ filesystems[i].handler = 0;
+ }
+
+ rom_cur_fs = 0;
+
+ for (int i = 0; i < NUM_UNITS; i++) {
+ if (devs[i].fd != -1) {
+ piscsi_parse_rdb(&devs[i]);
+ piscsi_find_partitions(&devs[i]);
+ piscsi_find_filesystems(&devs[i]);
+ }
+ }
+}
+
+void piscsi_find_filesystems(struct piscsi_dev *d) {
+ if (!d->num_partitions)
+ return;
+
+ uint8_t fs_found = 0;
+
+ uint8_t *fhb_block = malloc(512);
+
+ lseek64(d->fd, d->fshd_offs, SEEK_SET);
+
+ struct FileSysHeaderBlock *fhb = (struct FileSysHeaderBlock *)fhb_block;
+ read(d->fd, fhb_block, 512);
+
+ while (BE(fhb->fhb_ID) == FS_IDENTIFIER) {
+ char *dosID = (char *)&fhb->fhb_DosType;
+#ifdef PISCSI_DEBUG
+ uint16_t *fsVer = (uint16_t *)&fhb->fhb_Version;
+
+ DEBUG("[FSHD] FSHD Block found.\n");
+ DEBUG("[FSHD] HostID: %d Next: %d Size: %d\n", BE(fhb->fhb_HostID), BE(fhb->fhb_Next), BE(fhb->fhb_SummedLongs));
+ DEBUG("[FSHD] Flags: %.8X DOSType: %c%c%c/%d\n", BE(fhb->fhb_Flags), dosID[0], dosID[1], dosID[2], dosID[3]);
+ DEBUG("[FSHD] Version: %d.%d\n", BE16(fsVer[0]), BE16(fsVer[1]));
+ DEBUG("[FSHD] Patchflags: %d Type: %d\n", BE(fhb->fhb_PatchFlags), BE(fhb->fhb_Type));
+ DEBUG("[FSHD] Task: %d Lock: %d\n", BE(fhb->fhb_Task), BE(fhb->fhb_Lock));
+ DEBUG("[FSHD] Handler: %d StackSize: %d\n", BE(fhb->fhb_Handler), BE(fhb->fhb_StackSize));
+ DEBUG("[FSHD] Prio: %d Startup: %d\n", BE(fhb->fhb_Priority), BE(fhb->fhb_Startup));
+ DEBUG("[FSHD] SegListBlocks: %d GlobalVec: %d\n", BE(fhb->fhb_Priority), BE(fhb->fhb_Startup));
+ DEBUG("[FSHD] FileSysName: %s\n", fhb->fhb_FileSysName + 1);
+#endif
+
+ for (int i = 0; i < NUM_FILESYSTEMS; i++) {
+ if (filesystems[i].FS_ID == fhb->fhb_DosType) {
+ DEBUG("[FSHD] File system %c%c%c/%d already loaded. Skipping.\n", dosID[0], dosID[1], dosID[2], dosID[3]);
+ if (BE(fhb->fhb_Next) == 0xFFFFFFFF)
+ goto fs_done;
+
+ goto skip_fs_load_lseg;
+ }
+ }
+
+ if (load_lseg(d->fd, &filesystems[piscsi_num_fs].binary_data, &filesystems[piscsi_num_fs].h_info, filesystems[piscsi_num_fs].relocs) != -1) {
+ filesystems[piscsi_num_fs].FS_ID = fhb->fhb_DosType;
+ filesystems[piscsi_num_fs].fhb = fhb;
+ printf("[FSHD] Loaded and set up file system %d: %c%c%c/%d\n", piscsi_num_fs + 1, dosID[0], dosID[1], dosID[2], dosID[3]);
+ piscsi_num_fs++;
+ }
+
+skip_fs_load_lseg:;
+ fs_found++;
+ lseek64(d->fd, BE(fhb->fhb_Next) * 512, SEEK_SET);
+ fhb_block = malloc(512);
+ fhb = (struct FileSysHeaderBlock *)fhb_block;
+ read(d->fd, fhb_block, 512);
+ }
+
+ if (!fs_found) {
+ DEBUG("[!!!FSHD] No file systems found on hard drive!\n");
+ }
+
+fs_done:;
+ if (fhb_block)
+ free(fhb_block);
+}
+
+void piscsi_map_drive(char *filename, uint8_t index) {
+ if (index > 7) {
+ printf("[PISCSI] Drive index %d out of range.\nUnable to map file %s to drive.\n", index, filename);
+ return;
+ }
+
+ int32_t tmp_fd = open(filename, O_RDWR);
+ if (tmp_fd == -1) {
+ printf("[PISCSI] Failed to open file %s, could not map drive %d.\n", filename, index);
+ return;
+ }
+
+ struct piscsi_dev *d = &devs[index];
+
+ uint64_t file_size = lseek(tmp_fd, 0, SEEK_END);
+ d->fs = file_size;
+ d->fd = tmp_fd;
+ lseek(tmp_fd, 0, SEEK_SET);
+ printf("[PISCSI] Map %d: [%s] - %llu bytes.\n", index, filename, file_size);
+
+ if (piscsi_parse_rdb(d) == -1) {
+ DEBUG("[PISCSI] No RDB found on disk, making up some CHS values.\n");
+ d->h = 16;
+ d->s = 63;
+ d->c = (file_size / 512) / (d->s * d->h);
+ }
+ printf("[PISCSI] CHS: %d %d %d\n", d->c, d->h, d->s);
+
+ piscsi_find_partitions(d);
+ piscsi_find_filesystems(d);
+}
+
+void piscsi_unmap_drive(uint8_t index) {
+ if (devs[index].fd != -1) {
+ DEBUG("[PISCSI] Unmapped drive %d.\n", index);
+ close (devs[index].fd);
+ devs[index].fd = -1;
+ }
+}
+
+char *io_cmd_name(int index) {
+ switch (index) {
+ case CMD_INVALID: return "INVALID";
+ case CMD_RESET: return "RESET";
+ case CMD_READ: return "READ";
+ case CMD_WRITE: return "WRITE";
+ case CMD_UPDATE: return "UPDATE";
+ case CMD_CLEAR: return "CLEAR";
+ case CMD_STOP: return "STOP";
+ case CMD_START: return "START";
+ case CMD_FLUSH: return "FLUSH";
+ case TD_MOTOR: return "TD_MOTOR";
+ case TD_SEEK: return "SEEK";
+ case TD_FORMAT: return "FORMAT";
+ case TD_REMOVE: return "REMOVE";
+ case TD_CHANGENUM: return "CHANGENUM";
+ case TD_CHANGESTATE: return "CHANGESTATE";
+ case TD_PROTSTATUS: return "PROTSTATUS";
+ case TD_RAWREAD: return "RAWREAD";
+ case TD_RAWWRITE: return "RAWWRITE";
+ case TD_GETDRIVETYPE: return "GETDRIVETYPE";
+ case TD_GETNUMTRACKS: return "GETNUMTRACKS";
+ case TD_ADDCHANGEINT: return "ADDCHANGEINT";
+ case TD_REMCHANGEINT: return "REMCHANGEINT";
+ case TD_GETGEOMETRY: return "GETGEOMETRY";
+ case TD_EJECT: return "EJECT";
+ case TD_LASTCOMM: return "LASTCOMM/READ64";
+ case TD_WRITE64: return "WRITE64";
+ case HD_SCSICMD: return "HD_SCSICMD";
+ case NSCMD_DEVICEQUERY: return "NSCMD_DEVICEQUERY";
+ case NSCMD_TD_READ64: return "NSCMD_TD_READ64";
+ case NSCMD_TD_WRITE64: return "NSCMD_TD_WRITE64";
+ case NSCMD_TD_FORMAT64: return "NSCMD_TD_FORMAT64";
+
+ default:
+ return "[!!!PISCSI] Unhandled IO command";
+ }
+}
+
+#define GETSCSINAME(a) case a: return ""#a"";
+#define SCSIUNHANDLED(a) return "[!!!PISCSI] Unhandled SCSI command "#a"";
+
+char *scsi_cmd_name(int index) {
+ switch(index) {
+ GETSCSINAME(SCSICMD_TEST_UNIT_READY);
+ GETSCSINAME(SCSICMD_INQUIRY);
+ GETSCSINAME(SCSICMD_READ_6);
+ GETSCSINAME(SCSICMD_WRITE_6);
+ GETSCSINAME(SCSICMD_READ_10);
+ GETSCSINAME(SCSICMD_WRITE_10);
+ GETSCSINAME(SCSICMD_READ_CAPACITY_10);
+ GETSCSINAME(SCSICMD_MODE_SENSE_6);
+ GETSCSINAME(SCSICMD_READ_DEFECT_DATA_10);
+ default:
+ return "[!!!PISCSI] Unhandled SCSI command";
+ }
+}
+
+void print_piscsi_debug_message(int index) {
+ int32_t r = 0;
+
+ switch (index) {
+ case DBG_INIT:
+ DEBUG("[PISCSI] Initializing devices.\n");
+ break;
+ case DBG_OPENDEV:
+ if (piscsi_dbg[0] != 255) {
+ DEBUG("[PISCSI] Opening device %d (%d). Flags: %d (%.2X)\n", piscsi_dbg[0], piscsi_dbg[2], piscsi_dbg[1], piscsi_dbg[1]);
+ }
+ break;
+ case DBG_CLEANUP:
+ DEBUG("[PISCSI] Cleaning up.\n");
+ break;
+ case DBG_CHS:
+ DEBUG("[PISCSI] C/H/S: %d / %d / %d\n", piscsi_dbg[0], piscsi_dbg[1], piscsi_dbg[2]);
+ break;
+ case DBG_BEGINIO:
+ DEBUG("[PISCSI] BeginIO: io_Command: %d (%s) - io_Flags = %d - quick: %d\n", piscsi_dbg[0], io_cmd_name(piscsi_dbg[0]), piscsi_dbg[1], piscsi_dbg[2]);
+ break;
+ case DBG_ABORTIO:
+ DEBUG("[PISCSI] AbortIO!\n");
+ break;
+ case DBG_SCSICMD:
+ DEBUG("[PISCSI] SCSI Command %d (%s)\n", piscsi_dbg[1], scsi_cmd_name(piscsi_dbg[1]));
+ DEBUG("Len: %d - %.2X %.2X %.2X - Command Length: %d\n", piscsi_dbg[0], piscsi_dbg[1], piscsi_dbg[2], piscsi_dbg[3], piscsi_dbg[4]);
+ break;
+ case DBG_SCSI_UNKNOWN_MODESENSE:
+ DEBUG("[!!!PISCSI] SCSI: Unknown modesense %.4X\n", piscsi_dbg[0]);
+ break;
+ case DBG_SCSI_UNKNOWN_COMMAND:
+ DEBUG("[!!!PISCSI] SCSI: Unknown command %.4X\n", piscsi_dbg[0]);
+ break;
+ case DBG_SCSIERR:
+ DEBUG("[!!!PISCSI] SCSI: An error occured: %.4X\n", piscsi_dbg[0]);
+ break;
+ case DBG_IOCMD:
+ DEBUG_TRIVIAL("[PISCSI] IO Command %d (%s)\n", piscsi_dbg[0], io_cmd_name(piscsi_dbg[0]));
+ break;
+ case DBG_IOCMD_UNHANDLED:
+ DEBUG("[!!!PISCSI] WARN: IO command %.4X (%s) is unhandled by driver.\n", piscsi_dbg[0], io_cmd_name(piscsi_dbg[0]));
+ break;
+ case DBG_SCSI_FORMATDEVICE:
+ DEBUG("[PISCSI] Get SCSI FormatDevice MODE SENSE.\n");
+ break;
+ case DBG_SCSI_RDG:
+ DEBUG("[PISCSI] Get SCSI RDG MODE SENSE.\n");
+ break;
+ case DBG_SCSICMD_RW10:
+#ifdef PISCSI_DEBUG
+ r = get_mapped_item_by_address(cfg, piscsi_dbg[0]);
+ struct SCSICmd_RW10 *rwdat = NULL;
+ char data[10];
+ if (r != -1) {
+ uint32_t addr = piscsi_dbg[0] - cfg->map_offset[r];
+ rwdat = (struct SCSICmd_RW10 *)(&cfg->map_data[r][addr]);
+ }
+ else {
+ DEBUG_TRIVIAL("[RW10] scsiData: %.8X\n", piscsi_dbg[0]);
+ for (int i = 0; i < 10; i++) {
+ data[i] = read8(piscsi_dbg[0] + i);
+ }
+ rwdat = data;
+ }
+ if (rwdat) {
+ DEBUG_TRIVIAL("[RW10] CMD: %.2X\n", rwdat->opcode);
+ DEBUG_TRIVIAL("[RW10] RDP: %.2X\n", rwdat->rdprotect_flags);
+ DEBUG_TRIVIAL("[RW10] Block: %d (%d)\n", rwdat->block, BE(rwdat->block));
+ DEBUG_TRIVIAL("[RW10] Res_Group: %.2X\n", rwdat->res_groupnum);
+ DEBUG_TRIVIAL("[RW10] Len: %d (%d)\n", rwdat->len, BE16(rwdat->len));
+ }
+#endif
+ break;
+ case DBG_SCSI_DEBUG_MODESENSE_6:
+ DEBUG_TRIVIAL("[PISCSI] SCSI ModeSense debug. Data: %.8X\n", piscsi_dbg[0]);
+ r = get_mapped_item_by_address(cfg, piscsi_dbg[0]);
+ if (r != -1) {
+#ifdef PISCSI_DEBUG
+ uint32_t addr = piscsi_dbg[0] - cfg->map_offset[r];
+ struct SCSICmd_ModeSense6 *sense = (struct SCSICmd_ModeSense6 *)(&cfg->map_data[r][addr]);
+ DEBUG_TRIVIAL("[SenseData] CMD: %.2X\n", sense->opcode);
+ DEBUG_TRIVIAL("[SenseData] DBD: %d\n", sense->reserved_dbd & 0x04);
+ DEBUG_TRIVIAL("[SenseData] PC: %d\n", (sense->pc_pagecode & 0xC0 >> 6));
+ DEBUG_TRIVIAL("[SenseData] PageCodes: %.2X %.2X\n", (sense->pc_pagecode & 0x3F), sense->subpage_code);
+ DEBUG_TRIVIAL("[SenseData] AllocLen: %d\n", sense->alloc_len);
+ DEBUG_TRIVIAL("[SenseData] Control: %.2X (%d)\n", sense->control, sense->control);
+#endif
+ }
+ else {
+ DEBUG("[!!!PISCSI] ModeSense data not immediately available.\n");
+ }
+ break;
+ default:
+ DEBUG("[!!!PISCSI] No debug message available for index %d.\n", index);
+ break;
+ }
+}
+
+#define DEBUGME_SIMPLE(i, s) case i: DEBUG(s); break;
+
+void piscsi_debugme(uint32_t index) {
+ switch (index) {
+ DEBUGME_SIMPLE(1, "[PISCSI-DEBUGME] Arrived at DiagEntry.\n");
+ DEBUGME_SIMPLE(3, "[PISCSI-DEBUGME] Init: Interrupt disable.\n");
+ DEBUGME_SIMPLE(4, "[PISCSI-DEBUGME] Init: Copy/reloc driver.\n");
+ DEBUGME_SIMPLE(5, "[PISCSI-DEBUGME] Init: InitResident.\n");
+ DEBUGME_SIMPLE(7, "[PISCSI-DEBUGME] Init: Begin partition loop.\n");
+ DEBUGME_SIMPLE(8, "[PISCSI-DEBUGME] Init: Partition loop done. Cleaning up and returning to Exec.\n");
+ DEBUGME_SIMPLE(9, "[PISCSI-DEBUGME] Init: Load file systems.\n");
+ DEBUGME_SIMPLE(10, "[PISCSI-DEBUGME] Init: AllocMem for resident.\n");
+ DEBUGME_SIMPLE(11, "[PISCSI-DEBUGME] Init: Checking if resident is loaded.\n");
+ DEBUGME_SIMPLE(22, "[PISCSI-DEBUGME] Arrived at BootEntry.\n");
+ DEBUGME_SIMPLE(30, "[PISCSI-DEBUGME] LoadFileSystems: Opening FileSystem.resource.\n");
+ DEBUGME_SIMPLE(33, "[PISCSI-DEBUGME] FileSystem.resource not available, creating.\n");
+ case 31:
+ DEBUG("[PISCSI-DEBUGME] OpenResource result: %d\n", piscsi_u32[0]);
+ break;
+ case 32:
+ DEBUG("AAAAHH!\n");
+ break;
+ default:
+ DEBUG("[!!!PISCSI-DEBUGME] No debugme message for index %d!\n", index);
+ break;
+ }
+
+ if (index == 8) {
+ stop_cpu_emulation(1);
+ }
+}
+
+void handle_piscsi_write(uint32_t addr, uint32_t val, uint8_t type) {
+ int32_t r;
+#ifndef PISCSI_DEBUG
+ if (type) {}
+#endif
+
+ struct piscsi_dev *d = &devs[piscsi_cur_drive];
+
+ uint16_t cmd = (addr & 0xFFFF);
+
+ switch (cmd) {
+ case PISCSI_CMD_READ64:
+ case PISCSI_CMD_READ:
+ d = &devs[val];
+ if (d->fd == -1) {
+ DEBUG("[!!!PISCSI] BUG: Attempted read from unmapped drive %d.\n", val);
+ break;
+ }
+
+ if (cmd == PISCSI_CMD_READ) {
+ DEBUG("[PISCSI-%d] %d byte READ from block %d to address %.8X\n", val, piscsi_u32[1], piscsi_u32[0], piscsi_u32[2]);
+ d->lba = piscsi_u32[0];
+ lseek(d->fd, (piscsi_u32[0] * 512), SEEK_SET);
+ }
+ else {
+ uint64_t src = piscsi_u32[3];
+ src = (src << 32) | piscsi_u32[0];
+ DEBUG("[PISCSI-%d] %d byte READ64 from block %lld to address %.8X\n", val, piscsi_u32[1], (src / 512), piscsi_u32[2]);
+ d->lba = (src / 512);
+ lseek64(d->fd, src, SEEK_SET);
+ }
+
+ r = get_mapped_item_by_address(cfg, piscsi_u32[2]);
+ if (r != -1 && cfg->map_type[r] == MAPTYPE_RAM) {
+ DEBUG_TRIVIAL("[PISCSI-%d] \"DMA\" Read goes to mapped range %d.\n", val, r);
+ read(d->fd, cfg->map_data[r] + piscsi_u32[2] - cfg->map_offset[r], piscsi_u32[1]);
+ }
+ else {
+ DEBUG_TRIVIAL("[PISCSI-%d] No mapped range found for read.\n", val);
+ uint8_t c = 0;
+ for (uint32_t i = 0; i < piscsi_u32[1]; i++) {
+ read(d->fd, &c, 1);
+ write8(piscsi_u32[2] + i, (uint32_t)c);
+ }
+ }
+ break;
+ case PISCSI_CMD_WRITE64:
+ case PISCSI_CMD_WRITE:
+ d = &devs[val];
+ if (d->fd == -1) {
+ DEBUG ("[PISCSI] BUG: Attempted write to unmapped drive %d.\n", val);
+ break;
+ }
+
+ if (cmd == PISCSI_CMD_WRITE) {
+ DEBUG("[PISCSI-%d] %d byte WRITE to block %d from address %.8X\n", val, piscsi_u32[1], piscsi_u32[0], piscsi_u32[2]);
+ d->lba = piscsi_u32[0];
+ lseek(d->fd, (piscsi_u32[0] * 512), SEEK_SET);
+ }
+ else {
+ uint64_t src = piscsi_u32[3];
+ src = (src << 32) | piscsi_u32[0];
+ DEBUG("[PISCSI-%d] %d byte WRITE64 to block %lld from address %.8X\n", val, piscsi_u32[1], (src / 512), piscsi_u32[2]);
+ d->lba = (src / 512);
+ lseek64(d->fd, src, SEEK_SET);
+ }
+
+ r = get_mapped_item_by_address(cfg, piscsi_u32[2]);
+ if (r != -1) {
+ DEBUG_TRIVIAL("[PISCSI-%d] \"DMA\" Write comes from mapped range %d.\n", val, r);
+ write(d->fd, cfg->map_data[r] + piscsi_u32[2] - cfg->map_offset[r], piscsi_u32[1]);
+ }
+ else {
+ DEBUG_TRIVIAL("[PISCSI-%d] No mapped range found for write.\n", val);
+ uint8_t c = 0;
+ for (uint32_t i = 0; i < piscsi_u32[1]; i++) {
+ c = read8(piscsi_u32[2] + i);
+ write(d->fd, &c, 1);
+ }
+ }
+ break;
+ case PISCSI_CMD_ADDR1: case PISCSI_CMD_ADDR2: case PISCSI_CMD_ADDR3: case PISCSI_CMD_ADDR4: {
+ int i = ((addr & 0xFFFF) - PISCSI_CMD_ADDR1) / 4;
+ piscsi_u32[i] = val;
+ break;
+ }
+ case PISCSI_CMD_DRVNUM:
+ //printf("%d ", val);
+ if (val % 10 != 0)
+ piscsi_cur_drive = 255;
+ else
+ piscsi_cur_drive = val / 10;
+ if (piscsi_cur_drive > NUM_UNITS)
+ piscsi_cur_drive = 255;
+
+ if (piscsi_cur_drive != 255) {
+ DEBUG("[PISCSI] (%s) Drive number set to %d (%d)\n", op_type_names[type], piscsi_cur_drive, val);
+ }
+ break;
+ case PISCSI_CMD_DEBUGME:
+ piscsi_debugme(val);
+ break;
+ case PISCSI_CMD_DRIVER: {
+ DEBUG("[PISCSI] Driver copy/patch called, destination address %.8X.\n", val);
+ int r = get_mapped_item_by_address(cfg, val);
+ if (r != -1) {
+ uint32_t addr = val - cfg->map_offset[r];
+ uint8_t *dst_data = cfg->map_data[r];
+ uint8_t cur_partition = 0;
+ memcpy(dst_data + addr, piscsi_rom_ptr + PISCSI_DRIVER_OFFSET, 0x4000 - PISCSI_DRIVER_OFFSET);
+
+ piscsi_hinfo.base_offset = val;
+
+ reloc_hunks(piscsi_hreloc, dst_data + addr, &piscsi_hinfo);
+
+ #define PUTNODELONG(val) *(uint32_t *)&dst_data[p_offs] = htobe32(val); p_offs += 4;
+ #define PUTNODELONGBE(val) *(uint32_t *)&dst_data[p_offs] = val; p_offs += 4;
+
+ for (int i = 0; i < 128; i++) {
+ rom_partitions[i] = 0;
+ rom_partition_prio[i] = 0;
+ rom_partition_dostype[i] = 0;
+ }
+ rom_cur_partition = 0;
+
+ uint32_t data_addr = addr + 0x3F00;
+ sprintf((char *)dst_data + data_addr, "pi-scsi.device");
+ uint32_t addr2 = addr + 0x4000;
+ for (int i = 0; i < NUM_UNITS; i++) {
+ if (devs[i].fd != -1)
+ piscsi_find_partitions(&devs[i]);
+ else
+ goto skip_disk;
+
+ if (devs[i].num_partitions) {
+ uint32_t p_offs = addr2;
+ DEBUG("[PISCSI] Adding %d partitions for unit %d\n", devs[i].num_partitions, i);
+ for (uint32_t j = 0; j < devs[i].num_partitions; j++) {
+ DEBUG("Partition %d: %s\n", j, devs[i].pb[j]->pb_DriveName + 1);
+ sprintf((char *)dst_data + p_offs, "%s", devs[i].pb[j]->pb_DriveName + 1);
+ p_offs += 0x20;
+ PUTNODELONG(addr2 + cfg->map_offset[r]);
+ PUTNODELONG(data_addr + cfg->map_offset[r]);
+ PUTNODELONG((i * 10));
+ PUTNODELONG(0);
+ uint32_t nodesize = (be32toh(devs[i].pb[j]->pb_Environment[0]) + 1) * 4;
+ memcpy(dst_data + p_offs, devs[i].pb[j]->pb_Environment, nodesize);
+
+ struct pihd_dosnode_data *dat = (struct pihd_dosnode_data *)(&dst_data[addr2+0x20]);
+
+ if (BE(devs[i].pb[j]->pb_Flags) & 0x01) {
+ DEBUG("Partition is bootable.\n");
+ rom_partition_prio[cur_partition] = 0;
+ dat->priority = 0;
+ }
+ else {
+ DEBUG("Partition is not bootable.\n");
+ rom_partition_prio[cur_partition] = -128;
+ dat->priority = htobe32(-128);
+ }
+
+ DEBUG("DOSNode Data:\n");
+ DEBUG("Name: %s Device: %s\n", dst_data + addr2, dst_data + data_addr);
+ DEBUG("Unit: %d Flags: %d Pad1: %d\n", BE(dat->unit), BE(dat->flags), BE(dat->pad1));
+ DEBUG("Node len: %d Block len: %d\n", BE(dat->node_len) * 4, BE(dat->block_len) * 4);
+ DEBUG("H: %d SPB: %d BPS: %d\n", BE(dat->surf), BE(dat->secs_per_block), BE(dat->blocks_per_track));
+ DEBUG("Reserved: %d Prealloc: %d\n", BE(dat->reserved_blocks), BE(dat->pad2));
+ DEBUG("Interleaved: %d Buffers: %d Memtype: %d\n", BE(dat->interleave), BE(dat->buffers), BE(dat->mem_type));
+ DEBUG("Lowcyl: %d Highcyl: %d Prio: %d\n", BE(dat->lowcyl), BE(dat->highcyl), BE(dat->priority));
+ DEBUG("Maxtransfer: %.8X Mask: %.8X\n", BE(dat->maxtransfer), BE(dat->transfer_mask));
+ DEBUG("DOSType: %.8X\n", BE(dat->dostype));
+
+ rom_partitions[cur_partition] = addr2 + 0x20 + cfg->map_offset[r];
+ rom_partition_dostype[cur_partition] = dat->dostype;
+ cur_partition++;
+ addr2 += 0x100;
+ p_offs = addr2;
+ }
+ }
+skip_disk:;
+ }
+ }
+
+ break;
+ }
+ case PISCSI_CMD_NEXTPART:
+ DEBUG("[PISCSI] Switch partition %d -> %d\n", rom_cur_partition, rom_cur_partition + 1);
+ rom_cur_partition++;
+ break;
+ case PISCSI_CMD_NEXTFS:
+ DEBUG("[PISCSI] Switch file file system %d -> %d\n", rom_cur_fs, rom_cur_fs + 1);
+ rom_cur_fs++;
+ break;
+ case PISCSI_CMD_COPYFS:
+ DEBUG("[PISCSI] Copy file system %d to %.8X and reloc.\n", rom_cur_fs, piscsi_u32[2]);
+ r = get_mapped_item_by_address(cfg, piscsi_u32[2]);
+ if (r != -1) {
+ uint32_t addr = piscsi_u32[2] - cfg->map_offset[r];
+ memset(cfg->map_data[r] + addr, 0x00, filesystems[rom_cur_fs].h_info.alloc_size);
+ memcpy(cfg->map_data[r] + addr, filesystems[rom_cur_fs].binary_data, filesystems[rom_cur_fs].h_info.byte_size);
+ filesystems[rom_cur_fs].h_info.base_offset = piscsi_u32[2];
+ reloc_hunks(filesystems[rom_cur_fs].relocs, cfg->map_data[r] + addr, &filesystems[rom_cur_fs].h_info);
+ filesystems[rom_cur_fs].handler = piscsi_u32[2];
+ }
+ break;
+ case PISCSI_CMD_SETFSH: {
+ int i = 0;
+ DEBUG("[PISCSI] Set handler for partition %d (DeviceNode: %.8X)\n", rom_cur_partition, val);
+ r = get_mapped_item_by_address(cfg, val);
+ if (r != -1) {
+ uint32_t addr = val - cfg->map_offset[r];
+ struct DeviceNode *node = (struct DeviceNode *)(cfg->map_data[r] + addr);
+#ifdef PISCSI_DEBUG
+ char *dosID = (char *)&rom_partition_dostype[rom_cur_partition];
+#endif
+ DEBUG("[PISCSI] Partition DOSType is %c%c%c/%d\n", dosID[0], dosID[1], dosID[2], dosID[3]);
+ for (i = 0; i < piscsi_num_fs; i++) {
+ if (rom_partition_dostype[rom_cur_partition] == filesystems[i].FS_ID) {
+ node->dn_SegList = htobe32((filesystems[i].handler >> 2));
+ node->dn_GlobalVec = 0xFFFFFFFF;
+ goto fs_found;
+ }
+ }
+ DEBUG("[!!!PISCSI] Found no handler for file system!\n");
+fs_found:;
+ DEBUG("[FS-HANDLER] Next: %d Type: %.8X\n", BE(node->dn_Next), BE(node->dn_Type));
+ DEBUG("[FS-HANDLER] Task: %d Lock: %d\n", BE(node->dn_Task), BE(node->dn_Lock));
+ DEBUG("[FS-HANDLER] Handler: %d Stacksize: %d\n", BE((uint32_t)node->dn_Handler), BE(node->dn_StackSize));
+ DEBUG("[FS-HANDLER] Priority: %d Startup: %d\n", BE((uint32_t)node->dn_Priority), BE(node->dn_Startup));
+ DEBUG("[FS-HANDLER] SegList: %.8X GlobalVec: %d\n", BE((uint32_t)node->dn_SegList), BE(node->dn_GlobalVec));
+ DEBUG("[PISCSI] Handler for partition %.8X set to %.8X (%.8X).\n", BE((uint32_t)node->dn_Name), filesystems[i].FS_ID, filesystems[i].handler);
+ }
+ break;
+ }
+ case PISCSI_DBG_VAL1: case PISCSI_DBG_VAL2: case PISCSI_DBG_VAL3: case PISCSI_DBG_VAL4:
+ case PISCSI_DBG_VAL5: case PISCSI_DBG_VAL6: case PISCSI_DBG_VAL7: case PISCSI_DBG_VAL8: {
+ int i = ((addr & 0xFFFF) - PISCSI_DBG_VAL1) / 4;
+ piscsi_dbg[i] = val;
+ break;
+ }
+ case PISCSI_DBG_MSG:
+ print_piscsi_debug_message(val);
+ break;
+ default:
+ DEBUG("[!!!PISCSI] WARN: Unhandled %s register write to %.8X: %d\n", op_type_names[type], addr, val);
+ break;
+ }
+}
+
+#define PIB 0x00
+
+uint32_t handle_piscsi_read(uint32_t addr, uint8_t type) {
+ if (type) {}
+
+ if ((addr & 0xFFFF) >= PISCSI_CMD_ROM) {
+ uint32_t romoffs = (addr & 0xFFFF) - PISCSI_CMD_ROM;
+ if (romoffs < (piscsi_rom_size + PIB)) {
+ //DEBUG("[PISCSI] %s read from Boot ROM @$%.4X (%.8X): ", op_type_names[type], romoffs, addr);
+ uint32_t v = 0;
+ switch (type) {
+ case OP_TYPE_BYTE:
+ v = piscsi_rom_ptr[romoffs - PIB];
+ //DEBUG("%.2X\n", v);
+ break;
+ case OP_TYPE_WORD:
+ v = be16toh(*((uint16_t *)&piscsi_rom_ptr[romoffs - PIB]));
+ //DEBUG("%.4X\n", v);
+ break;
+ case OP_TYPE_LONGWORD:
+ v = be32toh(*((uint32_t *)&piscsi_rom_ptr[romoffs - PIB]));
+ //DEBUG("%.8X\n", v);
+ break;
+ }
+ return v;
+ }
+ return 0;
+ }
+
+ switch (addr & 0xFFFF) {
+ case PISCSI_CMD_ADDR1: case PISCSI_CMD_ADDR2: case PISCSI_CMD_ADDR3: case PISCSI_CMD_ADDR4: {
+ int i = ((addr & 0xFFFF) - PISCSI_CMD_ADDR1) / 4;
+ return piscsi_u32[i];
+ break;
+ }
+ case PISCSI_CMD_DRVTYPE:
+ if (devs[piscsi_cur_drive].fd == -1) {
+ DEBUG("[PISCSI] %s Read from DRVTYPE %d, drive not attached.\n", op_type_names[type], piscsi_cur_drive);
+ return 0;
+ }
+ DEBUG("[PISCSI] %s Read from DRVTYPE %d, drive attached.\n", op_type_names[type], piscsi_cur_drive);
+ return 1;
+ break;
+ case PISCSI_CMD_DRVNUM:
+ return piscsi_cur_drive;
+ break;
+ case PISCSI_CMD_CYLS:
+ DEBUG("[PISCSI] %s Read from CYLS %d: %d\n", op_type_names[type], piscsi_cur_drive, devs[piscsi_cur_drive].c);
+ return devs[piscsi_cur_drive].c;
+ break;
+ case PISCSI_CMD_HEADS:
+ DEBUG("[PISCSI] %s Read from HEADS %d: %d\n", op_type_names[type], piscsi_cur_drive, devs[piscsi_cur_drive].h);
+ return devs[piscsi_cur_drive].h;
+ break;
+ case PISCSI_CMD_SECS:
+ DEBUG("[PISCSI] %s Read from SECS %d: %d\n", op_type_names[type], piscsi_cur_drive, devs[piscsi_cur_drive].s);
+ return devs[piscsi_cur_drive].s;
+ break;
+ case PISCSI_CMD_BLOCKS: {
+ uint32_t blox = devs[piscsi_cur_drive].fs / 512;
+ DEBUG("[PISCSI] %s Read from BLOCKS %d: %d\n", op_type_names[type], piscsi_cur_drive, (uint32_t)(devs[piscsi_cur_drive].fs / 512));
+ DEBUG("fs: %lld (%d)\n", devs[piscsi_cur_drive].fs, blox);
+ return blox;
+ break;
+ }
+ case PISCSI_CMD_GETPART: {
+ DEBUG("[PISCSI] Get ROM partition %d offset: %.8X\n", rom_cur_partition, rom_partitions[rom_cur_partition]);
+ return rom_partitions[rom_cur_partition];
+ break;
+ }
+ case PISCSI_CMD_GETPRIO:
+ DEBUG("[PISCSI] Get partition %d boot priority: %d\n", rom_cur_partition, rom_partition_prio[rom_cur_partition]);
+ return rom_partition_prio[rom_cur_partition];
+ break;
+ case PISCSI_CMD_CHECKFS:
+ DEBUG("[PISCSI] Get current loaded file system: %.8X\n", filesystems[rom_cur_fs].FS_ID);
+ return filesystems[rom_cur_fs].FS_ID;
+ case PISCSI_CMD_FSSIZE:
+ DEBUG("[PISCSI] Get alloc size of loaded file system: %d\n", filesystems[rom_cur_fs].h_info.alloc_size);
+ return filesystems[rom_cur_fs].h_info.alloc_size;
+ default:
+ DEBUG("[!!!PISCSI] WARN: Unhandled %s register read from %.8X\n", op_type_names[type], addr);
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+#include <stdint.h>
+
+#include "platforms/amiga/hunk-reloc.h"
+
+#define TDF_EXTCOM (1<<15)
+
+#define CMD_INVALID 0
+#define CMD_RESET 1
+#define CMD_READ 2
+#define CMD_WRITE 3
+#define CMD_UPDATE 4
+#define CMD_CLEAR 5
+#define CMD_STOP 6
+#define CMD_START 7
+#define CMD_FLUSH 8
+#define CMD_NONSTD 9
+
+#define TD_MOTOR (CMD_NONSTD+0) // 9
+#define TD_SEEK (CMD_NONSTD+1) // 10
+#define TD_FORMAT (CMD_NONSTD+2) // 11
+#define TD_REMOVE (CMD_NONSTD+3) // 12
+#define TD_CHANGENUM (CMD_NONSTD+4) // 13
+#define TD_CHANGESTATE (CMD_NONSTD+5) // 15
+#define TD_PROTSTATUS (CMD_NONSTD+6) // 16
+#define TD_RAWREAD (CMD_NONSTD+7) // 17
+#define TD_RAWWRITE (CMD_NONSTD+8) // 18
+#define TD_GETDRIVETYPE (CMD_NONSTD+9) // 19
+#define TD_GETNUMTRACKS (CMD_NONSTD+10) // 20
+#define TD_ADDCHANGEINT (CMD_NONSTD+11) // 21
+#define TD_REMCHANGEINT (CMD_NONSTD+12) // 22
+#define TD_GETGEOMETRY (CMD_NONSTD+13) // 23
+#define TD_EJECT (CMD_NONSTD+14) // 24
+#define TD_LASTCOMM (CMD_NONSTD+15) // 25
+
+#define ETD_WRITE (CMD_WRITE|TDF_EXTCOM)
+#define ETD_READ (CMD_READ|TDF_EXTCOM)
+#define ETD_MOTOR (TD_MOTOR|TDF_EXTCOM)
+#define ETD_SEEK (TD_SEEK|TDF_EXTCOM)
+#define ETD_FORMAT (TD_FORMAT|TDF_EXTCOM)
+#define ETD_UPDATE (CMD_UPDATE|TDF_EXTCOM)
+#define ETD_CLEAR (CMD_CLEAR|TDF_EXTCOM)
+#define ETD_RAWREAD (TD_RAWREAD|TDF_EXTCOM)
+#define ETD_RAWWRITE (TD_RAWWRITE|TDF_EXTCOM)
+
+#define HD_SCSICMD 28
+
+#define NSCMD_DEVICEQUERY 0x4000
+#define NSCMD_TD_READ64 0xC000
+#define NSCMD_TD_WRITE64 0xC001
+#define NSCMD_TD_SEEK64 0xC002
+#define NSCMD_TD_FORMAT64 0xC003
+
+#define RDB_BLOCK_LIMIT 16
+
+// RDSK
+#define RDB_IDENTIFIER 0x5244534B
+// PART
+#define PART_IDENTIFIER 0x50415254
+// FSHD
+#define FS_IDENTIFIER 0x46534844
+
+#define PISCSI_DRIVER_OFFSET 0x1000
+#define NUM_FILESYSTEMS 32
+
+struct piscsi_dev {
+ uint32_t c;
+ uint16_t h, s;
+ uint64_t fs;
+ int32_t fd;
+ uint32_t lba;
+ uint32_t num_partitions;
+ uint32_t fshd_offs;
+ // Will parse max eight partitions per disk
+ struct PartitionBlock *pb[16];
+ struct RigidDiskBlock *rdb;
+};
+
+struct piscsi_fs {
+ struct FileSysHeaderBlock * fhb;
+ uint32_t FS_ID;
+ uint32_t handler;
+ struct hunk_reloc relocs[512];
+ struct hunk_info h_info;
+ uint8_t *binary_data;
+};
+
+// .long 0 /* dos disk name */
+// .long 0 /* device file name */
+// .long 0 /* unit */
+// .long 0 /* flags */
+struct DosEnvec {
+ uint32_t de_TableSize; /* Size of Environment vector */
+ uint32_t de_SizeBlock; /* in longwords: standard value is 128 */
+ uint32_t de_SecOrg; /* not used; must be 0 */
+ uint32_t de_Surfaces; /* # of heads (surfaces). drive specific */
+ uint32_t de_SectorPerBlock; /* not used; must be 1 */
+ uint32_t de_BlocksPerTrack; /* blocks per track. drive specific */
+ uint32_t de_Reserved; /* DOS reserved blocks at start of partition. */
+ uint32_t de_PreAlloc; /* DOS reserved blocks at end of partition */
+ uint32_t de_Interleave; /* usually 0 */
+ uint32_t de_LowCyl; /* starting cylinder. typically 0 */
+ uint32_t de_HighCyl; /* max cylinder. drive specific */
+ uint32_t de_NumBuffers; /* Initial # DOS of buffers. */
+ uint32_t de_BufMemType; /* type of mem to allocate for buffers */
+ uint32_t de_MaxTransfer; /* Max number of bytes to transfer at a time */
+ uint32_t de_Mask; /* Address Mask to block out certain memory */
+ int32_t de_BootPri; /* Boot priority for autoboot */
+ uint32_t de_DosType; /* ASCII (HEX) string showing filesystem type;
+ * 0X444F5300 is old filesystem,
+ * 0X444F5301 is fast file system */
+ uint32_t de_Baud; /* Baud rate for serial handler */
+ uint32_t de_Control; /* Control word for handler/filesystem */
+ uint32_t de_BootBlocks; /* Number of blocks containing boot code */
+
+};
+
+struct pihd_dosnode_data {
+ uint32_t name_ptr;
+ uint32_t dev_name_ptr;
+ uint32_t unit;
+ uint32_t flags;
+ uint32_t node_len;
+ uint32_t block_len;
+ uint32_t pad1;
+ uint32_t surf;
+ uint32_t secs_per_block;
+ uint32_t blocks_per_track;
+ uint32_t reserved_blocks;
+ uint32_t pad2;
+ uint32_t interleave;
+ uint32_t lowcyl;
+ uint32_t highcyl;
+ uint32_t buffers;
+ uint32_t mem_type;
+ uint32_t maxtransfer;
+ uint32_t transfer_mask;
+ uint32_t priority;
+ uint32_t dostype;
+};
+
+struct RigidDiskBlock {
+ uint32_t rdb_ID;
+ uint32_t rdb_SummedLongs;
+ int32_t rdb_ChkSum;
+ uint32_t rdb_HostID;
+ uint32_t rdb_BlockBytes;
+ uint32_t rdb_Flags;
+ /* block list heads */
+ uint32_t rdb_BadBlockList;
+ uint32_t rdb_PartitionList;
+ uint32_t rdb_FileSysHeaderList;
+ uint32_t rdb_DriveInit;
+ uint32_t rdb_Reserved1[6];
+ /* physical drive characteristics */
+ uint32_t rdb_Cylinders;
+ uint32_t rdb_Sectors;
+ uint32_t rdb_Heads;
+ uint32_t rdb_Interleave;
+ uint32_t rdb_Park;
+ uint32_t rdb_Reserved2[3];
+ uint32_t rdb_WritePreComp;
+ uint32_t rdb_ReducedWrite;
+ uint32_t rdb_StepRate;
+ uint32_t rdb_Reserved3[5];
+ /* logical drive characteristics */
+ uint32_t rdb_RDBBlocksLo;
+ uint32_t rdb_RDBBlocksHi;
+ uint32_t rdb_LoCylinder;
+ uint32_t rdb_HiCylinder;
+ uint32_t rdb_CylBlocks;
+ uint32_t rdb_AutoParkSeconds;
+ uint32_t rdb_HighRDSKBlock;
+ uint32_t rdb_Reserved4;
+ /* drive identification */
+ char rdb_DiskVendor[8];
+ char rdb_DiskProduct[16];
+ char rdb_DiskRevision[4];
+ char rdb_ControllerVendor[8];
+ char rdb_ControllerProduct[16];
+ char rdb_ControllerRevision[4];
+ char rdb_DriveInitName[40];
+};
+
+struct DeviceNode {
+ uint32_t dn_Next;
+ uint32_t dn_Type;
+ uint32_t dn_Task;
+ uint32_t dn_Lock;
+ uint8_t *dn_Handler;
+ uint32_t dn_StackSize;
+ int32_t dn_Priority;
+ uint32_t dn_Startup;
+ uint32_t dn_SegList;
+ uint32_t dn_GlobalVec;
+ uint8_t *dn_Name;
+};
+
+struct PartitionBlock {
+ uint32_t pb_ID;
+ uint32_t pb_SummedLongs;
+ int32_t pb_ChkSum;
+ uint32_t pb_HostID;
+ uint32_t pb_Next;
+ uint32_t pb_Flags;
+ uint32_t pb_Reserved1[2];
+ uint32_t pb_DevFlags;
+ uint8_t pb_DriveName[32];
+ uint32_t pb_Reserved2[15];
+ uint32_t pb_Environment[20];
+ uint32_t pb_EReserved[12];
+};
+
+struct SCSICmd_ModeSense6 {
+ uint8_t opcode;
+ uint8_t reserved_dbd;
+ uint8_t pc_pagecode;
+ uint8_t subpage_code;
+ uint8_t alloc_len;
+ uint8_t control;
+};
+
+struct SCSICmd_RW10 {
+ uint8_t opcode;
+ uint8_t rdprotect_flags;
+ uint32_t block;
+ uint8_t res_groupnum;
+ uint16_t len;
+ uint8_t control;
+};
+
+struct FileSysHeaderBlock {
+ uint32_t fhb_ID;
+ uint32_t fhb_SummedLongs;
+ int32_t fhb_ChkSum;
+ uint32_t fhb_HostID;
+ uint32_t fhb_Next;
+ uint32_t fhb_Flags;
+ uint32_t fhb_Reserved1[2];
+ uint32_t fhb_DosType;
+ uint32_t fhb_Version;
+ uint32_t fhb_PatchFlags;
+ uint32_t fhb_Type;
+ uint32_t fhb_Task;
+ uint32_t fhb_Lock;
+ uint32_t fhb_Handler;
+ uint32_t fhb_StackSize;
+ int32_t fhb_Priority;
+ int32_t fhb_Startup;
+ int32_t fhb_SegListBlocks;
+ int32_t fhb_GlobalVec;
+ uint32_t fhb_Reserved2[23];
+ uint8_t fhb_FileSysName[84];
+};
+
+void piscsi_init();
+void piscsi_map_drive(char *filename, uint8_t index);
+
+void handle_piscsi_write(uint32_t addr, uint32_t val, uint8_t type);
+uint32_t handle_piscsi_read(uint32_t addr, uint8_t type);
+
+void piscsi_find_filesystems(struct piscsi_dev *d);
+void piscsi_refresh_drives();
--- /dev/null
+# PiSCSI Interface/Device driver for Amiga
+
+A high performance replacement for scsi.device, allowing automatic booting and mounting of raw hard disk (RDB/RDSK) images.
+
+This driver and interface is work in progress, do not use it in conjunction with any critical data that you need to survive.
+
+# Instructions
+
+To use the PiSCSI interface, simply enable it by uncommenting the `setvar piscsi` line in default.cfg, or add it to the config file you're currently using.
+
+Add disk images to the PiSCSI interface by uncommenting the `piscsi0` and `piscsi1` lines and editing them to point at the disk image(s) you want to use.
+
+Physical drives can also be mounted using their mount point files on Linux, such as `/dev/sda` for a USB stick, but keep in mind that this is dangerous as it can destroy the contents of the disk.
+
+You can mount up to 7 disk images using setvar `piscsi0` through `piscsi6`.
+
+If you want EVEN MORE speed, either adjust the size of your hard drive image so that it gets properly detected with 16 heads in HDToolBox or manually edit the Cylinders/Heads settings when setting up your drive.
+
+(The trackdisk device on the Amiga seems to enable transfers bigger than 512 bytes (one sector) only if the drive is identified as having more than one drive head/surface.)
+
+# Making changes to the driver
+
+If you make changes to the driver, you can always test these on the Amiga as a regular file in `DEVS:`, but the Z2 device has to be disabled for this to work properly.
+
+Steps to create an updated boot ROM, all of these are done in the `device_driver_amiga` directory:
+
+* (Optional) If you've made changes to bootrom.s, first run `./build.sh`.
+* (Optional) If you've had build.sh create a new `bootrom` file, you need to chop off the first few bytes of it, since VASM adds a single hunk to the beginning of it. Simply delete all bytes up until you bump into the value `0x90`, this is the first value in the boot ROM identifier.
+* Compile the new `pi-scsi.device` using `./build2.sh`.
+* (Optional) If you haven't previously compiled the `makerom` binary, or the code for it has been updated since last time, simply run `gcc makerom.c -o makerom`
+* Run `./makerom` to assemble the boot ROM file, it's automatically in the correct place for the emulator to find it.
+
+# If you for instance want to mount a FAT32 disk with fat95, these old instructions may be of some use:
+
+* Download giggledisk from http://www.geit.de/eng_giggledisk.html or https://aminet.net/package/disk/misc/giggledisk to make MountLists for attached devices.
+ Place the giggledisk binary in `C:` or something so that it's available in the search path.
+* It might be a good idea to have fat95 installed on your Amiga, in case you want to use FAT32 images or other file systems that fat95 can handle: https://aminet.net/package/disk/misc/fat95
+
+Now open a new CLI, and type something like:
+`giggledisk device=pi-scsi.device unit=0 to=RAM:PI0`
+
+This will create a MountList file called `PI0` on the RAM disk, which contains almost all the information needed to mount the drive and its partitions in Workbench.
+
+You'll have to start up your favorite (or least hated) text editor and change the contents of the file a bit.
+
+Above the `FileSystem` line, you'll notice a drive identifier. This line might say something along the lines of `DH0` or `PDH0`, etc, and it must be removed, otherwise the file can't be parsed.
+
+The `FileSystem` line will usually be empty, so you have to fill this out yourself. For instance, you can set it to something like `L:FastFileSystem` to use the standard file system for the drive, or `L:fat95` in case the image is in a format that fat95 can handle.
+
+Thus, an edited line would look something like `FileSystem = L:FastFileSystem`
+
+If the MountList has several partitions listed in it, it must be split up into separate files for all partitions to be mounted.
+
+Once you've edited a MountList file, simply copy/move it to `SYS:Devs/DOSDrivers`, and the drive will be mounted automatically the next time you boot into Workbench.
+
+If you don't want it to be mounted automatically, simply use the `Mount` command from CLI.
+
+# A big word of caution
+
+While the PiSCSI interface can be used to mount physical drives that are available as block device nodes on the Pi, you should not do this unless you are absolutely sure what you're doing.
+
+Directly mounting a block device connected to the Pi may corrupt or destroy the data on the device, depending on what you or the file system drivers do with this disk on the Amiga side.
+
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include "config_file/config_file.h"
+#ifndef FAKESTORM
+#include "gpio/ps_protocol.h"
+#endif
+#include "rtg.h"
+
+extern uint32_t rtg_address[8];
+extern uint32_t rtg_address_adj[8];
+extern uint8_t *rtg_mem; // FIXME
+extern uint16_t rtg_display_format;
+extern uint16_t rtg_user[8];
+extern uint16_t rtg_x[8], rtg_y[8];
+
+extern uint8_t realtime_graphics_debug;
+
+void rtg_fillrect_solid(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t color, uint16_t pitch, uint16_t format) {
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (x << format) + (y * pitch)];
+ switch(format) {
+ case RTGFMT_8BIT: {
+ for (int xs = 0; xs < w; xs++) {
+ dptr[xs] = color & 0xFF;
+ }
+ break;
+ }
+ case RTGFMT_RBG565: {
+ color = htobe16((color & 0xFFFF));
+ uint16_t *ptr = (uint16_t *)dptr;
+ for (int xs = 0; xs < w; xs++) {
+ ptr[xs] = color;
+ }
+ break;
+ }
+ case RTGFMT_RGB32: {
+ color = htobe32(color);
+ uint32_t *ptr = (uint32_t *)dptr;
+ for (int xs = 0; xs < w; xs++) {
+ ptr[xs] = color;
+ }
+ break;
+ }
+ }
+ for (int ys = 1; ys < h; ys++) {
+ dptr += pitch;
+ memcpy(dptr, (void *)(size_t)(dptr - pitch), (w << format));
+ }
+}
+
+void rtg_fillrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t color, uint16_t pitch, uint16_t format, uint8_t mask) {
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (x << format) + (y * pitch)];
+
+ for (int ys = 0; ys < h; ys++) {
+ for (int xs = 0; xs < w; xs++) {
+ SET_RTG_PIXEL_MASK(&dptr[xs], (color & 0xFF), format);
+ }
+ dptr += pitch;
+ }
+}
+
+void rtg_invertrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format, uint8_t mask) {
+ if (mask) {}
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (x << format) + (y * pitch)];
+ for (int ys = 0; ys < h; ys++) {
+ switch(format) {
+ case RTGFMT_8BIT: {
+ for (int xs = 0; xs < w; xs++) {
+ dptr[xs] ^= mask;
+ }
+ break;
+ }
+ case RTGFMT_RBG565: {
+ for (int xs = 0; xs < w; xs++) {
+ ((uint16_t *)dptr)[xs] = ~((uint16_t *)dptr)[xs];
+ }
+ break;
+ }
+ case RTGFMT_RGB32: {
+ for (int xs = 0; xs < w; xs++) {
+ ((uint32_t *)dptr)[xs] = ~((uint32_t *)dptr)[xs];
+ }
+ break;
+ }
+ }
+ dptr += pitch;
+ }
+}
+
+void rtg_blitrect(uint16_t x, uint16_t y, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format, uint8_t mask) {
+ if (mask) {}
+ uint8_t *sptr = &rtg_mem[rtg_address_adj[0] + (x << format) + (y * pitch)];
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (dx << format) + (dy * pitch)];
+
+ uint32_t xdir = 1, pitchstep = pitch;
+
+ if (y < dy) {
+ pitchstep = -pitch;
+ sptr += ((h - 1) * pitch);
+ dptr += ((h - 1) * pitch);
+ }
+ if (x < dx) {
+ xdir = 0;
+ }
+
+ for (int ys = 0; ys < h; ys++) {
+ if (xdir) {
+ for (int xs = 0; xs < w; xs++) {
+ SET_RTG_PIXEL_MASK(&dptr[xs], sptr[xs], format);
+ }
+ }
+ else {
+ for (int xs = w - 1; xs >= x; xs--) {
+ SET_RTG_PIXEL_MASK(&dptr[xs], sptr[xs], format);
+ }
+ }
+ sptr += pitchstep;
+ dptr += pitchstep;
+ }
+}
+
+void rtg_blitrect_solid(uint16_t x, uint16_t y, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format) {
+ uint8_t *sptr = &rtg_mem[rtg_address_adj[0] + (x << format) + (y * pitch)];
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (dx << format) + (dy * pitch)];
+
+ uint32_t xdir = 1, pitchstep = pitch;
+
+ if (y < dy) {
+ pitchstep = -pitch;
+ sptr += ((h - 1) * pitch);
+ dptr += ((h - 1) * pitch);
+ }
+ if (x < dx) {
+ xdir = 0;
+ }
+
+ for (int ys = 0; ys < h; ys++) {
+ if (xdir)
+ memcpy(dptr, sptr, w << format);
+ else
+ memmove(dptr, sptr, w << format);
+ sptr += pitchstep;
+ dptr += pitchstep;
+ }
+}
+
+void rtg_blitrect_nomask_complete(uint16_t sx, uint16_t sy, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t srcpitch, uint16_t dstpitch, uint32_t src_addr, uint32_t dst_addr, uint16_t format, uint8_t minterm) {
+ if (minterm) {}
+ uint8_t *sptr = &rtg_mem[src_addr - (PIGFX_RTG_BASE + PIGFX_REG_SIZE) + (sx << format) + (sy * srcpitch)];
+ uint8_t *dptr = &rtg_mem[dst_addr - (PIGFX_RTG_BASE + PIGFX_REG_SIZE) + (dx << format) + (dy * dstpitch)];
+
+ uint32_t xdir = 1, src_pitchstep = srcpitch, dst_pitchstep = dstpitch;
+ uint8_t draw_mode = minterm;
+ uint32_t mask = 0xFF;
+
+ if (src_addr == dst_addr) {
+ if (sy < dy) {
+ src_pitchstep = -srcpitch;
+ sptr += ((h - 1) * srcpitch);
+ dst_pitchstep = -dstpitch;
+ dptr += ((h - 1) * dstpitch);
+ }
+ if (sx < dx) {
+ xdir = 0;
+ }
+ }
+
+ if (format == RTGFMT_RBG565)
+ mask = 0xFFFF;
+ if (format == RTGFMT_RGB32)
+ mask = 0xFFFFFFFF;
+
+ if (minterm == MINTERM_SRC) {
+ for (int ys = 0; ys < h; ys++) {
+ if (xdir)
+ memcpy(dptr, sptr, w << format);
+ else
+ memmove(dptr, sptr, w << format);
+ sptr += src_pitchstep;
+ dptr += dst_pitchstep;
+ }
+ }
+ else {
+ for (int ys = 0; ys < h; ys++) {
+ if (xdir) {
+ for (int xs = 0; xs < w; xs++) {
+ switch (format) {
+ case RTGFMT_8BIT:
+ HANDLE_MINTERM_PIXEL(sptr[xs], dptr[xs], format);
+ break;
+ case RTGFMT_RBG565:
+ HANDLE_MINTERM_PIXEL(((uint16_t *)sptr)[xs], ((uint16_t *)dptr)[xs], format);
+ break;
+ case RTGFMT_RGB32:
+ HANDLE_MINTERM_PIXEL(((uint32_t *)sptr)[xs], ((uint32_t *)dptr)[xs], format);
+ break;
+ }
+ }
+ }
+ else {
+ for (int xs = w - 1; xs >= sx; xs--) {
+ switch (format) {
+ case RTGFMT_8BIT:
+ HANDLE_MINTERM_PIXEL(sptr[xs], dptr[xs], format);
+ break;
+ case RTGFMT_RBG565:
+ HANDLE_MINTERM_PIXEL(((uint16_t *)sptr)[xs], ((uint16_t *)dptr)[xs], format);
+ break;
+ case RTGFMT_RGB32:
+ HANDLE_MINTERM_PIXEL(((uint32_t *)sptr)[xs], ((uint32_t *)dptr)[xs], format);
+ break;
+ }
+ }
+ }
+ sptr += src_pitchstep;
+ dptr += src_pitchstep;
+ }
+ }
+}
+
+extern struct emulator_config *cfg;
+
+void rtg_blittemplate(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t src_addr, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t t_pitch, uint16_t format, uint16_t offset_x, uint8_t mask, uint8_t draw_mode) {
+ if (mask) {}
+
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[1] + (x << format) + (y * pitch)];
+ uint8_t *sptr = NULL;
+ uint8_t cur_bit = 0, base_bit = 0, cur_byte = 0;
+ uint8_t invert = (draw_mode & DRAWMODE_INVERSVID);
+ uint16_t tmpl_x = 0;
+
+ draw_mode &= 0x03;
+
+ tmpl_x = offset_x / 8;
+ cur_bit = base_bit = (0x80 >> (offset_x % 8));
+
+ if (realtime_graphics_debug) {
+ printf("DEBUG: BlitTemplate - %d, %d (%dx%d)\n", x, y, w, h);
+ printf("Src: %.8X (%.8X)\n", src_addr, rtg_address_adj[0]);
+ printf("Dest: %.8X (%.8X)\n", rtg_address[1], rtg_address_adj[1]);
+ printf("pitch: %d t_pitch: %d format: %d\n", pitch, t_pitch, format);
+ printf("offset_x: %d mask: %.2X draw_mode: %d\n", offset_x, mask, draw_mode);
+ }
+
+ uint32_t fg_color[3] = {
+ (fgcol & 0xFF),
+ htobe16((fgcol & 0xFFFF)),
+ htobe32(fgcol),
+ };
+ uint32_t bg_color[3] = {
+ (bgcol & 0xFF),
+ htobe16((bgcol & 0xFFFF)),
+ htobe32(bgcol),
+ };
+
+ if (src_addr >= (PIGFX_RTG_BASE + PIGFX_REG_SIZE)) {
+ sptr = &rtg_mem[src_addr - (PIGFX_RTG_BASE + PIGFX_REG_SIZE)];
+ if (realtime_graphics_debug) {
+ printf("Origin: %.8X\n", rtg_address[2]);
+ printf("Grabbing data from RTG memory.\nData:\n");
+ for (int i = 0; i < h; i++) {
+ for (int j = 0; j < t_pitch; j++) {
+ printf("%.2X", sptr[j + (i * t_pitch)]);
+ }
+ printf("\n");
+ }
+#ifndef FAKESTORM
+ printf("Data available at origin:\n");
+ for (int i = 0; i < h; i++) {
+ for (int j = 0; j < w; j++) {
+ printf("%.2X", read8(rtg_address[2] + j + (i * t_pitch)));
+ }
+ printf("\n");
+ }
+#endif
+ }
+ }
+ else {
+ int i = get_mapped_item_by_address(cfg, src_addr);
+ if (i != -1) {
+ sptr = &cfg->map_data[i][src_addr - cfg->map_offset[i]];
+ if (realtime_graphics_debug) {
+ printf("Grabbing data from maping %d - offset %.8X\nData:\n", i, src_addr - cfg->map_offset[i]);
+ for (int i = 0; i < h; i++) {
+ for (int j = 0; j < t_pitch; j++) {
+ printf("%.2X", sptr[j + (i * t_pitch)]);
+ }
+ printf("\n");
+ }
+ }
+ }
+ else {
+ printf("BlitTemplate: Failed to find mapped range for address %.8X\n", src_addr);
+ return;
+ }
+ }
+
+ switch (draw_mode) {
+ case DRAWMODE_JAM1:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXELS(&dptr[xs << format], fg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXELS_MASK(&dptr[xs], fg_color[format], format);
+ }
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (cur_byte & cur_bit) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXEL(&dptr[xs << format], fg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXEL_MASK(&dptr[xs], fg_color[format], format);
+ }
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ TEMPLATE_LOOPX;
+ }
+ TEMPLATE_LOOPY;
+ }
+ return;
+ case DRAWMODE_JAM2:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXELS2_COND(&dptr[xs << format], fg_color[format], bg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXELS2_COND_MASK(&dptr[xs << format], fg_color[format], bg_color[format], format);
+ }
+
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXEL(&dptr[xs << format], (cur_byte & cur_bit) ? fg_color[format] : bg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXEL_MASK(&dptr[xs << format], (cur_byte & cur_bit) ? fg_color[format] : bg_color[format], format);
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ TEMPLATE_LOOPX;
+ }
+ TEMPLATE_LOOPY;
+ }
+ return;
+ case DRAWMODE_COMPLEMENT:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ INVERT_RTG_PIXELS(&dptr[xs << format], format)
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (cur_byte & cur_bit) {
+ INVERT_RTG_PIXEL(&dptr[xs << format], format)
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ TEMPLATE_LOOPX;
+ }
+ TEMPLATE_LOOPY;
+ }
+ return;
+ }
+}
+
+void rtg_blitpattern(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t src_addr, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t format, uint16_t offset_x, uint16_t offset_y, uint8_t mask, uint8_t draw_mode, uint8_t loop_rows) {
+ if (mask) {}
+
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[1] + (x << format) + (y * pitch)];
+ uint8_t *sptr = NULL, *sptr_base = NULL;
+ uint8_t cur_bit = 0, base_bit = 0, cur_byte = 0;
+ uint8_t invert = (draw_mode & DRAWMODE_INVERSVID);
+ uint16_t tmpl_x = 0;
+
+ draw_mode &= 0x03;
+
+ tmpl_x = (offset_x / 8) % 2;
+ cur_bit = base_bit = (0x80 >> (offset_x % 8));
+
+ uint32_t fg_color[3] = {
+ (fgcol & 0xFF),
+ htobe16((fgcol & 0xFFFF)),
+ htobe32(fgcol),
+ };
+ uint32_t bg_color[3] = {
+ (bgcol & 0xFF),
+ htobe16((bgcol & 0xFFFF)),
+ htobe32(bgcol),
+ };
+
+
+ if (src_addr >= (PIGFX_RTG_BASE + PIGFX_REG_SIZE))
+ sptr = &rtg_mem[src_addr - (PIGFX_RTG_BASE + PIGFX_REG_SIZE)];
+ else {
+ int i = get_mapped_item_by_address(cfg, src_addr);
+ if (i != -1) {
+ sptr = &cfg->map_data[i][src_addr - cfg->map_offset[i]];
+ }
+ else {
+ printf("BlitPattern: Failed to find mapped range for address %.8X\n", src_addr);
+ return;
+ }
+ }
+
+ sptr_base = sptr;
+ sptr += (offset_y % loop_rows) * 2;
+
+ switch (draw_mode) {
+ case DRAWMODE_JAM1:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXELS(&dptr[xs << format], fg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXELS_MASK(&dptr[xs], fg_color[format], format);
+ }
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (cur_byte & cur_bit) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXEL(&dptr[xs << format], fg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXEL_MASK(&dptr[xs], fg_color[format], format);
+ }
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ PATTERN_LOOPX;
+ }
+ PATTERN_LOOPY;
+ }
+ return;
+ case DRAWMODE_JAM2:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXELS2_COND(&dptr[xs << format], fg_color[format], bg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXELS2_COND_MASK(&dptr[xs << format], fg_color[format], bg_color[format], format);
+ }
+
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (mask == 0xFF || format != RTGFMT_8BIT) {
+ SET_RTG_PIXEL(&dptr[xs << format], (cur_byte & cur_bit) ? fg_color[format] : bg_color[format], format);
+ }
+ else {
+ SET_RTG_PIXEL_MASK(&dptr[xs << format], (cur_byte & cur_bit) ? fg_color[format] : bg_color[format], format);
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ PATTERN_LOOPX;
+ }
+ PATTERN_LOOPY;
+ }
+ return;
+ case DRAWMODE_COMPLEMENT:
+ for (uint16_t ys = 0; ys < h; ys++) {
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x];
+
+ for (int xs = 0; xs < w; xs++) {
+ if (w >= 8 && cur_bit == 0x80 && xs < w - 8) {
+ INVERT_RTG_PIXELS(&dptr[xs << format], format)
+ xs += 7;
+ }
+ else {
+ while (cur_bit > 0 && xs < w) {
+ if (cur_byte & cur_bit) {
+ INVERT_RTG_PIXEL(&dptr[xs << format], format)
+ }
+ xs++;
+ cur_bit >>= 1;
+ }
+ xs--;
+ cur_bit = 0x80;
+ }
+ PATTERN_LOOPX;
+ }
+ PATTERN_LOOPY;
+ }
+ return;
+ }
+}
+
+void rtg_drawline_solid(int16_t x1_, int16_t y1_, int16_t x2_, int16_t y2_, uint16_t len, uint32_t fgcol, uint16_t pitch, uint16_t format) {
+ int16_t x1 = x1_, y1 = y1_;
+ int16_t x2 = x1_ + x2_, y2 = y1 + y2_;
+
+ uint32_t fg_color[3] = {
+ (fgcol & 0xFF),
+ htobe16((fgcol & 0xFFFF)),
+ htobe32(fgcol),
+ };
+
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (y1 * pitch)];
+
+ int32_t line_step = pitch;
+ int8_t x_step = 1;
+
+ int16_t dx, dy, dx_abs, dy_abs, ix, iy, x = x1;
+
+ if (x2 < x1)
+ x_step = -1;
+ if (y2 < y1)
+ line_step = -pitch;
+
+ dx = x2 - x1;
+ dy = y2 - y1;
+ dx_abs = abs(dx);
+ dy_abs = abs(dy);
+ ix = dy_abs >> 1;
+ iy = dx_abs >> 1;
+
+ SET_RTG_PIXEL(&dptr[x << format], fg_color[format], format);
+
+ if (dx_abs >= dy_abs) {
+ if (!len) len = dx_abs;
+ for (uint16_t i = 0; i < len; i++) {
+ iy += dy_abs;
+ if (iy >= dx_abs) {
+ iy -= dx_abs;
+ dptr += line_step;
+ }
+ x += x_step;
+
+ SET_RTG_PIXEL(&dptr[x << format], fg_color[format], format);
+ }
+ }
+ else {
+ if (!len) len = dy_abs;
+ for (uint16_t i = 0; i < len; i++) {
+ ix += dx_abs;
+ if (ix >= dy_abs) {
+ ix -= dy_abs;
+ x += x_step;
+ }
+ dptr += line_step;
+
+ SET_RTG_PIXEL(&dptr[x << format], fg_color[format], format);
+ }
+ }
+}
+
+#define DRAW_LINE_PIXEL \
+ if (pattern & cur_bit) { \
+ if (invert) { INVERT_RTG_PIXEL(&dptr[x << format], format) } \
+ else { \
+ if (mask == 0xFF || format != RTGFMT_8BIT) { SET_RTG_PIXEL(&dptr[x << format], fg_color[format], format); } \
+ else { SET_RTG_PIXEL_MASK(&dptr[x << format], fg_color[format], format); } \
+ } \
+ } \
+ else if (draw_mode == DRAWMODE_JAM2) { \
+ if (invert) { INVERT_RTG_PIXEL(&dptr[x << format], format) } \
+ else { \
+ if (mask == 0xFF || format != RTGFMT_8BIT) { SET_RTG_PIXEL(&dptr[x << format], bg_color[format], format); } \
+ else { SET_RTG_PIXEL_MASK(&dptr[x << format], bg_color[format], format); } \
+ } \
+ } \
+ if ((cur_bit >>= 1) == 0) \
+ cur_bit = 0x8000;
+
+void rtg_drawline (int16_t x1_, int16_t y1_, int16_t x2_, int16_t y2_, uint16_t len, uint16_t pattern, uint16_t pattern_offset, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t format, uint8_t mask, uint8_t draw_mode) {
+ if (pattern_offset) {}
+
+ int16_t x1 = x1_, y1 = y1_;
+ int16_t x2 = x1_ + x2_, y2 = y1 + y2_;
+ uint16_t cur_bit = 0x8000;
+ //uint32_t color_mask = 0xFFFF0000;
+ uint8_t invert = 0;
+
+ uint32_t fg_color[3] = {
+ (fgcol & 0xFF),
+ htobe16((fgcol & 0xFFFF)),
+ htobe32(fgcol),
+ };
+ uint32_t bg_color[3] = {
+ (bgcol & 0xFF),
+ htobe16((bgcol & 0xFFFF)),
+ htobe32(bgcol),
+ };
+
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (y1 * pitch)];
+
+ int32_t line_step = pitch;
+ int8_t x_step = 1;
+
+ int16_t dx, dy, dx_abs, dy_abs, ix, iy, x = x1;
+
+ if (x2 < x1)
+ x_step = -1;
+ if (y2 < y1)
+ line_step = -pitch;
+
+ dx = x2 - x1;
+ dy = y2 - y1;
+ dx_abs = abs(dx);
+ dy_abs = abs(dy);
+ ix = dy_abs >> 1;
+ iy = dx_abs >> 1;
+
+ if (draw_mode & DRAWMODE_INVERSVID)
+ pattern = ~pattern;
+ if (draw_mode & DRAWMODE_COMPLEMENT) {
+ invert = 1;
+ }
+ draw_mode &= 0x01;
+
+ DRAW_LINE_PIXEL;
+
+ if (dx_abs >= dy_abs) {
+ if (!len) len = dx_abs;
+ for (uint16_t i = 0; i < len; i++) {
+ iy += dy_abs;
+ if (iy >= dx_abs) {
+ iy -= dx_abs;
+ dptr += line_step;
+ }
+ x += x_step;
+
+ DRAW_LINE_PIXEL;
+ }
+ }
+ else {
+ if (!len) len = dy_abs;
+ for (uint16_t i = 0; i < len; i++) {
+ ix += dx_abs;
+ if (ix >= dy_abs) {
+ ix -= dy_abs;
+ x += x_step;
+ }
+ dptr += line_step;
+
+ DRAW_LINE_PIXEL;
+ }
+ }
+}
+
+void rtg_p2c (int16_t sx, int16_t sy, int16_t dx, int16_t dy, int16_t w, int16_t h, uint8_t draw_mode, uint8_t planes, uint8_t mask, uint8_t layer_mask, uint16_t src_line_pitch, uint8_t *bmp_data_src) {
+ uint16_t pitch = rtg_x[3];
+ uint8_t *dptr = &rtg_mem[rtg_address_adj[0] + (dy * pitch)];
+
+ uint8_t cur_bit, base_bit, base_byte;
+ uint16_t cur_byte = 0, u8_fg = 0;
+ //uint32_t color_mask = 0xFFFFFFFF;
+
+ uint32_t plane_size = src_line_pitch * h;
+ uint8_t *bmp_data = bmp_data_src;
+
+ cur_bit = base_bit = (0x80 >> (sx % 8));
+ cur_byte = base_byte = ((sx / 8) % src_line_pitch);
+
+ if (realtime_graphics_debug) {
+ printf("P2C: %d,%d - %d,%d (%dx%d) %d, %.2X\n", sx, sy, dx, dy, w, h, planes, layer_mask);
+ printf("Mask: %.2X Minterm: %.2X\n", mask, draw_mode);
+ printf("Pitch: %d Src Pitch: %d (!!!: %.4X)\n", pitch, src_line_pitch, rtg_user[0]);
+ printf("Curbyte: %d Curbit: %d\n", cur_byte, cur_bit);
+ printf("Plane size: %d Total size: %d (%X)\n", plane_size, plane_size * planes, plane_size * planes);
+ printf("Source: %.8X - %.8X\n", rtg_address[1], rtg_address_adj[1]);
+ printf("Target: %.8X - %.8X\n", rtg_address[0], rtg_address_adj[0]);
+ fflush(stdout);
+
+ printf("Grabbing data from RTG memory.\nData:\n");
+ for (int i = 0; i < h; i++) {
+ for (int k = 0; k < planes; k++) {
+ for (int j = 0; j < src_line_pitch; j++) {
+ printf("%.2X", bmp_data_src[j + (i * src_line_pitch) + (plane_size * k)]);
+ }
+ printf(" ");
+ }
+ printf("\n");
+ }
+ }
+
+ for (int16_t line_y = 0; line_y < h; line_y++) {
+ for (int16_t x = dx; x < dx + w; x++) {
+ u8_fg = 0;
+ if (draw_mode & 0x01) {
+ DECODE_INVERTED_PLANAR_PIXEL(u8_fg)
+ }
+ else {
+ DECODE_PLANAR_PIXEL(u8_fg)
+ }
+
+ if (mask == 0xFF && (draw_mode == MINTERM_SRC || draw_mode == MINTERM_NOTSRC)) {
+ dptr[x] = u8_fg;
+ goto skip;
+ }
+
+ HANDLE_MINTERM_PIXEL(u8_fg, dptr[x], rtg_display_format);
+
+ skip:;
+ if ((cur_bit >>= 1) == 0) {
+ cur_bit = 0x80;
+ cur_byte++;
+ cur_byte %= src_line_pitch;
+ }
+
+ }
+ dptr += pitch;
+ if ((line_y + sy + 1) % h)
+ bmp_data += src_line_pitch;
+ else
+ bmp_data = bmp_data_src;
+ cur_bit = base_bit;
+ cur_byte = base_byte;
+ }
+}
--- /dev/null
+#include "emulator.h"
+#include "rtg.h"
+
+#include <pthread.h>
+#include <SDL2/SDL.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#define RTG_INIT_ERR(a) { printf(a); *data->running = 0; }
+
+uint8_t busy = 0, rtg_on = 0, rtg_initialized = 0;
+extern uint8_t *rtg_mem;
+extern uint32_t framebuffer_addr;
+extern uint32_t framebuffer_addr_adj;
+
+extern uint16_t rtg_display_width, rtg_display_height;
+extern uint16_t rtg_display_format;
+extern uint16_t rtg_pitch, rtg_total_rows;
+extern uint16_t rtg_offset_x, rtg_offset_y;
+
+static pthread_t thread_id;
+
+struct rtg_shared_data {
+ uint16_t *width, *height;
+ uint16_t *format, *pitch;
+ uint16_t *offset_x, *offset_y;
+ uint8_t *memory;
+ uint32_t *addr;
+ uint8_t *running;
+};
+
+SDL_Window *win = NULL;
+SDL_Renderer *renderer = NULL;
+SDL_Texture *img = NULL;
+
+struct rtg_shared_data rtg_share_data;
+static uint32_t palette[256];
+
+void rtg_update_screen() {}
+
+uint32_t rtg_to_sdl2[RTGFMT_NUM] = {
+ SDL_PIXELFORMAT_ARGB8888,
+ SDL_PIXELFORMAT_RGB565,
+ SDL_PIXELFORMAT_ARGB8888,
+ SDL_PIXELFORMAT_RGB555,
+};
+
+void *rtgThread(void *args) {
+
+ printf("RTG thread running\n");
+ fflush(stdout);
+
+ int reinit = 0;
+ rtg_on = 1;
+
+ uint32_t *indexed_buf = NULL;
+
+ rtg_share_data.format = &rtg_display_format;
+ rtg_share_data.width = &rtg_display_width;
+ rtg_share_data.height = &rtg_display_height;
+ rtg_share_data.pitch = &rtg_pitch;
+ rtg_share_data.offset_x = &rtg_offset_x;
+ rtg_share_data.offset_y = &rtg_offset_y;
+ rtg_share_data.memory = rtg_mem;
+ rtg_share_data.running = &rtg_on;
+ rtg_share_data.addr = &framebuffer_addr_adj;
+ struct rtg_shared_data *data = &rtg_share_data;
+
+ uint16_t width = rtg_display_width;
+ uint16_t height = rtg_display_height;
+ uint16_t format = rtg_display_format;
+ uint16_t pitch = rtg_pitch;
+
+ printf("Initializing SDL2...\n");
+ if (SDL_Init(0) < 0) {
+ printf("Failed to initialize SDL2.\n");
+ }
+
+ printf("Initializing SDL2 Video...\n");
+ if (SDL_Init(SDL_INIT_VIDEO) < 0) {
+ printf("Failed to initialize SDL2 Video..\n");
+ }
+
+reinit_sdl:;
+ if (reinit) {
+ printf("Reinitializing SDL2...\n");
+ width = rtg_display_width;
+ height = rtg_display_height;
+ format = rtg_display_format;
+ pitch = rtg_pitch;
+ if (indexed_buf) {
+ free(indexed_buf);
+ indexed_buf = NULL;
+ }
+ reinit = 0;
+ }
+
+ printf("Creating %dx%d SDL2 window...\n", width, height);
+ win = SDL_CreateWindow("Pistorm RTG", 0, 0, width, height, 0);
+ if (!win) {
+ RTG_INIT_ERR("Failed create SDL2 window.\n");
+ }
+ else {
+ printf("Created %dx%d window.\n", width, height);
+ }
+
+ printf("Creating SDL2 renderer...\n");
+ renderer = SDL_CreateRenderer(win, -1, SDL_RENDERER_ACCELERATED);
+ if (!renderer) {
+ RTG_INIT_ERR("Failed create SDL2 renderer.\n");
+ }
+ else {
+ printf("Created SDL2 renderer.\n");
+ }
+
+ printf("Creating SDL2 texture...\n");
+ img = SDL_CreateTexture(renderer, rtg_to_sdl2[format], SDL_TEXTUREACCESS_TARGET, width, height);
+ if (!img) {
+ RTG_INIT_ERR("Failed create SDL2 texture.\n");
+ }
+ else {
+ printf("Created %dx%d texture.\n", width, height);
+ }
+
+ switch (format) {
+ case RTGFMT_8BIT:
+ indexed_buf = calloc(1, width * height * 4);
+ break;
+ case RTGFMT_RBG565:
+ indexed_buf = calloc(1, width * height * 2);
+ break;
+ default:
+ break;
+ }
+
+ uint64_t frame_start = 0, frame_end = 0;
+ float elapsed = 0.0f;
+
+ while (1) {
+ if (renderer && win && img) {
+ frame_start = SDL_GetPerformanceCounter();
+ SDL_RenderClear(renderer);
+ if (*data->running) {
+ switch (format) {
+ case RTGFMT_RGB32:
+ SDL_UpdateTexture(img, NULL, &data->memory[*data->addr], pitch);
+ break;
+ case RTGFMT_RBG565:
+ SDL_UpdateTexture(img, NULL, (uint8_t *)indexed_buf, width * 2);
+ break;
+ case RTGFMT_8BIT:
+ SDL_UpdateTexture(img, NULL, (uint8_t *)indexed_buf, width * 4);
+ break;
+ }
+ SDL_RenderCopy(renderer, img, NULL, NULL);
+ }
+ SDL_RenderPresent(renderer);
+ //usleep(16667); //ghetto 60hz
+ if (height != *data->height || width != *data->width || format != *data->format) {
+ printf("Reinitializing due to something change.\n");
+ reinit = 1;
+ goto shutdown_sdl;
+ }
+ switch (format) {
+ case RTGFMT_8BIT:
+ for (int y = 0; y < height; y++) {
+ for (int x = 0; x < width; x++) {
+ indexed_buf[x + (y * width)] = palette[data->memory[*data->addr + x + (y * pitch)]];
+ }
+ }
+ break;
+ case RTGFMT_RBG565:
+ for (int y = 0; y < height; y++) {
+ for (int x = 0; x < width; x++) {
+ ((uint16_t *)indexed_buf)[x + (y * width)] = be16toh(((uint16_t *)data->memory)[(*data->addr / 2) + x + (y * (pitch / 2))]);
+ }
+ }
+ break;
+ }
+ frame_end = SDL_GetPerformanceCounter();
+ elapsed = (frame_end - frame_start) / (float)SDL_GetPerformanceFrequency() * 1000.0f;
+ pitch = rtg_pitch;
+ SDL_Delay(floor(16.66666f - elapsed));
+ }
+ else
+ break;
+ }
+
+ rtg_initialized = 0;
+ printf("RTG thread shut down.\n");
+
+shutdown_sdl:;
+ if (img) SDL_DestroyTexture(img);
+ if (renderer) SDL_DestroyRenderer(renderer);
+ if (win) SDL_DestroyWindow(win);
+
+ win = NULL;
+ img = NULL;
+ renderer = NULL;
+
+ if (reinit)
+ goto reinit_sdl;
+
+ if (indexed_buf)
+ free(indexed_buf);
+
+ SDL_QuitSubSystem(SDL_INIT_VIDEO);
+ SDL_Quit();
+
+ return args;
+}
+
+void rtg_set_clut_entry(uint8_t index, uint32_t xrgb) {
+ palette[index] = xrgb;
+}
+
+void rtg_init_display() {
+ int err;
+ rtg_on = 1;
+
+ if (!rtg_initialized) {
+ err = pthread_create(&thread_id, NULL, &rtgThread, (void *)&rtg_share_data);
+ if (err != 0) {
+ rtg_on = 0;
+ printf("can't create RTG thread :[%s]", strerror(err));
+ }
+ else {
+ rtg_initialized = 1;
+ pthread_setname_np(thread_id, "pistorm: rtg");
+ printf("RTG Thread created successfully\n");
+ }
+ }
+ printf("RTG display enabled.\n");
+}
+
+void rtg_shutdown_display() {
+ printf("RTG display disabled.\n");
+ rtg_on = 0;
+}
--- /dev/null
+#include <stdint.h>
+#include <endian.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include "rtg.h"
+#include "config_file/config_file.h"
+
+uint8_t rtg_u8[4];
+uint16_t rtg_x[8], rtg_y[8];
+uint16_t rtg_user[8];
+uint16_t rtg_format;
+uint32_t rtg_address[8];
+uint32_t rtg_address_adj[8];
+uint32_t rtg_rgb[8];
+
+static uint8_t display_enabled = 0xFF;
+
+uint16_t rtg_display_width, rtg_display_height;
+uint16_t rtg_display_format;
+uint16_t rtg_pitch, rtg_total_rows;
+uint16_t rtg_offset_x, rtg_offset_y;
+
+uint8_t *rtg_mem; // FIXME
+
+uint32_t framebuffer_addr = 0;
+uint32_t framebuffer_addr_adj = 0;
+
+static void handle_rtg_command(uint32_t cmd);
+static struct timespec f1, f2;
+
+uint8_t realtime_graphics_debug = 0;
+extern int cpu_emulation_running;
+
+static const char *op_type_names[OP_TYPE_NUM] = {
+ "BYTE",
+ "WORD",
+ "LONGWORD",
+ "MEM",
+};
+
+static const char *rtg_format_names[RTGFMT_NUM] = {
+ "8BPP CLUT",
+ "16BPP RGB (565)",
+ "32BPP RGB (RGBA)",
+ "15BPP RGB (555)",
+};
+
+int init_rtg_data() {
+ rtg_mem = calloc(1, 40 * SIZE_MEGA);
+ if (!rtg_mem) {
+ printf("Failed to allocate RTG video memory.\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+extern uint8_t busy, rtg_on;
+void rtg_update_screen();
+
+unsigned int rtg_read(uint32_t address, uint8_t mode) {
+ //printf("%s read from RTG: %.8X\n", op_type_names[mode], address);
+ if (address == RTG_COMMAND) {
+ return 0xFFCF;
+ }
+ if (address >= PIGFX_REG_SIZE) {
+ if (rtg_mem && (address - PIGFX_REG_SIZE) < PIGFX_UPPER) {
+ switch (mode) {
+ case OP_TYPE_BYTE:
+ return (rtg_mem[address - PIGFX_REG_SIZE]);
+ break;
+ case OP_TYPE_WORD:
+ return be16toh(*(( uint16_t *) (&rtg_mem[address - PIGFX_REG_SIZE])));
+ break;
+ case OP_TYPE_LONGWORD:
+ return be32toh(*(( uint32_t *) (&rtg_mem[address - PIGFX_REG_SIZE])));
+ break;
+ default:
+ return 0;
+ }
+ }
+ }
+
+ return 0;
+}
+
+struct timespec diff(struct timespec start, struct timespec end)
+{
+ struct timespec temp;
+ if ((end.tv_nsec-start.tv_nsec)<0) {
+ temp.tv_sec = end.tv_sec-start.tv_sec-1;
+ temp.tv_nsec = 1000000000+end.tv_nsec-start.tv_nsec;
+ } else {
+ temp.tv_sec = end.tv_sec-start.tv_sec;
+ temp.tv_nsec = end.tv_nsec-start.tv_nsec;
+ }
+ return temp;
+}
+
+#define CHKREG(a, b) case a: b = value; break;
+
+void rtg_write(uint32_t address, uint32_t value, uint8_t mode) {
+ //printf("%s write to RTG: %.8X (%.8X)\n", op_type_names[mode], address, value);
+ if (address >= PIGFX_REG_SIZE) {
+ /*if ((address - PIGFX_REG_SIZE) < framebuffer_addr) {// || (address - PIGFX_REG_SIZE) > framebuffer_addr + ((rtg_display_width << rtg_display_format) * rtg_display_height)) {
+ printf("Write to RTG memory outside frame buffer %.8X (%.8X).\n", (address - PIGFX_REG_SIZE), framebuffer_addr);
+ }*/
+ if (rtg_mem && (address - PIGFX_REG_SIZE) < PIGFX_UPPER) {
+ switch (mode) {
+ case OP_TYPE_BYTE:
+ rtg_mem[address - PIGFX_REG_SIZE] = value;
+ break;
+ case OP_TYPE_WORD:
+ *(( uint16_t *) (&rtg_mem[address - PIGFX_REG_SIZE])) = htobe16(value);
+ break;
+ case OP_TYPE_LONGWORD:
+ *(( uint32_t *) (&rtg_mem[address - PIGFX_REG_SIZE])) = htobe32(value);
+ break;
+ default:
+ return;
+ }
+ }
+ }
+ else {
+ switch (mode) {
+ case OP_TYPE_BYTE:
+ switch (address) {
+ CHKREG(RTG_U81, rtg_u8[0]);
+ CHKREG(RTG_U82, rtg_u8[1]);
+ CHKREG(RTG_U83, rtg_u8[2]);
+ CHKREG(RTG_U84, rtg_u8[3]);
+ }
+ break;
+ case OP_TYPE_WORD:
+ switch (address) {
+ CHKREG(RTG_X1, rtg_x[0]);
+ CHKREG(RTG_X2, rtg_x[1]);
+ CHKREG(RTG_X3, rtg_x[2]);
+ CHKREG(RTG_X4, rtg_x[3]);
+ CHKREG(RTG_X5, rtg_x[4]);
+ CHKREG(RTG_Y1, rtg_y[0]);
+ CHKREG(RTG_Y2, rtg_y[1]);
+ CHKREG(RTG_Y3, rtg_y[2]);
+ CHKREG(RTG_Y4, rtg_y[3]);
+ CHKREG(RTG_Y5, rtg_y[4]);
+ CHKREG(RTG_U1, rtg_user[0]);
+ CHKREG(RTG_U2, rtg_user[1]);
+ CHKREG(RTG_FORMAT, rtg_format);
+ case RTG_COMMAND:
+ handle_rtg_command(value);
+ break;
+ }
+ break;
+ case OP_TYPE_LONGWORD:
+ switch (address) {
+ case RTG_ADDR1:
+ rtg_address[0] = value;
+ rtg_address_adj[0] = value - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
+ break;
+ case RTG_ADDR2:
+ rtg_address[1] = value;
+ rtg_address_adj[1] = value - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
+ break;
+ CHKREG(RTG_ADDR3, rtg_address[2]);
+ CHKREG(RTG_ADDR4, rtg_address[3]);
+ CHKREG(RTG_RGB1, rtg_rgb[0]);
+ CHKREG(RTG_RGB2, rtg_rgb[1]);
+ }
+ break;
+ }
+ }
+
+ return;
+}
+
+#define gdebug(a) if (realtime_graphics_debug) { printf(a); m68k_end_timeslice(); cpu_emulation_running = 0; }
+
+static void handle_rtg_command(uint32_t cmd) {
+ //printf("Handling RTG command %d (%.8X)\n", cmd, cmd);
+ switch (cmd) {
+ case RTGCMD_SETGC:
+ rtg_display_format = rtg_format;
+ rtg_display_width = rtg_x[0];
+ rtg_display_height = rtg_y[0];
+ if (rtg_u8[0]) {
+ //rtg_pitch = rtg_display_width << rtg_format;
+ framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
+ rtg_total_rows = rtg_y[1];
+ }
+ else {
+ //rtg_pitch = rtg_display_width << rtg_format;
+ framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
+ rtg_total_rows = rtg_y[1];
+ }
+ //printf("Set RTG mode:\n");
+ //printf("%dx%d pixels\n", rtg_display_width, rtg_display_height);
+ //printf("Pixel format: %s\n", rtg_format_names[rtg_display_format]);
+ break;
+ case RTGCMD_SETPAN:
+ //printf("Command: SetPan.\n");
+ rtg_offset_x = rtg_x[1];
+ rtg_offset_y = rtg_y[1];
+ rtg_pitch = (rtg_x[0] << rtg_display_format);
+ framebuffer_addr = rtg_address[0] - (PIGFX_RTG_BASE + PIGFX_REG_SIZE);
+ framebuffer_addr_adj = framebuffer_addr + (rtg_offset_x << rtg_display_format) + (rtg_offset_y * rtg_pitch);
+ //printf("Set panning to $%.8X (%.8X)\n", framebuffer_addr, rtg_address[0]);
+ //printf("(Panned: $%.8X)\n", framebuffer_addr_adj);
+ //printf("Offset X/Y: %d/%d\n", rtg_offset_x, rtg_offset_y);
+ printf("Pitch: %d (%d bytes)\n", rtg_x[0], rtg_pitch);
+ break;
+ case RTGCMD_SETCLUT: {
+ //printf("Command: SetCLUT.\n");
+ //printf("Set palette entry %d to %d, %d, %d\n", rtg_u8[0], rtg_u8[1], rtg_u8[2], rtg_u8[3]);
+ //printf("Set palette entry %d to 32-bit palette color: %.8X\n", rtg_u8[0], rtg_rgb[0]);
+ rtg_set_clut_entry(rtg_u8[0], rtg_rgb[0]);
+ break;
+ }
+ case RTGCMD_SETDISPLAY:
+ //printf("RTG SetDisplay %s\n", (rtg_u8[1]) ? "enabled" : "disabled");
+ // I remeber wrongs.
+ //printf("Command: SetDisplay.\n");
+ break;
+ case RTGCMD_ENABLE:
+ case RTGCMD_SETSWITCH:
+ //printf("RTG SetSwitch %s\n", ((rtg_x[0]) & 0x01) ? "enabled" : "disabled");
+ //printf("LAL: %.4X\n", rtg_x[0]);
+ if (display_enabled != ((rtg_x[0]) & 0x01)) {
+ display_enabled = ((rtg_x[0]) & 0x01);
+ if (display_enabled) {
+ rtg_init_display();
+ }
+ else
+ rtg_shutdown_display();
+ }
+ break;
+ case RTGCMD_FILLRECT:
+ if (rtg_u8[0] == 0xFF || rtg_format != RTGFMT_8BIT) {
+ rtg_fillrect_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_rgb[0], rtg_x[2], rtg_format);
+ gdebug("FillRect Solid\n");
+ }
+ else {
+ rtg_fillrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_rgb[0], rtg_x[2], rtg_format, rtg_u8[0]);
+ gdebug("FillRect Masked\n");
+ }
+ break;
+ case RTGCMD_INVERTRECT:
+ rtg_invertrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_format, rtg_u8[0]);
+ gdebug("InvertRect\n");
+ break;
+ case RTGCMD_BLITRECT:
+ if (rtg_u8[0] == 0xFF || rtg_format != RTGFMT_8BIT) {
+ rtg_blitrect_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_format);
+ gdebug("BlitRect Solid\n");
+ }
+ else {
+ rtg_blitrect(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_format, rtg_u8[0]);
+ gdebug("BlitRect Masked\n");
+ }
+ break;
+ case RTGCMD_BLITRECT_NOMASK_COMPLETE:
+ rtg_blitrect_nomask_complete(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_x[4], rtg_address[0], rtg_address[1], rtg_format, rtg_u8[0]);
+ gdebug("BlitRectNoMaskComplete\n");
+ break;
+ case RTGCMD_BLITPATTERN:
+ rtg_blitpattern(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_address[0], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_format, rtg_x[2], rtg_y[2], rtg_u8[0], rtg_u8[1], rtg_u8[2]);
+ gdebug("BlitPattern\n");
+ return;
+ case RTGCMD_BLITTEMPLATE:
+ rtg_blittemplate(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_address[0], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_x[4], rtg_format, rtg_x[2], rtg_u8[0], rtg_u8[1]);
+ gdebug("BlitTemplate\n");
+ break;
+ case RTGCMD_DRAWLINE:
+ if (rtg_u8[0] == 0xFF && rtg_y[2] == 0xFFFF)
+ rtg_drawline_solid(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_rgb[0], rtg_x[3], rtg_format);
+ else
+ rtg_drawline(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[4], rtg_rgb[0], rtg_rgb[1], rtg_x[3], rtg_format, rtg_u8[0], rtg_u8[1]);
+ gdebug("DrawLine\n");
+ break;
+ case RTGCMD_P2C:
+ rtg_p2c(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_u8[1], rtg_u8[2], rtg_u8[0], (rtg_user[0] >> 0x8), rtg_x[4], (uint8_t *)&rtg_mem[rtg_address_adj[1]]);
+ //rtg_p2c_broken(rtg_x[0], rtg_y[0], rtg_x[1], rtg_y[1], rtg_x[2], rtg_y[2], rtg_x[3], rtg_u8[0], rtg_u8[1], rtg_u8[2], rtg_user[0]);
+ gdebug("Planar2Chunky\n");
+ break;
+ case RTGCMD_P2D:
+ break;
+ }
+}
--- /dev/null
+#define PIGFX_RTG_BASE 0x70000000
+#define PIGFX_REG_SIZE 0x00010000
+#define PIGFX_RTG_SIZE 0x02000000
+#define PIGFX_SCRATCH_SIZE 0x00800000
+#define PIGFX_SCRATCH_AREA 0x72010000
+#define PIGFX_UPPER 0x72810000
+
+#define CARD_OFFSET 0
+
+#include "rtg_driver_amiga/rtg_enums.h"
+
+void rtg_write(uint32_t address, uint32_t value, uint8_t mode);
+unsigned int rtg_read(uint32_t address, uint8_t mode);
+void rtg_set_clut_entry(uint8_t index, uint32_t xrgb);
+void rtg_init_display();
+void rtg_shutdown_display();
+
+void rtg_fillrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t color, uint16_t pitch, uint16_t format, uint8_t mask);
+void rtg_fillrect_solid(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t color, uint16_t pitch, uint16_t format);
+void rtg_invertrect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format, uint8_t mask);
+void rtg_blitrect(uint16_t x, uint16_t y, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format, uint8_t mask);
+void rtg_blitrect_solid(uint16_t x, uint16_t y, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t pitch, uint16_t format);
+void rtg_blitrect_nomask_complete(uint16_t sx, uint16_t sy, uint16_t dx, uint16_t dy, uint16_t w, uint16_t h, uint16_t srcpitch, uint16_t dstpitch, uint32_t src_addr, uint32_t dst_addr, uint16_t format, uint8_t minterm);
+void rtg_blittemplate(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t src_addr, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t t_pitch, uint16_t format, uint16_t offset_x, uint8_t mask, uint8_t draw_mode);
+void rtg_blitpattern(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint32_t src_addr, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t format, uint16_t offset_x, uint16_t offset_y, uint8_t mask, uint8_t draw_mode, uint8_t loop_rows);
+void rtg_drawline_solid(int16_t x1_, int16_t y1_, int16_t x2_, int16_t y2_, uint16_t len, uint32_t fgcol, uint16_t pitch, uint16_t format);
+void rtg_drawline (int16_t x1_, int16_t y1_, int16_t x2_, int16_t y2_, uint16_t len, uint16_t pattern, uint16_t pattern_offset, uint32_t fgcol, uint32_t bgcol, uint16_t pitch, uint16_t format, uint8_t mask, uint8_t draw_mode);
+
+void rtg_p2c (int16_t sx, int16_t sy, int16_t dx, int16_t dy, int16_t w, int16_t h, uint8_t draw_mode, uint8_t planes, uint8_t mask, uint8_t layer_mask, uint16_t src_line_pitch, uint8_t *bmp_data_src);
+
+#define PATTERN_LOOPX \
+ tmpl_x ^= 0x01; \
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x]; \
+
+#define PATTERN_LOOPY \
+ sptr += 2 ; \
+ if ((ys + offset_y + 1) % loop_rows == 0) \
+ sptr = sptr_base; \
+ tmpl_x = (offset_x / 8) % 2; \
+ cur_bit = base_bit; \
+ dptr += pitch;
+
+#define TEMPLATE_LOOPX \
+ tmpl_x++; \
+ cur_byte = (invert) ? sptr[tmpl_x] ^ 0xFF : sptr[tmpl_x]; \
+
+#define TEMPLATE_LOOPY \
+ sptr += t_pitch; \
+ dptr += pitch; \
+ tmpl_x = offset_x / 8; \
+ cur_bit = base_bit;
+
+#define INVERT_RTG_PIXELS(dest, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ if (cur_byte & 0x80) (dest)[0] ^= mask; \
+ if (cur_byte & 0x40) (dest)[1] ^= mask; \
+ if (cur_byte & 0x20) (dest)[2] ^= mask; \
+ if (cur_byte & 0x10) (dest)[3] ^= mask; \
+ if (cur_byte & 0x08) (dest)[4] ^= mask; \
+ if (cur_byte & 0x04) (dest)[5] ^= mask; \
+ if (cur_byte & 0x02) (dest)[6] ^= mask; \
+ if (cur_byte & 0x01) (dest)[7] ^= mask; \
+ break; \
+ case RTGFMT_RBG565: \
+ if (cur_byte & 0x80) ((uint16_t *)dest)[0] = ~((uint16_t *)dest)[0]; \
+ if (cur_byte & 0x40) ((uint16_t *)dest)[1] = ~((uint16_t *)dest)[1]; \
+ if (cur_byte & 0x20) ((uint16_t *)dest)[2] = ~((uint16_t *)dest)[2]; \
+ if (cur_byte & 0x10) ((uint16_t *)dest)[3] = ~((uint16_t *)dest)[3]; \
+ if (cur_byte & 0x08) ((uint16_t *)dest)[4] = ~((uint16_t *)dest)[4]; \
+ if (cur_byte & 0x04) ((uint16_t *)dest)[5] = ~((uint16_t *)dest)[5]; \
+ if (cur_byte & 0x02) ((uint16_t *)dest)[6] = ~((uint16_t *)dest)[6]; \
+ if (cur_byte & 0x01) ((uint16_t *)dest)[7] = ~((uint16_t *)dest)[7]; \
+ break; \
+ case RTGFMT_RGB32: \
+ if (cur_byte & 0x80) ((uint32_t *)dest)[0] = ~((uint32_t *)dest)[0]; \
+ if (cur_byte & 0x40) ((uint32_t *)dest)[1] = ~((uint32_t *)dest)[1]; \
+ if (cur_byte & 0x20) ((uint32_t *)dest)[2] = ~((uint32_t *)dest)[2]; \
+ if (cur_byte & 0x10) ((uint32_t *)dest)[3] = ~((uint32_t *)dest)[3]; \
+ if (cur_byte & 0x08) ((uint32_t *)dest)[4] = ~((uint32_t *)dest)[4]; \
+ if (cur_byte & 0x04) ((uint32_t *)dest)[5] = ~((uint32_t *)dest)[5]; \
+ if (cur_byte & 0x02) ((uint32_t *)dest)[6] = ~((uint32_t *)dest)[6]; \
+ if (cur_byte & 0x01) ((uint32_t *)dest)[7] = ~((uint32_t *)dest)[7]; \
+ break; \
+ }
+
+#define SET_RTG_PIXELS_MASK(dest, src, format) \
+ if (cur_byte & 0x80) (dest)[0] = src ^ ((dest)[0] & ~mask); \
+ if (cur_byte & 0x40) (dest)[1] = src ^ ((dest)[1] & ~mask); \
+ if (cur_byte & 0x20) (dest)[2] = src ^ ((dest)[2] & ~mask); \
+ if (cur_byte & 0x10) (dest)[3] = src ^ ((dest)[3] & ~mask); \
+ if (cur_byte & 0x08) (dest)[4] = src ^ ((dest)[4] & ~mask); \
+ if (cur_byte & 0x04) (dest)[5] = src ^ ((dest)[5] & ~mask); \
+ if (cur_byte & 0x02) (dest)[6] = src ^ ((dest)[6] & ~mask); \
+ if (cur_byte & 0x01) (dest)[7] = src ^ ((dest)[7] & ~mask); \
+
+#define SET_RTG_PIXELS2_COND_MASK(dest, src, src2, format) \
+ (dest)[0] = (cur_byte & 0x80) ? src : src2 ^ ((dest)[0] & ~mask); \
+ (dest)[1] = (cur_byte & 0x40) ? src : src2 ^ ((dest)[1] & ~mask); \
+ (dest)[2] = (cur_byte & 0x20) ? src : src2 ^ ((dest)[2] & ~mask); \
+ (dest)[3] = (cur_byte & 0x10) ? src : src2 ^ ((dest)[3] & ~mask); \
+ (dest)[4] = (cur_byte & 0x08) ? src : src2 ^ ((dest)[4] & ~mask); \
+ (dest)[5] = (cur_byte & 0x04) ? src : src2 ^ ((dest)[5] & ~mask); \
+ (dest)[6] = (cur_byte & 0x02) ? src : src2 ^ ((dest)[6] & ~mask); \
+ (dest)[7] = (cur_byte & 0x01) ? src : src2 ^ ((dest)[7] & ~mask); \
+
+
+#define SET_RTG_PIXELS(dest, src, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ if (cur_byte & 0x80) (dest)[0] = src; \
+ if (cur_byte & 0x40) (dest)[1] = src; \
+ if (cur_byte & 0x20) (dest)[2] = src; \
+ if (cur_byte & 0x10) (dest)[3] = src; \
+ if (cur_byte & 0x08) (dest)[4] = src; \
+ if (cur_byte & 0x04) (dest)[5] = src; \
+ if (cur_byte & 0x02) (dest)[6] = src; \
+ if (cur_byte & 0x01) (dest)[7] = src; \
+ break; \
+ case RTGFMT_RBG565: \
+ if (cur_byte & 0x80) ((uint16_t *)dest)[0] = src; \
+ if (cur_byte & 0x40) ((uint16_t *)dest)[1] = src; \
+ if (cur_byte & 0x20) ((uint16_t *)dest)[2] = src; \
+ if (cur_byte & 0x10) ((uint16_t *)dest)[3] = src; \
+ if (cur_byte & 0x08) ((uint16_t *)dest)[4] = src; \
+ if (cur_byte & 0x04) ((uint16_t *)dest)[5] = src; \
+ if (cur_byte & 0x02) ((uint16_t *)dest)[6] = src; \
+ if (cur_byte & 0x01) ((uint16_t *)dest)[7] = src; \
+ break; \
+ case RTGFMT_RGB32: \
+ if (cur_byte & 0x80) ((uint32_t *)dest)[0] = src; \
+ if (cur_byte & 0x40) ((uint32_t *)dest)[1] = src; \
+ if (cur_byte & 0x20) ((uint32_t *)dest)[2] = src; \
+ if (cur_byte & 0x10) ((uint32_t *)dest)[3] = src; \
+ if (cur_byte & 0x08) ((uint32_t *)dest)[4] = src; \
+ if (cur_byte & 0x04) ((uint32_t *)dest)[5] = src; \
+ if (cur_byte & 0x02) ((uint32_t *)dest)[6] = src; \
+ if (cur_byte & 0x01) ((uint32_t *)dest)[7] = src; \
+ break; \
+ }
+
+#define SET_RTG_PIXELS2_COND(dest, src, src2, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ (dest)[0] = (cur_byte & 0x80) ? src : src2; \
+ (dest)[1] = (cur_byte & 0x40) ? src : src2; \
+ (dest)[2] = (cur_byte & 0x20) ? src : src2; \
+ (dest)[3] = (cur_byte & 0x10) ? src : src2; \
+ (dest)[4] = (cur_byte & 0x08) ? src : src2; \
+ (dest)[5] = (cur_byte & 0x04) ? src : src2; \
+ (dest)[6] = (cur_byte & 0x02) ? src : src2; \
+ (dest)[7] = (cur_byte & 0x01) ? src : src2; \
+ break; \
+ case RTGFMT_RBG565: \
+ ((uint16_t *)dest)[0] = (cur_byte & 0x80) ? src : src2; \
+ ((uint16_t *)dest)[1] = (cur_byte & 0x40) ? src : src2; \
+ ((uint16_t *)dest)[2] = (cur_byte & 0x20) ? src : src2; \
+ ((uint16_t *)dest)[3] = (cur_byte & 0x10) ? src : src2; \
+ ((uint16_t *)dest)[4] = (cur_byte & 0x08) ? src : src2; \
+ ((uint16_t *)dest)[5] = (cur_byte & 0x04) ? src : src2; \
+ ((uint16_t *)dest)[6] = (cur_byte & 0x02) ? src : src2; \
+ ((uint16_t *)dest)[7] = (cur_byte & 0x01) ? src : src2; \
+ break; \
+ case RTGFMT_RGB32: \
+ ((uint32_t *)dest)[0] = (cur_byte & 0x80) ? src : src2; \
+ ((uint32_t *)dest)[1] = (cur_byte & 0x40) ? src : src2; \
+ ((uint32_t *)dest)[2] = (cur_byte & 0x20) ? src : src2; \
+ ((uint32_t *)dest)[3] = (cur_byte & 0x10) ? src : src2; \
+ ((uint32_t *)dest)[4] = (cur_byte & 0x08) ? src : src2; \
+ ((uint32_t *)dest)[5] = (cur_byte & 0x04) ? src : src2; \
+ ((uint32_t *)dest)[6] = (cur_byte & 0x02) ? src : src2; \
+ ((uint32_t *)dest)[7] = (cur_byte & 0x01) ? src : src2; \
+ break; \
+ }
+
+
+
+#define SET_RTG_PIXEL(dest, src, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ *(dest) = src; \
+ break; \
+ case RTGFMT_RBG565: \
+ *((uint16_t *)dest) = src; \
+ break; \
+ case RTGFMT_RGB32: \
+ *((uint32_t *)dest) = src; \
+ break; \
+ }
+
+#define SET_RTG_PIXEL_MASK(dest, src, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ *(dest) = src ^ (*(dest) & ~mask); \
+ break; \
+ case RTGFMT_RBG565: \
+ *((uint16_t *)dest) = src; \
+ break; \
+ case RTGFMT_RGB32: \
+ *((uint32_t *)dest) = src; \
+ break; \
+ }
+
+#define INVERT_RTG_PIXEL(dest, format) \
+ switch (format) { \
+ case RTGFMT_8BIT: \
+ *(dest) ^= mask; \
+ break; \
+ case RTGFMT_RBG565: \
+ *((uint16_t *)dest) = ~*((uint16_t *)dest); \
+ break; \
+ case RTGFMT_RGB32: \
+ *((uint32_t *)dest) = ~*((uint32_t *)dest); \
+ break; \
+ }
+
+#define HANDLE_MINTERM_PIXEL(s, d, f) \
+ switch(draw_mode) {\
+ case MINTERM_NOR: \
+ s &= ~(d); \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_ONLYDST: \
+ d = d & ~(s); break; \
+ case MINTERM_NOTSRC: \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_ONLYSRC: \
+ s &= (d ^ 0xFF); \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_INVERT: \
+ d ^= 0xFF; break; \
+ case MINTERM_EOR: \
+ d ^= s; break; \
+ case MINTERM_NAND: \
+ s = ~(d & ~(s)) & mask; \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_AND: \
+ s &= d; \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_NEOR: \
+ d ^= (s & mask); break; \
+ case MINTERM_DST: /* This one does nothing. */ \
+ return; break; \
+ case MINTERM_NOTONLYSRC: \
+ d |= (s & mask); break; \
+ case MINTERM_SRC: \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_NOTONLYDST: \
+ s = ~(d & s) & mask; \
+ SET_RTG_PIXEL_MASK(&d, s, f); break; \
+ case MINTERM_OR: \
+ d |= (s & mask); break; \
+ }
+
+
+#define DECODE_PLANAR_PIXEL(a) \
+ switch (planes) { \
+ case 8: if (layer_mask & 0x80 && bmp_data[(plane_size * 7) + cur_byte] & cur_bit) a |= 0x80; \
+ /* Fallthrough */ \
+ case 7: if (layer_mask & 0x40 && bmp_data[(plane_size * 6) + cur_byte] & cur_bit) a |= 0x40; \
+ /* Fallthrough */ \
+ case 6: if (layer_mask & 0x20 && bmp_data[(plane_size * 5) + cur_byte] & cur_bit) a |= 0x20; \
+ /* Fallthrough */ \
+ case 5: if (layer_mask & 0x10 && bmp_data[(plane_size * 4) + cur_byte] & cur_bit) a |= 0x10; \
+ /* Fallthrough */ \
+ case 4: if (layer_mask & 0x08 && bmp_data[(plane_size * 3) + cur_byte] & cur_bit) a |= 0x08; \
+ /* Fallthrough */ \
+ case 3: if (layer_mask & 0x04 && bmp_data[(plane_size * 2) + cur_byte] & cur_bit) a |= 0x04; \
+ /* Fallthrough */ \
+ case 2: if (layer_mask & 0x02 && bmp_data[plane_size + cur_byte] & cur_bit) a |= 0x02; \
+ /* Fallthrough */ \
+ case 1: if (layer_mask & 0x01 && bmp_data[cur_byte] & cur_bit) a |= 0x01; \
+ break; \
+ }
+
+#define DECODE_INVERTED_PLANAR_PIXEL(a) \
+ switch (planes) { \
+ case 8: if (layer_mask & 0x80 && (bmp_data[(plane_size * 7) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x80; \
+ /* Fallthrough */ \
+ case 7: if (layer_mask & 0x40 && (bmp_data[(plane_size * 6) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x40; \
+ /* Fallthrough */ \
+ case 6: if (layer_mask & 0x20 && (bmp_data[(plane_size * 5) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x20; \
+ /* Fallthrough */ \
+ case 5: if (layer_mask & 0x10 && (bmp_data[(plane_size * 4) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x10; \
+ /* Fallthrough */ \
+ case 4: if (layer_mask & 0x08 && (bmp_data[(plane_size * 3) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x08; \
+ /* Fallthrough */ \
+ case 3: if (layer_mask & 0x04 && (bmp_data[(plane_size * 2) + cur_byte] ^ 0xFF) & cur_bit) a |= 0x04; \
+ /* Fallthrough */ \
+ case 2: if (layer_mask & 0x02 && (bmp_data[plane_size + cur_byte] ^ 0xFF) & cur_bit) a |= 0x02; \
+ /* Fallthrough */ \
+ case 1: if (layer_mask & 0x01 && (bmp_data[cur_byte] ^ 0xFF) & cur_bit) a |= 0x01; \
+ break; \
+ }
--- /dev/null
+#ifndef boardinfo_H
+#define boardinfo_H
+
+#ifndef LIBRARIES_PICASSO96_H
+#include <libraries/Picasso96.h>
+#endif
+
+#ifndef EXEC_INTERRUPTS_H
+#include <exec/interrupts.h>
+#endif
+
+#ifndef EXEC_LIBRARIES_H
+#include <exec/libraries.h>
+#endif
+
+#ifndef EXEC_SEMAPHORES_H
+#include <exec/semaphores.h>
+#endif
+
+#ifndef GRAPHICS_GFX_H
+#include <graphics/gfx.h>
+#endif
+
+#ifndef GRAPHICS_VIEW_H
+#include <graphics/view.h>
+#endif
+
+#ifndef DEVICES_TIMER_H
+#include <devices/timer.h>
+#endif
+
+#ifndef settings_H
+#include "settings.h"
+#endif
+
+/* registerized parameters */
+
+#ifdef __STORMGCC__
+ #define ASM
+#else
+ #ifdef __GNUC__
+ #define ASM
+ #define __REGD0(x) x __asm("d0")
+ #define __REGD1(x) x __asm("d1")
+ #define __REGD2(x) x __asm("d2")
+ #define __REGD3(x) x __asm("d3")
+ #define __REGD4(x) x __asm("d4")
+ #define __REGD5(x) x __asm("d5")
+ #define __REGD6(x) x __asm("d6")
+ #define __REGD7(x) x __asm("d7")
+ #define __REGA0(x) x __asm("a0")
+ #define __REGA1(x) x __asm("a1")
+ #define __REGA2(x) x __asm("a2")
+ #define __REGA3(x) x __asm("a3")
+ #define __REGA4(x) x __asm("a4")
+ #define __REGA5(x) x __asm("a5")
+ #define __REGA6(x) x __asm("a6")
+ #define __REGA7(x) x __asm("a7")
+ #else
+ #define ASM
+ #define __REGD0(x) __reg("d0") x
+ #define __REGD1(x) __reg("d1") x
+ #define __REGD2(x) __reg("d2") x
+ #define __REGD3(x) __reg("d3") x
+ #define __REGD4(x) __reg("d4") x
+ #define __REGD5(x) __reg("d5") x
+ #define __REGD6(x) __reg("d6") x
+ #define __REGD7(x) __reg("d7") x
+ #define __REGA0(x) __reg("a0") x
+ #define __REGA1(x) __reg("a1") x
+ #define __REGA2(x) __reg("a2") x
+ #define __REGA3(x) __reg("a3") x
+ #define __REGA4(x) __reg("a4") x
+ #define __REGA5(x) __reg("a5") x
+ #define __REGA6(x) __reg("a6") x
+ #define __REGA7(x) __reg("a7") x
+ #endif
+#endif
+
+/************************************************************************/
+
+#define MAXSPRITEWIDTH 32
+#define MAXSPRITEHEIGHT 48
+
+/************************************************************************/
+
+#define DI_P96_INVALID 0x1000
+#define DI_P96_MONITOOL 0x2000
+
+/************************************************************************/
+/* Types for BoardType Identification
+ */
+typedef enum {
+ BT_NoBoard,
+ BT_oMniBus,
+ BT_Graffity,
+ BT_CyberVision,
+ BT_Domino,
+ BT_Merlin,
+ BT_PicassoII,
+ BT_Piccolo,
+ BT_RetinaBLT,
+ BT_Spectrum,
+ BT_PicassoIV,
+ BT_PiccoloSD64,
+ BT_A2410,
+ BT_Pixel64,
+ BT_uaegfx, // 14
+ BT_CVision3D,
+ BT_Altais,
+ BT_Prometheus,
+ BT_Mediator,
+ BT_powerfb,
+ BT_powerpci,
+ BT_CVisionPPC,
+ BT_GREX,
+ BT_Prototype7,
+ BT_Reserved,
+ BT_Reserved2,
+ BT_MNT_VA2000,
+ BT_MNT_ZZ9000,
+ BT_MaxBoardTypes
+} BTYPE;
+
+/************************************************************************/
+/* Types for PaletteChipType Identification
+ */
+typedef enum {
+ PCT_Unknown,
+ PCT_S11483, // Sierra S11483: HiColor 15 bit, oMniBus, Domino
+ PCT_S15025, // Sierra S15025: TrueColor 32 bit, oMniBus
+ PCT_CirrusGD542x, // Cirrus GD542x internal: TrueColor 24 bit
+ PCT_Domino, // is in fact a Sierra S11483
+ PCT_BT482, // BrookTree BT482: TrueColor 32 bit, Merlin
+ PCT_Music, // Music MU9C4910: TrueColor 24 bit, oMniBus
+ PCT_ICS5300, // ICS 5300: ...., Retina BLT Z3
+ PCT_CirrusGD5446, // Cirrus GD5446 internal: TrueColor 24 bit
+ PCT_CirrusGD5434, // Cirrus GD5434 internal: TrueColor 32 bit
+ PCT_S3Trio64, // S3 Trio64 internal: TrueColor 32 bit
+ PCT_A2410_xxx, // A2410 DAC, *type unknown*
+ PCT_S3ViRGE, // S3 ViRGE internal: TrueColor 32 bit
+ PCT_3dfxVoodoo, // 3dfx Voodoo internal
+ PCT_TIPermedia2, // TexasInstruments TVP4020 Permedia2 internal
+ PCT_ATIRV100, // ATI Technologies Radeon/Radeon 7000 internal
+ PCT_reserved,
+ PCT_reserved2,
+ PCT_MNT_VA2000,
+ PCT_MNT_ZZ9000,
+ PCT_MaxPaletteChipTypes
+} PCTYPE;
+
+/************************************************************************/
+/* Types for GraphicsControllerType Identification
+ */
+typedef enum {
+ GCT_Unknown,
+ GCT_ET4000,
+ GCT_ETW32,
+ GCT_CirrusGD542x,
+ GCT_NCR77C32BLT,
+ GCT_CirrusGD5446,
+ GCT_CirrusGD5434,
+ GCT_S3Trio64,
+ GCT_TI34010,
+ GCT_S3ViRGE,
+ GCT_3dfxVoodoo,
+ GCT_TIPermedia2,
+ GCT_ATIRV100,
+ GCT_reserved,
+ GCT_reserved2,
+ GCT_MNT_VA2000,
+ GCT_MNT_ZZ9000,
+ GCT_MaxGraphicsControllerTypes
+} GCTYPE;
+
+/************************************************************************/
+
+#define RGBFF_PLANAR RGBFF_NONE
+#define RGBFF_CHUNKY RGBFF_CLUT
+
+#define RGBFB_PLANAR RGBFB_NONE
+#define RGBFB_CHUNKY RGBFB_CLUT
+
+/************************************************************************/
+
+enum{
+ DPMS_ON, /* Full operation */
+ DPMS_STANDBY, /* Optional state of minimal power reduction */
+ DPMS_SUSPEND, /* Significant reduction of power consumption */
+ DPMS_OFF /* Lowest level of power consumption */
+};
+
+/************************************************************************/
+
+struct CLUTEntry {
+ UBYTE Red;
+ UBYTE Green;
+ UBYTE Blue;
+};
+
+struct ColorIndexMapping {
+ ULONG ColorMask;
+ ULONG Colors[256];
+};
+
+/************************************************************************/
+
+struct GfxMemChunk {
+ struct MinNode Node;
+ char *Ptr;
+ ULONG Size;
+ BOOL Used;
+};
+
+/************************************************************************/
+
+struct Template {
+ APTR Memory;
+ WORD BytesPerRow;
+ UBYTE XOffset; // 0 <= XOffset <= 15
+ UBYTE DrawMode;
+ ULONG FgPen;
+ ULONG BgPen;
+};
+
+/************************************************************************/
+
+struct Pattern {
+ APTR Memory;
+ UWORD XOffset, YOffset;
+ ULONG FgPen, BgPen;
+ UBYTE Size; // Width: 16, Height: (1<<pat_Size)
+ UBYTE DrawMode;
+};
+
+/************************************************************************/
+
+struct Line {
+ WORD X, Y;
+ UWORD Length;
+ WORD dX, dY;
+ WORD sDelta, lDelta, twoSDminusLD;
+ UWORD LinePtrn;
+ UWORD PatternShift;
+ ULONG FgPen, BgPen;
+ BOOL Horizontal;
+ UBYTE DrawMode;
+ BYTE pad;
+ UWORD Xorigin, Yorigin;
+};
+
+/************************************************************************/
+
+struct BitMapExtra {
+ struct MinNode BoardNode;
+ struct BitMapExtra *HashChain;
+ APTR Match;
+ struct BitMap *BitMap;
+ struct BoardInfo *BoardInfo;
+ APTR MemChunk;
+ struct RenderInfo RenderInfo;
+ UWORD Width, Height;
+ UWORD Flags;
+ // NEW !!!
+ WORD BaseLevel, CurrentLevel;
+ struct BitMapExtra *CompanionMaster;
+};
+
+/* BitMapExtra flags */
+#define BMEF_ONBOARD 0x0001
+#define BMEF_SPECIAL 0x0002
+#define BMEF_VISIBLE 0x0800
+#define BMEF_DISPLAYABLE 0x1000
+#define BMEF_SPRITESAVED 0x2000
+#define BMEF_CHECKSPRITE 0x4000
+#define BMEF_INUSE 0x8000
+
+/************************************************************************/
+
+struct SpecialFeature {
+ struct MinNode Node;
+ struct BoardInfo *BoardInfo;
+ struct BitMap *BitMap;
+ ULONG Type;
+ APTR FeatureData;
+};
+
+enum {
+ SFT_INVALID, SFT_FLICKERFIXER, SFT_VIDEOCAPTURE, SFT_VIDEOWINDOW, SFT_MEMORYWINDOW
+};
+
+#define FA_Restore (TAG_USER+0) /* becomes visible again */
+#define FA_Onboard (TAG_USER+1)
+#define FA_Active (TAG_USER+2)
+#define FA_Left (TAG_USER+3)
+#define FA_Top (TAG_USER+4)
+#define FA_Width (TAG_USER+5)
+#define FA_Height (TAG_USER+6)
+#define FA_Format (TAG_USER+7)
+#define FA_Color (TAG_USER+8)
+#define FA_Occlusion (TAG_USER+9)
+#define FA_SourceWidth (TAG_USER+10)
+#define FA_SourceHeight (TAG_USER+11)
+#define FA_MinWidth (TAG_USER+12)
+#define FA_MinHeight (TAG_USER+13)
+#define FA_MaxWidth (TAG_USER+14)
+#define FA_MaxHeight (TAG_USER+15)
+#define FA_Interlace (TAG_USER+16)
+#define FA_PAL (TAG_USER+17)
+#define FA_BitMap (TAG_USER+18)
+#define FA_Brightness (TAG_USER+19)
+#define FA_ModeInfo (TAG_USER+20)
+#define FA_ModeFormat (TAG_USER+21)
+#define FA_Colors (TAG_USER+22)
+#define FA_Colors32 (TAG_USER+23)
+#define FA_NoMemory (TAG_USER+24)
+#define FA_RenderFunc (TAG_USER+25)
+#define FA_SaveFunc (TAG_USER+26)
+#define FA_UserData (TAG_USER+27)
+#define FA_Alignment (TAG_USER+28)
+#define FA_ConstantBytesPerRow (TAG_USER+29)
+#define FA_DoubleBuffer (TAG_USER+30)
+#define FA_Pen (TAG_USER+31)
+#define FA_ModeMemorySize (TAG_USER+32)
+#define FA_ClipLeft (TAG_USER+33)
+#define FA_ClipTop (TAG_USER+34)
+#define FA_ClipWidth (TAG_USER+35)
+#define FA_ClipHeight (TAG_USER+36)
+#define FA_ConstantByteSwapping (TAG_USER+37)
+
+/************************************************************************/
+
+/* Tags for bi->AllocBitMap() */
+
+#define ABMA_Friend (TAG_USER+0)
+#define ABMA_Depth (TAG_USER+1)
+#define ABMA_RGBFormat (TAG_USER+2)
+#define ABMA_Clear (TAG_USER+3)
+#define ABMA_Displayable (TAG_USER+4)
+#define ABMA_Visible (TAG_USER+5)
+#define ABMA_NoMemory (TAG_USER+6)
+#define ABMA_NoSprite (TAG_USER+7)
+#define ABMA_Colors (TAG_USER+8)
+#define ABMA_Colors32 (TAG_USER+9)
+#define ABMA_ModeWidth (TAG_USER+10)
+#define ABMA_ModeHeight (TAG_USER+11)
+#define ABMA_RenderFunc (TAG_USER+12)
+#define ABMA_SaveFunc (TAG_USER+13)
+#define ABMA_UserData (TAG_USER+14)
+#define ABMA_Alignment (TAG_USER+15)
+#define ABMA_ConstantBytesPerRow (TAG_USER+16)
+#define ABMA_UserPrivate (TAG_USER+17)
+#define ABMA_ConstantByteSwapping (TAG_USER+18)
+/*
+ * THOR: New for V45 Gfx/Intuiton
+ * "by accident", this is identically to SA_DisplayID of intuition
+ * resp. SA_Behind, SA_Colors, SA_Colors32
+ */
+#define ABMA_DisplayID (TAG_USER + 32 + 0x12)
+#define ABMA_BitmapInvisible (TAG_USER + 32 + 0x17)
+#define ABMA_BitmapColors (TAG_USER + 32 + 0x09)
+#define ABMA_BitmapColors32 (TAG_USER + 32 + 0x23)
+
+/************************************************************************/
+
+/* Tags for bi->GetBitMapAttr() */
+
+#define GBMA_MEMORY (TAG_USER+0)
+#define GBMA_BASEMEMORY (TAG_USER+1)
+#define GBMA_BYTESPERROW (TAG_USER+2)
+#define GBMA_BYTESPERPIXEL (TAG_USER+3)
+#define GBMA_BITSPERPIXEL (TAG_USER+4)
+#define GBMA_RGBFORMAT (TAG_USER+6)
+#define GBMA_WIDTH (TAG_USER+7)
+#define GBMA_HEIGHT (TAG_USER+8)
+#define GBMA_DEPTH (TAG_USER+9)
+
+/************************************************************************/
+
+struct BoardInfo{
+ UBYTE *RegisterBase, *MemoryBase, *MemoryIOBase;
+ ULONG MemorySize;
+ char *BoardName,VBIName[32];
+ struct CardBase *CardBase;
+ struct ChipBase *ChipBase;
+ struct ExecBase *ExecBase;
+ struct Library *UtilBase;
+ struct Interrupt HardInterrupt;
+ struct Interrupt SoftInterrupt;
+ struct SignalSemaphore BoardLock;
+ struct MinList ResolutionsList;
+ BTYPE BoardType;
+ PCTYPE PaletteChipType;
+ GCTYPE GraphicsControllerType;
+ UWORD MoniSwitch;
+ UWORD BitsPerCannon;
+ ULONG Flags;
+ UWORD SoftSpriteFlags;
+ UWORD ChipFlags; // private, chip specific, not touched by RTG
+ ULONG CardFlags; // private, card specific, not touched by RTG
+
+ UWORD BoardNum; // set by rtg.library
+ UWORD RGBFormats;
+
+ UWORD MaxHorValue[MAXMODES];
+ UWORD MaxVerValue[MAXMODES];
+ UWORD MaxHorResolution[MAXMODES];
+ UWORD MaxVerResolution[MAXMODES];
+ ULONG MaxMemorySize, MaxChunkSize;
+
+ ULONG MemoryClock;
+
+ ULONG PixelClockCount[MAXMODES];
+
+ APTR ASM (*AllocCardMem)(__REGA0(struct BoardInfo *bi), __REGD0(ULONG size), __REGD1(BOOL force), __REGD2(BOOL system));
+ BOOL ASM (*FreeCardMem)(__REGA0(struct BoardInfo *bi), __REGA1(APTR membase));
+
+ BOOL ASM (*SetSwitch)(__REGA0(struct BoardInfo *), __REGD0(BOOL));
+
+ void ASM (*SetColorArray)(__REGA0(struct BoardInfo *), __REGD0(UWORD), __REGD1(UWORD));
+
+ void ASM (*SetDAC)(__REGA0(struct BoardInfo *), __REGD7(RGBFTYPE));
+ void ASM (*SetGC)(__REGA0(struct BoardInfo *), __REGA1(struct ModeInfo *), __REGD0(BOOL));
+ void ASM (*SetPanning)(__REGA0(struct BoardInfo *), __REGA1(UBYTE *), __REGD0(UWORD), __REGD1(WORD), __REGD2(WORD), __REGD7(RGBFTYPE));
+ UWORD ASM (*CalculateBytesPerRow)(__REGA0(struct BoardInfo *), __REGD0(UWORD), __REGD7(RGBFTYPE));
+ APTR ASM (*CalculateMemory)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD7(RGBFTYPE));
+ ULONG ASM (*GetCompatibleFormats)(__REGA0(struct BoardInfo *), __REGD7(RGBFTYPE));
+ BOOL ASM (*SetDisplay)(__REGA0(struct BoardInfo *), __REGD0(BOOL));
+
+ LONG ASM (*ResolvePixelClock)(__REGA0(struct BoardInfo *), __REGA1(struct ModeInfo *), __REGD0(ULONG), __REGD7(RGBFTYPE));
+ ULONG ASM (*GetPixelClock)(__REGA0(struct BoardInfo *bi), __REGA1(struct ModeInfo *), __REGD0(ULONG), __REGD7(RGBFTYPE));
+ void ASM (*SetClock)(__REGA0(struct BoardInfo *));
+
+ void ASM (*SetMemoryMode)(__REGA0(struct BoardInfo *), __REGD7(RGBFTYPE));
+ void ASM (*SetWriteMask)(__REGA0(struct BoardInfo *), __REGD0(UBYTE));
+ void ASM (*SetClearMask)(__REGA0(struct BoardInfo *), __REGD0(UBYTE));
+ void ASM (*SetReadPlane)(__REGA0(struct BoardInfo *), __REGD0(UBYTE));
+
+ void ASM (*WaitVerticalSync)(__REGA0(struct BoardInfo *), __REGD0(BOOL));
+ BOOL ASM (*SetInterrupt)(__REGA0(struct BoardInfo *), __REGD0(BOOL));
+
+ void ASM (*WaitBlitter)(__REGA0(struct BoardInfo *));
+
+ void ASM (*ScrollPlanar)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(UWORD), __REGD1(UWORD), __REGD2(UWORD), __REGD3(UWORD), __REGD4(UWORD), __REGD5(UWORD), __REGD6(UBYTE));
+ void ASM (*ScrollPlanarDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(UWORD), __REGD1(UWORD), __REGD2(UWORD), __REGD3(UWORD), __REGD4(UWORD), __REGD5(UWORD), __REGD6(UBYTE));
+ void ASM (*UpdatePlanar)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(UBYTE));
+ void ASM (*UpdatePlanarDefault)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(UBYTE));
+ void ASM (*BlitPlanar2Chunky)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGD6(UBYTE), __REGD7(UBYTE));
+ void ASM (*BlitPlanar2ChunkyDefault)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGD6(UBYTE), __REGD7(UBYTE));
+
+ void ASM (*FillRect)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(ULONG), __REGD5(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*FillRectDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(ULONG), __REGD5(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*InvertRect)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*InvertRectDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitRect)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(WORD), __REGD5(WORD), __REGD6(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitRectDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(WORD), __REGD5(WORD), __REGD6(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitTemplate)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Template *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitTemplateDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Template *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitPattern)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Pattern *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitPatternDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Pattern *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*DrawLine)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Line *), __REGD0(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*DrawLineDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct Line *), __REGD0(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitRectNoMaskComplete)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(WORD), __REGD5(WORD), __REGD6(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitRectNoMaskCompleteDefault)(__REGA0(struct BoardInfo *), __REGA1(struct RenderInfo *), __REGA2(struct RenderInfo *), __REGD0(WORD), __REGD1(WORD), __REGD2(WORD), __REGD3(WORD), __REGD4(WORD), __REGD5(WORD), __REGD6(UBYTE), __REGD7(RGBFTYPE));
+ void ASM (*BlitPlanar2Direct)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGA3(struct ColorIndexMapping *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGD6(UBYTE), __REGD7(UBYTE));
+ void ASM (*BlitPlanar2DirectDefault)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct RenderInfo *), __REGA3(struct ColorIndexMapping *), __REGD0(SHORT), __REGD1(SHORT), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGD6(UBYTE), __REGD7(UBYTE));
+ BOOL ASM (*EnableSoftSprite)(__REGA0(struct BoardInfo *),__REGD0(ULONG formatflags),__REGA1(struct ModeInfo *));
+ BOOL ASM (*EnableSoftSpriteDefault)(__REGA0(struct BoardInfo *),__REGD0(ULONG formatflags),__REGA1(struct ModeInfo *));
+ APTR ASM (*AllocCardMemAbs)(__REGA0(struct BoardInfo *),__REGD0(ULONG size), __REGA1(char *target));
+ void ASM (*SetSplitPosition)(__REGA0(struct BoardInfo *),__REGD0(SHORT));
+ void ASM (*ReInitMemory)(__REGA0(struct BoardInfo *),__REGD0(RGBFTYPE));
+ void ASM (*Reserved2Default)(__REGA0(struct BoardInfo *));
+ void ASM (*Reserved3)(__REGA0(struct BoardInfo *));
+ void ASM (*Reserved3Default)(__REGA0(struct BoardInfo *));
+
+ int ASM (*WriteYUVRect)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD0(SHORT), __REGD1(SHORT), __REGA2(struct RenderInfo *), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGA3(struct TagItem *));
+ int ASM (*WriteYUVRectDefault)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD0(SHORT), __REGD1(SHORT), __REGA2(struct RenderInfo *), __REGD2(SHORT), __REGD3(SHORT), __REGD4(SHORT), __REGD5(SHORT), __REGA3(struct TagItem *));
+
+ BOOL ASM (*GetVSyncState)(__REGA0(struct BoardInfo *), __REGD0(BOOL));
+ ULONG ASM (*GetVBeamPos)(__REGA0(struct BoardInfo *));
+ void ASM (*SetDPMSLevel)(__REGA0(struct BoardInfo *), __REGD0(ULONG));
+ void ASM (*ResetChip)(__REGA0(struct BoardInfo *));
+ ULONG ASM (*GetFeatureAttrs)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD0(ULONG), __REGA2(struct TagItem *));
+
+ struct BitMap * ASM (*AllocBitMap)(__REGA0(struct BoardInfo *), __REGD0(ULONG), __REGD1(ULONG), __REGA1(struct TagItem *));
+ BOOL ASM (*FreeBitMap)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGA2(struct TagItem *));
+ ULONG ASM (*GetBitMapAttr)(__REGA0(struct BoardInfo *), __REGA1(struct BitMap *), __REGD0(ULONG));
+
+ BOOL ASM (*SetSprite)(__REGA0(struct BoardInfo *), __REGD0(BOOL), __REGD7(RGBFTYPE));
+ void ASM (*SetSpritePosition)(__REGA0(struct BoardInfo *), __REGD0(WORD), __REGD1(WORD), __REGD7(RGBFTYPE));
+ void ASM (*SetSpriteImage)(__REGA0(struct BoardInfo *), __REGD7(RGBFTYPE));
+ void ASM (*SetSpriteColor)(__REGA0(struct BoardInfo *), __REGD0(UBYTE), __REGD1(UBYTE), __REGD2(UBYTE), __REGD3(UBYTE), __REGD7(RGBFTYPE));
+
+ APTR ASM (*CreateFeature)(__REGA0(struct BoardInfo *), __REGD0(ULONG), __REGA1(struct TagItem *));
+ ULONG ASM (*SetFeatureAttrs)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD0(ULONG), __REGA2(struct TagItem *));
+ BOOL ASM (*DeleteFeature)(__REGA0(struct BoardInfo *), __REGA1(APTR), __REGD0(ULONG));
+ struct MinList SpecialFeatures;
+
+ struct ModeInfo *ModeInfo; /* Chip Settings Stuff */
+ RGBFTYPE RGBFormat;
+ WORD XOffset;
+ WORD YOffset;
+ UBYTE Depth;
+ UBYTE ClearMask;
+ BOOL Border;
+ ULONG Mask;
+ struct CLUTEntry CLUT[256];
+
+ struct ViewPort *ViewPort; /* ViewPort Stuff */
+ struct BitMap *VisibleBitMap;
+ struct BitMapExtra *BitMapExtra;
+ struct MinList BitMapList;
+ struct MinList MemList;
+
+ WORD MouseX;
+ WORD MouseY; /* Sprite Stuff */
+ UBYTE MouseWidth;
+ UBYTE MouseHeight;
+ UBYTE MouseXOffset;
+ UBYTE MouseYOffset;
+ UWORD *MouseImage;
+ UBYTE MousePens[4];
+ struct Rectangle MouseRect;
+ UBYTE *MouseChunky;
+ UWORD *MouseRendered;
+ UBYTE *MouseSaveBuffer;
+
+ ULONG ChipData[16]; /* for chip driver needs */
+ ULONG CardData[16]; /* for card driver needs */
+
+ APTR MemorySpaceBase; /* the base address of the board memory address space */
+ ULONG MemorySpaceSize; /* size of that area */
+
+ APTR DoubleBufferList; /* chain of dbinfos being notified on vblanks */
+
+ struct timeval SyncTime; /* system time when screen was set up, used for pseudo vblanks */
+ ULONG SyncPeriod; /* length of one frame in micros */
+ struct MsgPort SoftVBlankPort; /* MsgPort for software emulation of board interrupt */
+
+ struct MinList WaitQ; /* for WaitTOF and WaitBOVP, all elements will be signaled on VBlank */
+
+ LONG EssentialFormats; /* these RGBFormats will be used when user does not choose "all"
+ will be filled by InitBoard() */
+ UBYTE *MouseImageBuffer; /* rendered to the destination color format */
+ /* Additional viewport stuff */
+ struct ViewPort *backViewPort; /* The view port visible on the screen behind */
+ struct BitMap *backBitMap; /* Its bitmap */
+ struct BitMapExtra *backExtra; /* its bitmapExtra */
+ WORD YSplit;
+ ULONG MaxPlanarMemory; /* Size of a bitplane if planar. If left blank, MemorySize>>2 */
+ ULONG MaxBMWidth; /* Maximum width of a bitmap */
+ ULONG MaxBMHeight; /* Maximum height of a bitmap */
+};
+
+/* BoardInfo flags */
+/* 0-15: hardware flags */
+/* 16-31: user flags */
+#define BIB_HARDWARESPRITE 0 /* board has hardware sprite */
+#define BIB_NOMEMORYMODEMIX 1 /* board does not support modifying planar bitmaps while displaying chunky and vice versa */
+#define BIB_NEEDSALIGNMENT 2 /* bitmaps have to be aligned (not yet supported!) */
+#define BIB_CACHEMODECHANGE 3 /* board memory may be set to Imprecise (060) or Nonserialised (040) */
+#define BIB_VBLANKINTERRUPT 4 /* board can cause a hardware interrupt on a vertical retrace */
+#define BIB_HASSPRITEBUFFER 5 /* board has allocated memory for software sprite image and save buffer */
+
+#define BIB_VGASCREENSPLIT 6 /* has a screen B with fixed screen position for split-screens */
+
+#define BIB_DBLSCANDBLSPRITEY 8 /* hardware sprite y position is doubled on doublescan display modes */
+#define BIB_ILACEHALFSPRITEY 9 /* hardware sprite y position is halved on interlace display modes */
+#define BIB_ILACEDBLROWOFFSET 10 /* doubled row offset in interlaced display modes needs additional horizontal bit */
+#define BIB_INTERNALMODESONLY 11 /* board creates its resolutions and modes automatically and does not support user setting files (UAE) */
+#define BIB_FLICKERFIXER 12 /* board can flicker fix Amiga RGB signal */
+#define BIB_VIDEOCAPTURE 13 /* board can capture video data to a memory area */
+#define BIB_VIDEOWINDOW 14 /* board can display a second mem area as a pip */
+#define BIB_BLITTER 15 /* board has blitter */
+
+#define BIB_HIRESSPRITE 16 /* mouse sprite has double resolution */
+#define BIB_BIGSPRITE 17 /* user wants big mouse sprite */
+#define BIB_BORDEROVERRIDE 18 /* user wants to override system overscan border prefs */
+#define BIB_BORDERBLANK 19 /* user wants border blanking */
+#define BIB_INDISPLAYCHAIN 20 /* board switches Amiga signal */
+#define BIB_QUIET 21 /* not yet implemented */
+#define BIB_NOMASKBLITS 22 /* perform blits without taking care of mask */
+#define BIB_NOP2CBLITS 23 /* use CPU for planar to chunky conversions */
+#define BIB_NOBLITTER 24 /* disable all blitter functions */
+#define BIB_SYSTEM2SCREENBLITS 25 /* allow data to be written to screen memory for cpu as blitter source */
+#define BIB_GRANTDIRECTACCESS 26 /* all data on the board can be accessed at any time without bi->SetMemoryMode() */
+
+#define BIB_OVERCLOCK 31 /* enable overclocking for some boards */
+
+#define BIB_IGNOREMASK BIB_NOMASKBLITS
+
+#define BIF_HARDWARESPRITE (1<<BIB_HARDWARESPRITE)
+#define BIF_NOMEMORYMODEMIX (1<<BIB_NOMEMORYMODEMIX)
+#define BIF_NEEDSALIGNMENT (1<<BIB_NEEDSALIGNMENT)
+#define BIF_CACHEMODECHANGE (1<<BIB_CACHEMODECHANGE)
+#define BIF_VBLANKINTERRUPT (1<<BIB_VBLANKINTERRUPT)
+#define BIF_HASSPRITEBUFFER (1<<BIB_HASSPRITEBUFFER)
+#define BIF_VGASCREENSPLIT (1<<BIB_VGASCREENSPLIT)
+#define BIF_DBLSCANDBLSPRITEY (1<<BIB_DBLSCANDBLSPRITEY)
+#define BIF_ILACEHALFSPRITEY (1<<BIB_ILACEHALFSPRITEY)
+#define BIF_ILACEDBLROWOFFSET (1<<BIB_ILACEDBLROWOFFSET)
+#define BIF_INTERNALMODESONLY (1<<BIB_INTERNALMODESONLY)
+#define BIF_FLICKERFIXER (1<<BIB_FLICKERFIXER)
+#define BIF_VIDEOCAPTURE (1<<BIB_VIDEOCAPTURE)
+#define BIF_VIDEOWINDOW (1<<BIB_VIDEOWINDOW)
+#define BIF_BLITTER (1<<BIB_BLITTER)
+#define BIF_HIRESSPRITE (1<<BIB_HIRESSPRITE)
+#define BIF_BIGSPRITE (1<<BIB_BIGSPRITE)
+#define BIF_BORDEROVERRIDE (1<<BIB_BORDEROVERRIDE)
+#define BIF_BORDERBLANK (1<<BIB_BORDERBLANK)
+#define BIF_INDISPLAYCHAIN (1<<BIB_INDISPLAYCHAIN)
+#define BIF_QUIET (1<<BIB_QUIET)
+#define BIF_NOMASKBLITS (1<<BIB_NOMASKBLITS)
+#define BIF_NOP2CBLITS (1<<BIB_NOP2CBLITS)
+#define BIF_NOBLITTER (1<<BIB_NOBLITTER)
+#define BIF_SYSTEM2SCREENBLITS (1<<BIB_SYSTEM2SCREENBLITS)
+#define BIF_GRANTDIRECTACCESS (1<<BIB_GRANTDIRECTACCESS)
+#define BIF_OVERCLOCK (1<<BIB_OVERCLOCK)
+
+#define BIF_IGNOREMASK BIF_NOMASKBLITS
+
+/* write errors, continued for historical reasons... :-) */
+#define BIB_NOC2PBLITS BIB_NOP2CBLITS
+#define BIF_NOC2PBLITS BIF_NOP2CBLITS
+
+/************************************************************************/
+
+struct CardBase {
+ struct Library LibBase;
+ UBYTE Flags;
+ UBYTE pad;
+
+ struct ExecBase *ExecBase;
+ struct Library *ExpansionBase;
+
+ APTR SegList;
+ char *Name;
+};
+
+struct ChipBase {
+ struct Library LibBase;
+ UBYTE Flags;
+ UBYTE pad;
+
+ struct ExecBase *ExecBase;
+
+ APTR SegList;
+};
+
+/************************************************************************/
+/* private Tags */
+#define P96BD_BoardType (P96BD_Dummy+0x101)
+#define P96BD_ChipType (P96BD_Dummy+0x102)
+#define P96BD_DACType (P96BD_Dummy+0x103)
+#define P96BD_CurrentScreenBitMap (P96BD_Dummy+0x104)
+
+/************************************************************************/
+#endif
--- /dev/null
+vc +aos68k -nostdlib -I$VBCC/targets/m68k-amigaos/include2 -c99 -O2 -o pigfx020.card pigfx.c -ldebug -lamiga -cpu=68020
+vc +aos68k -nostdlib -I$VBCC/targets/m68k-amigaos/include2 -c99 -O2 -o pigfx030.card pigfx.c -ldebug -lamiga -cpu=68030
--- /dev/null
+vc +aos68k -nostdlib -I$VBCC/targets/m68k-amigaos/include2 -c99 -O2 -o pigfx020.card pigfx.c -ldebug -lamiga -cpu=68020
+vc +aos68k -nostdlib -I$VBCC/targets/m68k-amigaos/include2 -c99 -O2 -o pigfx030.card pigfx.c -ldebug -lamiga -cpu=68030
--- /dev/null
+// PiStorm RTG driver, VBCC edition.
+// Based in part on the ZZ9000 RTG driver.
+
+#include <proto/exec.h>
+#include <proto/expansion.h>
+#include <proto/dos.h>
+#include <proto/intuition.h>
+#include <exec/types.h>
+#include <exec/memory.h>
+#include <exec/libraries.h>
+#include <exec/execbase.h>
+#include <exec/resident.h>
+#include <exec/initializers.h>
+#include <clib/debug_protos.h>
+#include <string.h>
+#include <stdint.h>
+#include "boardinfo.h"
+#include "rtg_enums.h"
+
+#define WRITESHORT(cmd, val) *(unsigned short *)((unsigned long)(b->RegisterBase)+cmd) = val;
+#define WRITELONG(cmd, val) *(unsigned long *)((unsigned long)(b->RegisterBase)+cmd) = val;
+#define WRITEBYTE(cmd, val) *(unsigned char *)((unsigned long)(b->RegisterBase)+cmd) = val;
+
+#define CHECKRTG *((unsigned short *)(CARD_OFFSET))
+
+#define CARD_OFFSET 0x70000000
+#define CARD_REGSIZE 0x00010000
+#define CARD_MEMSIZE 0x02000000 // 32MB "VRAM"
+#define CARD_SCRATCH 0x72010000
+
+#define CHIP_RAM_SIZE 0x00200000 // Chip RAM offset, 2MB
+
+const unsigned short rgbf_to_rtg[16] = {
+ RTGFMT_8BIT, // 0x00
+ RTGFMT_8BIT, // 0x01
+ 0, // 0x02
+ 0, // 0x03
+ 0, // 0x04
+ RTGFMT_RGB555, // 0x05
+ 0, // 0x06
+ 0, // 0x07
+ RTGFMT_RGB32, // 0x08
+ RTGFMT_RGB32, // 0x09
+ RTGFMT_RBG565, // 0x0A
+ RTGFMT_RGB555, // 0x0B
+ 0, // 0x0C
+ RTGFMT_RGB555, // 0x0D
+ 0, // 0x0E
+ 0, // 0x0F
+};
+
+struct GFXBase {
+ struct Library libNode;
+ BPTR segList;
+ struct ExecBase* sysBase;
+ struct ExpansionBase* expansionBase;
+};
+
+int FindCard(__REGA0(struct BoardInfo* b));
+int InitCard(__REGA0(struct BoardInfo* b));
+
+void SetDAC (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format));
+void SetGC (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(BOOL border));
+void SetColorArray (__REGA0(struct BoardInfo *b), __REGD0(UWORD start), __REGD1(UWORD num));
+void SetPanning (__REGA0(struct BoardInfo *b), __REGA1(UBYTE *addr), __REGD0(UWORD width), __REGD1(WORD x_offset), __REGD2(WORD y_offset), __REGD7(RGBFTYPE format));
+UWORD SetSwitch (__REGA0(struct BoardInfo *b), __REGD0(UWORD enabled));
+UWORD SetDisplay (__REGA0(struct BoardInfo *b), __REGD0(UWORD enabled));
+
+UWORD CalculateBytesPerRow (__REGA0(struct BoardInfo *b), __REGD0(UWORD width), __REGD7(RGBFTYPE format));
+APTR CalculateMemory (__REGA0(struct BoardInfo *b), __REGA1(unsigned long addr), __REGD7(RGBFTYPE format));
+ULONG GetCompatibleFormats (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format));
+
+LONG ResolvePixelClock (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(ULONG pixel_clock), __REGD7(RGBFTYPE format));
+ULONG GetPixelClock (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(ULONG index), __REGD7(RGBFTYPE format));
+void SetClock (__REGA0(struct BoardInfo *b));
+
+void SetMemoryMode (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format));
+void SetWriteMask (__REGA0(struct BoardInfo *b), __REGD0(UBYTE mask));
+void SetClearMask (__REGA0(struct BoardInfo *b), __REGD0(UBYTE mask));
+void SetReadPlane (__REGA0(struct BoardInfo *b), __REGD0(UBYTE plane));
+
+void WaitVerticalSync (__REGA0(struct BoardInfo *b), __REGD0(BOOL toggle));
+
+void FillRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(ULONG color), __REGD5(UBYTE mask), __REGD7(RGBFTYPE format));
+void InvertRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format));
+void BlitRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD dx), __REGD3(WORD dy), __REGD4(WORD w), __REGD5(WORD h), __REGD6(UBYTE mask), __REGD7(RGBFTYPE format));
+void BlitRectNoMaskComplete (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *rs), __REGA2(struct RenderInfo *rt), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD dx), __REGD3(WORD dy), __REGD4(WORD w), __REGD5(WORD h), __REGD6(UBYTE minterm), __REGD7(RGBFTYPE format));
+void BlitTemplate (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Template *t), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format));
+void BlitPattern (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Pattern *p), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format));
+void DrawLine (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Line *l), __REGD0(UBYTE mask), __REGD7(RGBFTYPE format));
+
+void BlitPlanar2Chunky (__REGA0(struct BoardInfo *b), __REGA1(struct BitMap *bm), __REGA2(struct RenderInfo *r), __REGD0(SHORT x), __REGD1(SHORT y), __REGD2(SHORT dx), __REGD3(SHORT dy), __REGD4(SHORT w), __REGD5(SHORT h), __REGD6(UBYTE minterm), __REGD7(UBYTE mask));
+void BlitPlanar2Direct (__REGA0(struct BoardInfo *b), __REGA1(struct BitMap *bmp), __REGA2(struct RenderInfo *r), __REGA3(struct ColorIndexMapping *clut), __REGD0(SHORT x), __REGD1(SHORT y), __REGD2(SHORT dx), __REGD3(SHORT dy), __REGD4(SHORT w), __REGD5(SHORT h), __REGD6(UBYTE minterm), __REGD7(UBYTE mask));
+
+static ULONG LibStart(void) {
+ return(-1);
+}
+
+static const char LibraryName[] = "PiRTG.card";
+static const char LibraryID[] = "$VER: PiRTG.card 0.01\r\n";
+
+__saveds struct GFXBase* OpenLib(__REGA6(struct GFXBase *gfxbase));
+BPTR __saveds CloseLib(__REGA6(struct GFXBase *gfxbase));
+BPTR __saveds ExpungeLib(__REGA6(struct GFXBase *exb));
+ULONG ExtFuncLib(void);
+__saveds struct GFXBase* InitLib(__REGA6(struct ExecBase *sysbase),
+ __REGA0(BPTR seglist),
+ __REGD0(struct GFXBase *exb));
+
+static const APTR FuncTab[] = {
+ (APTR)OpenLib,
+ (APTR)CloseLib,
+ (APTR)ExpungeLib,
+ (APTR)ExtFuncLib,
+
+ (APTR)FindCard,
+ (APTR)InitCard,
+ (APTR)((LONG)-1)
+};
+
+struct InitTable
+{
+ ULONG LibBaseSize;
+ APTR FunctionTable;
+ APTR DataTable;
+ APTR InitLibTable;
+};
+
+static struct InitTable InitTab = {
+ (ULONG) sizeof(struct GFXBase),
+ (APTR) FuncTab,
+ (APTR) NULL,
+ (APTR) InitLib
+};
+
+static const struct Resident ROMTag = {
+ RTC_MATCHWORD,
+ &ROMTag,
+ &ROMTag + 1,
+ RTF_AUTOINIT,
+ 83,
+ NT_LIBRARY,
+ 0,
+ (char *)LibraryName,
+ (char *)LibraryID,
+ (APTR)&InitTab
+};
+
+#define CLOCK_HZ 100000000
+
+static struct GFXBase *_gfxbase;
+const char *gfxname = "PiStorm RTG";
+char dummies[128];
+
+__saveds struct GFXBase* InitLib(__REGA6(struct ExecBase *sysbase),
+ __REGA0(BPTR seglist),
+ __REGD0(struct GFXBase *exb))
+{
+ _gfxbase = exb;
+ return _gfxbase;
+}
+
+__saveds struct GFXBase* OpenLib(__REGA6(struct GFXBase *gfxbase))
+{
+ gfxbase->libNode.lib_OpenCnt++;
+ gfxbase->libNode.lib_Flags &= ~LIBF_DELEXP;
+
+ return gfxbase;
+}
+
+BPTR __saveds CloseLib(__REGA6(struct GFXBase *gfxbase))
+{
+ gfxbase->libNode.lib_OpenCnt--;
+
+ if (!gfxbase->libNode.lib_OpenCnt) {
+ if (gfxbase->libNode.lib_Flags & LIBF_DELEXP) {
+ return (ExpungeLib(gfxbase));
+ }
+ }
+ return 0;
+}
+
+BPTR __saveds ExpungeLib(__REGA6(struct GFXBase *exb))
+{
+ BPTR seglist;
+ struct ExecBase *SysBase = *(struct ExecBase **)4L;
+
+ if(!exb->libNode.lib_OpenCnt) {
+ ULONG negsize, possize, fullsize;
+ UBYTE *negptr = (UBYTE *)exb;
+
+ seglist = exb->segList;
+
+ Remove((struct Node *)exb);
+
+ negsize = exb->libNode.lib_NegSize;
+ possize = exb->libNode.lib_PosSize;
+ fullsize = negsize + possize;
+ negptr -= negsize;
+
+ FreeMem(negptr, fullsize);
+ return(seglist);
+ }
+
+ exb->libNode.lib_Flags |= LIBF_DELEXP;
+ return 0;
+}
+
+ULONG ExtFuncLib(void)
+{
+ return 0;
+}
+
+static LONG zorro_version = 0;
+
+static struct GFXData *gfxdata;
+//MNTZZ9KRegs* registers;
+
+#define LOADLIB(a, b) if ((a = (struct a*)OpenLibrary(b,0L))==NULL) { \
+ KPrintF("Failed to load %s.\n", b); \
+ return 0; \
+ } \
+
+static BYTE card_already_found;
+static BYTE card_initialized;
+
+int FindCard(__REGA0(struct BoardInfo* b)) {
+ //if (card_already_found)
+// return 1;
+ uint16_t card_check = CHECKRTG;
+ if (card_check != 0xFFCF) {
+ // RTG not enabled
+ return 0;
+ }
+
+ struct ConfigDev* cd = NULL;
+ struct ExpansionBase *ExpansionBase = NULL;
+ struct DOSBase *DOSBase = NULL;
+ struct IntuitionBase *IntuitionBase = NULL;
+ struct ExecBase *SysBase = *(struct ExecBase **)4L;
+
+ LOADLIB(ExpansionBase, "expansion.library");
+ LOADLIB(DOSBase, "dos.library");
+ LOADLIB(IntuitionBase, "intuition.library");
+
+ b->MemorySize = CARD_MEMSIZE;
+ b->RegisterBase = (void *)CARD_OFFSET;
+ b->MemoryBase = (void *)(CARD_OFFSET + CARD_REGSIZE);
+
+ return 1;
+}
+
+#define HWSPRITE 1
+#define VGASPLIT (1 << 6)
+#define FLICKERFIXER (1 << 12)
+#define INDISPLAYCHAIN (1 << 20)
+#define DIRECTACCESS (1 << 26)
+
+int InitCard(__REGA0(struct BoardInfo* b)) {
+ //if (!card_initialized)
+// card_initialized = 1;
+// else
+ //return 1;
+
+ int max, i;
+ struct ExecBase *SysBase = *(struct ExecBase **)4L;
+
+ b->CardBase = (struct CardBase *)_gfxbase;
+ b->ExecBase = SysBase;
+ b->BoardName = "PiStorm RTG";
+ b->BoardType = BT_MNT_ZZ9000;
+ b->PaletteChipType = PCT_MNT_ZZ9000;
+ b->GraphicsControllerType = GCT_MNT_ZZ9000;
+
+ b->Flags = BIF_INDISPLAYCHAIN | BIF_GRANTDIRECTACCESS;
+ b->RGBFormats = 1 | 2 | 512 | 1024 | 2048;
+ b->SoftSpriteFlags = 0;
+ b->BitsPerCannon = 8;
+
+ for(i = 0; i < MAXMODES; i++) {
+ b->MaxHorValue[i] = 1920;
+ b->MaxVerValue[i] = 1080;
+ b->MaxHorResolution[i] = 1920;
+ b->MaxVerResolution[i] = 1080;
+ b->PixelClockCount[i] = 1;
+ }
+
+ b->MemoryClock = CLOCK_HZ;
+
+ //b->AllocCardMem = (void *)NULL;
+ //b->FreeCardMem = (void *)NULL;
+ b->SetSwitch = (void *)SetSwitch;
+ b->SetColorArray = (void *)SetColorArray;
+ b->SetDAC = (void *)SetDAC;
+ b->SetGC = (void *)SetGC;
+ b->SetPanning = (void *)SetPanning;
+ b->CalculateBytesPerRow = (void *)CalculateBytesPerRow;
+ b->CalculateMemory = (void *)CalculateMemory;
+ b->GetCompatibleFormats = (void *)GetCompatibleFormats;
+ b->SetDisplay = (void *)SetDisplay;
+
+ b->ResolvePixelClock = (void *)ResolvePixelClock;
+ b->GetPixelClock = (void *)GetPixelClock;
+ b->SetClock = (void *)SetClock;
+
+ b->SetMemoryMode = (void *)SetMemoryMode;
+ b->SetWriteMask = (void *)SetWriteMask;
+ b->SetClearMask = (void *)SetClearMask;
+ b->SetReadPlane = (void *)SetReadPlane;
+
+ b->WaitVerticalSync = (void *)WaitVerticalSync;
+ //b->SetInterrupt = (void *)NULL;
+
+ //b->WaitBlitter = (void *)NULL;
+
+ //b->ScrollPlanar = (void *)NULL;
+ //b->UpdatePlanar = (void *)NULL;
+
+ //b->BlitPlanar2Chunky = (void *)BlitPlanar2Chunky;
+ //b->BlitPlanar2Direct = (void *)NULL;
+
+ b->FillRect = (void *)FillRect;
+ b->InvertRect = (void *)InvertRect;
+ b->BlitRect = (void *)BlitRect;
+ b->BlitTemplate = (void *)BlitTemplate;
+ b->BlitPattern = (void *)BlitPattern;
+ b->DrawLine = (void *)DrawLine;
+ b->BlitRectNoMaskComplete = (void *)BlitRectNoMaskComplete;
+ //b->EnableSoftSprite = (void *)NULL;
+
+ //b->AllocCardMemAbs = (void *)NULL;
+ //b->SetSplitPosition = (void *)NULL;
+ //b->ReInitMemory = (void *)NULL;
+ //b->WriteYUVRect = (void *)NULL;
+ //b->GetVSyncState = (void *)NULL;
+ //b->GetVBeamPos = (void *)NULL;
+ //b->SetDPMSLevel = (void *)NULL;
+ //b->ResetChip = (void *)NULL;
+ //b->GetFeatureAttrs = (void *)NULL;
+ //b->AllocBitMap = (void *)NULL;
+ //b->FreeBitMap = (void *)NULL;
+ //b->GetBitMapAttr = (void *)NULL;
+
+ //b->SetSprite = (void *)NULL;
+ //b->SetSpritePosition = (void *)NULL;
+ //b->SetSpriteImage = (void *)NULL;
+ //b->SetSpriteColor = (void *)NULL;
+
+ //b->CreateFeature = (void *)NULL;
+ //b->SetFeatureAttrs = (void *)NULL;
+ //b->DeleteFeature = (void *)NULL;
+
+ return 1;
+}
+
+void SetDAC (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format)) {
+ // Used to set the color format of the video card's RAMDAC.
+ // This needs no handling, since the PiStorm doesn't really have a RAMDAC or a video card chipset.
+}
+
+void SetGC (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(BOOL border)) {
+ b->ModeInfo = mode_info;
+ // Send width, height and format to the RaspberryPi Targetable Graphics.
+ WRITESHORT(RTG_X1, mode_info->Width);
+ WRITESHORT(RTG_Y1, mode_info->Height);
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[b->RGBFormat]);
+ WRITESHORT(RTG_COMMAND, RTGCMD_SETGC);
+}
+
+int setswitch = -1;
+UWORD SetSwitch (__REGA0(struct BoardInfo *b), __REGD0(UWORD enabled)) {
+ if (setswitch != enabled) {
+ setswitch = enabled;
+ }
+
+ WRITEBYTE(RTG_U81, setswitch);
+ WRITESHORT(RTG_X1, setswitch);
+ WRITESHORT(RTG_COMMAND, RTGCMD_SETSWITCH);
+
+ return 1 - enabled;
+}
+
+void SetPanning (__REGA0(struct BoardInfo *b), __REGA1(UBYTE *addr), __REGD0(UWORD width), __REGD1(WORD x_offset), __REGD2(WORD y_offset), __REGD7(RGBFTYPE format)) {
+ // Set the panning offset, or the offset used for the current display area on the Pi.
+ // The address needs to have CARD_BASE subtracted from it to be used as an offset on the Pi side.
+ if (!b)
+ return;
+
+ b->XOffset = x_offset;
+ b->YOffset = y_offset;
+
+ WRITELONG(RTG_ADDR1, (unsigned long)addr);
+ WRITESHORT(RTG_X1, width);
+ WRITESHORT(RTG_X2, b->XOffset);
+ WRITESHORT(RTG_Y2, b->YOffset);
+ WRITESHORT(RTG_COMMAND, RTGCMD_SETPAN);
+}
+
+void SetColorArray (__REGA0(struct BoardInfo *b), __REGD0(UWORD start), __REGD1(UWORD num)) {
+ // Sets the color components of X color components for 8-bit paletted display modes.
+ if (!b->CLUT)
+ return;
+
+ int j = start + num;
+
+ for(int i = start; i < j; i++) {
+ //WRITEBYTE(RTG_U82, (unsigned char)b->CLUT[i].Red);
+ //WRITEBYTE(RTG_U83, (unsigned char)b->CLUT[i].Green);
+ //WRITEBYTE(RTG_U84, (unsigned char)b->CLUT[i].Blue);
+ unsigned long xrgb = 0 | (b->CLUT[i].Red << 16) | (b->CLUT[i].Green << 8) | (b->CLUT[i].Blue);
+ WRITEBYTE(RTG_U81, (unsigned char)i);
+ WRITELONG(RTG_RGB1, xrgb);
+ WRITESHORT(RTG_COMMAND, RTGCMD_SETCLUT);
+ }
+}
+
+UWORD CalculateBytesPerRow (__REGA0(struct BoardInfo *b), __REGD0(UWORD width), __REGD7(RGBFTYPE format)) {
+ if (!b)
+ return 0;
+
+ UWORD pitch = width;
+
+ switch(format) {
+ default:
+ return pitch;
+ case 0x05: case 0x0A: case 0x0B: case 0x0D:
+ return (width * 2);
+ case 0x08: case 0x09:
+ return (width * 4);
+ }
+}
+
+APTR CalculateMemory (__REGA0(struct BoardInfo *b), __REGA1(unsigned long addr), __REGD7(RGBFTYPE format)) {
+ /*if (!b)
+ return (APTR)addr;
+
+ if (addr > (unsigned int)b->MemoryBase && addr < (((unsigned int)b->MemoryBase) + b->MemorySize)) {
+ addr = ((addr + 0x1000) & 0xFFFFF000);
+ }*/
+
+ return (APTR)addr;
+}
+
+ULONG GetCompatibleFormats (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format)) {
+ // It is of course compatible with all the formats ever.
+ return 0xFFFFFFFF;
+}
+
+static int display_enabled = 0;
+UWORD SetDisplay (__REGA0(struct BoardInfo *b), __REGD0(UWORD enabled)) {
+ // Enables or disables the display.
+ WRITEBYTE(RTG_U82, (unsigned char)enabled);
+ WRITESHORT(RTG_COMMAND, RTGCMD_SETDISPLAY);
+
+ return 1;
+}
+
+LONG ResolvePixelClock (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(ULONG pixel_clock), __REGD7(RGBFTYPE format)) {
+ mode_info->PixelClock = CLOCK_HZ;
+ mode_info->pll1.Clock = 0;
+ mode_info->pll2.ClockDivide = 1;
+
+ return 0;
+}
+
+ULONG GetPixelClock (__REGA0(struct BoardInfo *b), __REGA1(struct ModeInfo *mode_info), __REGD0(ULONG index), __REGD7(RGBFTYPE format)) {
+ // Just return 100MHz.
+ return CLOCK_HZ;
+}
+
+// None of these five really have to do anything.
+void SetClock (__REGA0(struct BoardInfo *b)) {
+}
+
+void SetMemoryMode (__REGA0(struct BoardInfo *b), __REGD7(RGBFTYPE format)) {
+}
+
+void SetWriteMask (__REGA0(struct BoardInfo *b), __REGD0(UBYTE mask)) {
+}
+
+void SetClearMask (__REGA0(struct BoardInfo *b), __REGD0(UBYTE mask)) {
+}
+
+void SetReadPlane (__REGA0(struct BoardInfo *b), __REGD0(UBYTE plane)) {
+}
+
+void WaitVerticalSync (__REGA0(struct BoardInfo *b), __REGD0(BOOL toggle)) {
+ // I don't know why this one has a bool in D0, but it isn't used for anything.
+}
+
+void FillRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(ULONG color), __REGD5(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r)
+ return;
+
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, w);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, h);
+ WRITELONG(RTG_RGB1, color);
+ WRITESHORT(RTG_X3, r->BytesPerRow);
+ WRITEBYTE(RTG_U81, mask);
+ WRITESHORT(RTG_COMMAND, RTGCMD_FILLRECT);
+}
+
+void InvertRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r)
+ return;
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, w);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, h);
+ WRITESHORT(RTG_X3, r->BytesPerRow);
+ WRITEBYTE(RTG_U81, mask);
+ WRITESHORT(RTG_COMMAND, RTGCMD_INVERTRECT);
+}
+
+void BlitRect (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD dx), __REGD3(WORD dy), __REGD4(WORD w), __REGD5(WORD h), __REGD6(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r)
+ return;
+
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, dx);
+ WRITESHORT(RTG_X3, w);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, dy);
+ WRITESHORT(RTG_Y3, h);
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITEBYTE(RTG_U81, mask);
+ WRITESHORT(RTG_COMMAND, RTGCMD_BLITRECT);
+}
+
+void BlitRectNoMaskComplete (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *rs), __REGA2(struct RenderInfo *rt), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD dx), __REGD3(WORD dy), __REGD4(WORD w), __REGD5(WORD h), __REGD6(UBYTE minterm), __REGD7(RGBFTYPE format)) {
+ if (!rs || !rt)
+ return;
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITELONG(RTG_ADDR1, (unsigned long)rs->Memory);
+ WRITELONG(RTG_ADDR2, (unsigned long)rt->Memory);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, dx);
+ WRITESHORT(RTG_X3, w);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, dy);
+ WRITESHORT(RTG_Y3, h);
+ WRITESHORT(RTG_X4, rs->BytesPerRow);
+ WRITESHORT(RTG_X5, rt->BytesPerRow);
+ WRITEBYTE(RTG_U81, minterm);
+ WRITESHORT(RTG_COMMAND, RTGCMD_BLITRECT_NOMASK_COMPLETE);
+}
+
+void BlitTemplate (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Template *t), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r || !t) return;
+ if (w < 1 || h < 1) return;
+
+ WRITELONG(RTG_ADDR2, (unsigned long)r->Memory);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, w);
+ WRITESHORT(RTG_X3, t->XOffset);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, h);
+ WRITESHORT(RTG_Y3, 0);
+
+ if ((unsigned long)t->Memory > CHIP_RAM_SIZE) {
+ WRITELONG(RTG_ADDR1, (unsigned long)t->Memory);
+ }
+ else {
+ unsigned long dest = CARD_SCRATCH;
+ memcpy((unsigned char *)dest, t->Memory, (t->BytesPerRow * h));
+ WRITELONG(RTG_ADDR1, (unsigned long)dest);
+ WRITELONG(RTG_ADDR3, (unsigned long)t->Memory);
+ }
+
+ WRITELONG(RTG_RGB1, t->FgPen);
+ WRITELONG(RTG_RGB2, t->BgPen);
+
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITESHORT(RTG_X5, t->BytesPerRow);
+
+ WRITEBYTE(RTG_U81, mask);
+ WRITEBYTE(RTG_U82, t->DrawMode);
+ WRITESHORT(RTG_COMMAND, RTGCMD_BLITTEMPLATE);
+}
+
+void BlitPattern (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Pattern *p), __REGD0(WORD x), __REGD1(WORD y), __REGD2(WORD w), __REGD3(WORD h), __REGD4(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r || !p) return;
+ if (w < 1 || h < 1) return;
+
+ WRITELONG(RTG_ADDR2, (unsigned long)r->Memory);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+ WRITESHORT(RTG_X1, x);
+ WRITESHORT(RTG_X2, w);
+ WRITESHORT(RTG_X3, p->XOffset);
+ WRITESHORT(RTG_Y1, y);
+ WRITESHORT(RTG_Y2, h);
+ WRITESHORT(RTG_Y3, p->YOffset);
+
+ if ((unsigned long)p->Memory > CHIP_RAM_SIZE) {
+ WRITELONG(RTG_ADDR1, (unsigned long)p->Memory);
+ }
+ else {
+ unsigned long dest = CARD_SCRATCH;
+ memcpy((unsigned char *)dest, p->Memory, (2 * (1 << p->Size)));
+ WRITELONG(RTG_ADDR1, (unsigned long)dest);
+ }
+
+ WRITELONG(RTG_RGB1, p->FgPen);
+ WRITELONG(RTG_RGB2, p->BgPen);
+
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITESHORT(RTG_X5, (1 << p->Size));
+
+ WRITEBYTE(RTG_U81, mask);
+ WRITEBYTE(RTG_U82, p->DrawMode);
+ WRITEBYTE(RTG_U83, (1 << p->Size));
+ WRITESHORT(RTG_COMMAND, RTGCMD_BLITPATTERN);
+}
+
+void DrawLine (__REGA0(struct BoardInfo *b), __REGA1(struct RenderInfo *r), __REGA2(struct Line *l), __REGD0(UBYTE mask), __REGD7(RGBFTYPE format)) {
+ if (!r || !b) return;
+
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+
+ WRITELONG(RTG_RGB1, l->FgPen);
+ WRITELONG(RTG_RGB2, l->BgPen);
+
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[format]);
+
+ WRITESHORT(RTG_X1, l->X);
+ WRITESHORT(RTG_X2, l->dX);
+ WRITESHORT(RTG_Y1, l->Y);
+ WRITESHORT(RTG_Y2, l->dY);
+
+ WRITESHORT(RTG_X3, l->Length);
+ WRITESHORT(RTG_Y3, l->LinePtrn);
+
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITESHORT(RTG_X5, l->PatternShift);
+
+ WRITEBYTE(RTG_U81, mask);
+ WRITEBYTE(RTG_U82, l->DrawMode);
+ WRITEBYTE(RTG_U83, l->pad);
+
+ WRITESHORT(RTG_COMMAND, RTGCMD_DRAWLINE);
+}
+
+void BlitPlanar2Chunky_Broken (__REGA0(struct BoardInfo *b), __REGA1(struct BitMap *bm), __REGA2(struct RenderInfo *r), __REGD0(SHORT x), __REGD1(SHORT y), __REGD2(SHORT dx), __REGD3(SHORT dy), __REGD4(SHORT w), __REGD5(SHORT h), __REGD6(UBYTE minterm), __REGD7(UBYTE mask)) {
+ if (!r || !b || !bm) return;
+
+ //unsigned long bmp_size = bm->BytesPerRow * bm->Rows;
+ unsigned char planemask_0 = 0, planemask = 0;
+ //unsigned short line_size = (w >> 3) + 2;
+ //unsigned long output_plane_size = line_size * h;
+ unsigned long plane_size = bm->BytesPerRow * bm->Rows;
+ short x_offset = (x >> 3);
+
+ unsigned long dest = CARD_SCRATCH;
+
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+ WRITELONG(RTG_ADDR2, (unsigned long)dest);
+ WRITELONG(RTG_ADDR3, (unsigned long)bm->Planes[0]);
+
+ for (unsigned short i = 0; i < bm->Depth; i++) {
+ if ((unsigned long)bm->Planes[i] == 0xFFFFFFFF) {
+ planemask |= (1 << i);
+ }
+ else if (bm->Planes[i] == NULL) {
+ planemask_0 |= (1 << i);
+ }
+ else {
+ unsigned long bmp_mem = (unsigned long)(bm->Planes[i]) + x_offset + (y * bm->BytesPerRow);
+ unsigned long plane_dest = dest;
+ for (unsigned short y_line = 0; y_line < h; y_line++) {
+ memcpy((unsigned char *)plane_dest, (unsigned char *)bmp_mem, bm->BytesPerRow);
+ plane_dest += bm->BytesPerRow;
+ bmp_mem += bm->BytesPerRow;
+ }
+ }
+ dest += plane_size;
+ }
+
+ WRITESHORT(RTG_X1, x % 0x07);
+ WRITESHORT(RTG_X2, dx);
+ WRITESHORT(RTG_X3, w);
+ WRITESHORT(RTG_Y1, 0);
+ WRITESHORT(RTG_Y2, dy);
+ WRITESHORT(RTG_Y3, h);
+
+ WRITESHORT(RTG_Y4, bm->Rows);
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITESHORT(RTG_U1, planemask_0 << 8 | planemask);
+ WRITESHORT(RTG_U2, bm->BytesPerRow);
+
+ WRITEBYTE(RTG_U81, mask);
+ WRITEBYTE(RTG_U82, minterm);
+ WRITEBYTE(RTG_U83, bm->Depth);
+
+ WRITESHORT(RTG_COMMAND, RTGCMD_P2C);
+}
+
+void BlitPlanar2Chunky (__REGA0(struct BoardInfo *b), __REGA1(struct BitMap *bm), __REGA2(struct RenderInfo *r), __REGD0(SHORT x), __REGD1(SHORT y), __REGD2(SHORT dx), __REGD3(SHORT dy), __REGD4(SHORT w), __REGD5(SHORT h), __REGD6(UBYTE minterm), __REGD7(UBYTE mask)) {
+ if (!b || !r)
+ return;
+
+ uint32_t plane_size = bm->BytesPerRow * bm->Rows;
+
+ uint32_t template_addr = CARD_SCRATCH;
+
+ uint16_t plane_mask = mask;
+ uint8_t ff_mask = 0x00;
+ uint8_t cur_plane = 0x01;
+
+ uint16_t line_size = (w >> 3) + 2;
+ uint32_t output_plane_size = line_size * h;
+ uint16_t x_offset = (x >> 3);
+
+ WRITELONG(RTG_ADDR1, (unsigned long)r->Memory);
+ WRITELONG(RTG_ADDR2, template_addr);
+ WRITESHORT(RTG_X4, r->BytesPerRow);
+ WRITESHORT(RTG_X5, line_size);
+ WRITESHORT(RTG_FORMAT, rgbf_to_rtg[r->RGBFormat]);
+
+ WRITEBYTE(RTG_U81, mask);
+ WRITEBYTE(RTG_U82, minterm);
+
+ for (int16_t i = 0; i < bm->Depth; i++) {
+ uint16_t x_offset = (x >> 3);
+ if ((uint32_t)bm->Planes[i] == 0xFFFFFFFF) {
+ //memset((uint8_t*)(((uint32_t)b->memory)+template_addr), 0xFF, output_plane_size);
+ ff_mask |= cur_plane;
+ }
+ else if (bm->Planes[i] != NULL) {
+ uint8_t* bmp_mem = (uint8_t*)bm->Planes[i] + (y * bm->BytesPerRow) + x_offset;
+ uint8_t* dest = (uint8_t*)((uint32_t)template_addr);
+ for (int16_t y_line = 0; y_line < h; y_line++) {
+ memcpy(dest, bmp_mem, line_size);
+ dest += line_size;
+ bmp_mem += bm->BytesPerRow;
+ }
+ }
+ else {
+ plane_mask &= (cur_plane ^ 0xFF);
+ }
+ cur_plane <<= 1;
+ template_addr += output_plane_size;
+ }
+
+ WRITESHORT(RTG_X1, (x & 0x07));
+ WRITESHORT(RTG_X2, dx);
+ WRITESHORT(RTG_X3, w);
+ WRITESHORT(RTG_Y1, 0);
+ WRITESHORT(RTG_Y2, dy);
+ WRITESHORT(RTG_Y3, h);
+
+ WRITESHORT(RTG_U1, (plane_mask << 8 | ff_mask));
+ WRITEBYTE(RTG_U83, bm->Depth);
+
+ WRITESHORT(RTG_COMMAND, RTGCMD_P2C);
+}
+
+void BlitPlanar2Direct (__REGA0(struct BoardInfo *b), __REGA1(struct BitMap *bmp), __REGA2(struct RenderInfo *r), __REGA3(struct ColorIndexMapping *clut), __REGD0(SHORT x), __REGD1(SHORT y), __REGD2(SHORT dx), __REGD3(SHORT dy), __REGD4(SHORT w), __REGD5(SHORT h), __REGD6(UBYTE minterm), __REGD7(UBYTE mask)) {
+
+}
--- /dev/null
+// "Register" offsets for sending data to the RTG.
+enum pi_regs {
+ RTG_COMMAND = 0x00,
+ RTG_X1 = 0x02,
+ RTG_X2 = 0x04,
+ RTG_X3 = 0x06,
+ RTG_Y1 = 0x08,
+ RTG_Y2 = 0x0A,
+ RTG_Y3 = 0x0C,
+ RTG_FORMAT = 0x0E,
+ RTG_RGB1 = 0x10,
+ RTG_RGB2 = 0x14,
+ RTG_ADDR1 = 0x18,
+ RTG_ADDR2 = 0x1C,
+ RTG_U81 = 0x20,
+ RTG_U82 = 0x21,
+ RTG_U83 = 0x22,
+ RTG_U84 = 0x23,
+ RTG_X4 = 0x24,
+ RTG_X5 = 0x26,
+ RTG_Y4 = 0x28,
+ RTG_Y5 = 0x2A,
+ RTG_U1 = 0x2C,
+ RTG_U2 = 0x2E,
+ RTG_ADDR3 = 0x30,
+ RTG_ADDR4 = 0x34,
+};
+
+enum rtg_cmds {
+ RTGCMD_SETGC,
+ RTGCMD_SETPAN,
+ RTGCMD_SETCLUT,
+ RTGCMD_ENABLE,
+ RTGCMD_SETDISPLAY,
+ RTGCMD_SETSWITCH,
+ RTGCMD_FILLRECT,
+ RTGCMD_BLITRECT,
+ RTGCMD_BLITRECT_NOMASK_COMPLETE,
+ RTGCMD_BLITPATTERN,
+ RTGCMD_BLITTEMPLATE,
+ RTGCMD_INVERTRECT,
+ RTGCMD_DRAWLINE,
+ RTGCMD_P2C,
+ RTGCMD_P2D,
+};
+
+enum rtg_formats {
+ RTGFMT_8BIT,
+ RTGFMT_RBG565,
+ RTGFMT_RGB32,
+ RTGFMT_RGB555,
+ RTGFMT_NUM,
+};
+
+enum gfx_minterm_modes {
+ MINTERM_FALSE,
+ MINTERM_NOR,
+ MINTERM_ONLYDST,
+ MINTERM_NOTSRC,
+ MINTERM_ONLYSRC,
+ MINTERM_INVERT,
+ MINTERM_EOR,
+ MINTERM_NAND,
+ MINTERM_AND,
+ MINTERM_NEOR,
+ MINTERM_DST,
+ MINTERM_NOTONLYSRC,
+ MINTERM_SRC,
+ MINTERM_NOTONLYDST,
+ MINTERM_OR,
+ MINTERM_TRUE,
+};
+
+enum gfx_draw_modes {
+ DRAWMODE_JAM1 = 0,
+ DRAWMODE_JAM2 = 1,
+ DRAWMODE_COMPLEMENT = 2,
+ DRAWMODE_INVERSVID = 4,
+};
--- /dev/null
+#ifndef settings_H
+#define settings_H
+
+/************************************************************************/
+
+enum{
+ PLANAR,
+ CHUNKY,
+ HICOLOR,
+ TRUECOLOR,
+ TRUEALPHA,
+ MAXMODES
+};
+
+/************************************************************************/
+
+#define SETTINGSNAMEMAXCHARS 30
+#define BOARDNAMEMAXCHARS 30
+
+struct P96MonitorInfo
+{
+ UBYTE Name[32]; // Name des Monitortyps, z.B. "NEC P750"
+
+ ULONG HSyncMin; // Minimal unterstützte Horizontalfrequenz in Hz
+ ULONG HSyncMax; // Maximal unterstützte Horizontalfrequenz in Hz
+
+ UWORD VSyncMin; // Minimal unterstützte Vertikalfrequenz in Hz
+ UWORD VSyncMax; // Maximal unterstützte Vertikalfrequenz in Hz
+
+ ULONG Flags; // Siehe unten
+};
+
+#define MIB_DPMS_StandBy (0) // Monitor unterstützt DPMS-Level "stand-by".
+ // Dieses Feature ist optional, nicht jeder
+ // DPMS-fähige Monitor muß es unterstützen.
+ // Aktivierung: hsync aus, vsync an
+
+#define MIB_DPMS_Suspend (1) // Monitor unterstützt DPMS-Level "suspend".
+ // Dieses Feature ist Pflicht, jeder
+ // DPMS-fähige Monitor muß es unterstützen.
+ // Aktivierung: hsync an, vsync aus
+
+#define MIB_DPMS_ActiveOff (2) // Monitor unterstützt DPMS-Level "active off".
+ // Dieses Feature ist Pflicht, jeder
+ // DPMS-fähige Monitor muß es unterstützen.
+ // Aktivierung: hsync aus, vsync aus
+
+#define MIF_DPMS_StandBy (1UL << MIB_DPMS_StandBy)
+#define MIF_DPMS_Suspend (1UL << MIB_DPMS_Suspend)
+#define MIF_DPMS_ActiveOff (1UL << MIB_DPMS_ActiveOff)
+
+struct Settings{
+ struct Node Node;
+ struct MinList Resolutions;
+ ULONG BoardType;
+// a value discribing assignment to nth board local to boardtype
+// to be used for reassignment when boards are added or removed.
+ UWORD LocalOrdering;
+ WORD LastSelected;
+ char NameField[SETTINGSNAMEMAXCHARS];
+ char *BoardName;
+ struct P96MonitorInfo *MonitorInfo;
+};
+
+#define MAXRESOLUTIONNAMELENGTH 22
+
+/********************************
+ * only used within rtg.library *
+ ********************************/
+struct LibResolution{
+ struct Node Node;
+ char P96ID[6];
+ char Name[MAXRESOLUTIONNAMELENGTH];
+ ULONG DisplayID;
+ UWORD Width;
+ UWORD Height;
+ UWORD Flags;
+ struct ModeInfo *Modes[MAXMODES];
+ struct BoardInfo *BoardInfo;
+ struct LibResolution *HashChain;
+};
+
+/*****************************
+ * only used within MoniTool *
+ *****************************/
+struct Resolution{
+ struct Node Node;
+ struct MinList ModeInfos;
+ ULONG DisplayID;
+ UWORD Width;
+ UWORD Height;
+ BOOL Active;
+ WORD LastSelected;
+ UWORD Flags;
+ char Name[MAXRESOLUTIONNAMELENGTH];
+};
+
+#define P96B_FAMILY 0 // obsolete (Resolution is an entire family)
+#define P96B_PUBLIC 1 // Resolution should be added to the public
+#define P96B_MONITOOL 2
+
+#define P96B_CHECKME 15 // Resolution has been attached to another board
+ // by AttachSettings without being checked against
+ // hardware limits
+
+#define P96F_FAMILY (1<<P96B_FAMILY) // obsolete
+#define P96F_PUBLIC (1<<P96B_PUBLIC)
+#define P96F_MONITOOL (1<<P96B_MONITOOL)
+#define P96F_CHECKME (1<<P96B_CHECKME)
+
+/*
+enum {
+ DBLLORES_FLAGS, // 0000 320x200
+ DBLHIRES_FLAGS, // 8000 640x200
+ DBLSHIRES_FLAGS, // 8020 1280x200
+ LORES_FLAGS, // 0004 320x400
+ HIRES_FLAGS, // 8004 640x400
+ SHIRES_FLAGS, // 8024 1280x400
+ LORESLACE_FLAGS, // 0005 320x800
+ HIRESLACE_FLAGS, // 8005 640x800
+ SHIRESLACE_FLAGS, // 8025 1280x800
+ MAXFAMILYFLAGS
+};
+*/
+
+/*****************************
+ * this one describes a mode *
+ *****************************/
+struct ModeInfo{
+ struct Node Node; // used for linking ModeInfos e.g. within MoniTool
+ WORD OpenCount;
+ BOOL Active;
+ UWORD Width;
+ UWORD Height;
+ UBYTE Depth;
+ UBYTE Flags;
+
+ UWORD HorTotal; // wichtig für aufziehen (beeinflußt Timings)
+ UWORD HorBlankSize; // Rahmengröße
+ UWORD HorSyncStart; // bestimmt Bildlage
+ UWORD HorSyncSize; // muß Spezifikation für Sync-Lücke erfüllen
+
+ UBYTE HorSyncSkew; // im Moment obsolet
+ UBYTE HorEnableSkew; //
+
+ UWORD VerTotal; // analog zu horizontalen Werten
+ UWORD VerBlankSize;
+ UWORD VerSyncStart;
+ UWORD VerSyncSize;
+
+ union{
+ UBYTE Clock; // Tseng: Nummer der Hardwareclock
+ UBYTE Numerator; // Cirrus: Mumerator für PLL
+ } pll1;
+ union{
+ UBYTE ClockDivide; // Tseng: Clockteiler
+ UBYTE Denominator; // Cirrus: Denominator für PLL
+ } pll2;
+ ULONG PixelClock; // PixelClock in Hz
+};
+
+/***********************************
+* Flags: */
+
+#define GMB_DOUBLECLOCK 0
+#define GMB_INTERLACE 1
+#define GMB_DOUBLESCAN 2
+#define GMB_HPOLARITY 3
+#define GMB_VPOLARITY 4
+#define GMB_COMPATVIDEO 5
+#define GMB_DOUBLEVERTICAL 6
+#define GMB_ALWAYSBORDER 7 // only used by MoniTool-EditScreen
+
+#define GMF_DOUBLECLOCK (1L<<GMB_DOUBLECLOCK)
+#define GMF_INTERLACE (1L<<GMB_INTERLACE)
+#define GMF_DOUBLESCAN (1L<<GMB_DOUBLESCAN)
+#define GMF_HPOLARITY (1L<<GMB_HPOLARITY)
+#define GMF_VPOLARITY (1L<<GMB_VPOLARITY)
+#define GMF_COMPATVIDEO (1L<<GMB_COMPATVIDEO)
+#define GMF_DOUBLEVERTICAL (1L<<GMB_DOUBLEVERTICAL)
+#define GMF_ALWAYSBORDER (1L<<GMB_ALWAYSBORDER)
+
+/************************************************************************/
+#endif
-#include "../platforms.h"
#include <stdlib.h>
#include <string.h>
+#include "platforms/platforms.h"
+
int handle_register_read_dummy(unsigned int addr, unsigned char type, unsigned int *val);
int handle_register_write_dummy(unsigned int addr, unsigned int value, unsigned char type);
-#include "../config_file/config_file.h"
+#include "config_file/config_file.h"
enum base_platforms {
PLATFORM_NONE,
--- /dev/null
+#include <time.h>
+#include <stdio.h>
+#include <stdint.h>
+#include "rtc.h"
+
+static unsigned char rtc_mystery_reg[3];
+unsigned char ricoh_memory[0x0F];
+unsigned char ricoh_alarm[0x0F];
+
+void put_rtc_byte(uint32_t address_, uint8_t value_, uint8_t rtc_type) {
+ uint32_t address = address_ & 0x3F;
+ uint8_t value = (value_ & 0x0F);
+
+ address >>= 2;
+
+ //printf("Wrote byte %.2X.\n", address);
+
+ if (rtc_type == RTC_TYPE_MSM) {
+ switch(address) {
+ case 0x0D:
+ rtc_mystery_reg[address - 0x0D] = value & (0x01 | 0x08);
+ break;
+ case 0x0E:
+ case 0x0F:
+ rtc_mystery_reg[address - 0x0D] = value;
+ break;
+ default:
+ return;
+ }
+ }
+ else {
+ int rtc_bank = (rtc_mystery_reg[0] & 0x03);
+ if ((rtc_bank & 0x02) && address < 0x0D) {
+ if (rtc_bank & 0x01) {
+ // Low nibble of value -> high nibble in RTC memory
+ ricoh_memory[address] &= 0x0F;
+ ricoh_memory[address] |= ((value & 0x0F) << 4);
+ }
+ else {
+ // Low nibble of value -> low nibble in RTC memory
+ ricoh_memory[address] &= 0xF0;
+ ricoh_memory[address] |= (value & 0x0F);
+ }
+ return;
+ }
+ else if ((rtc_bank & 0x01) && address < 0x0D) {
+ // RTC alarm stuff, no idea what this is supposed to be for.
+ switch(address) {
+ case 0x00:
+ case 0x01:
+ case 0x09:
+ case 0x0C:
+ ricoh_alarm[address] = 0;
+ break;
+ case 0x03:
+ case 0x06:
+ ricoh_alarm[address] &= (value & (0x08 ^ 0xFF));
+ break;
+ case 0x05:
+ case 0x08:
+ case 0x0B:
+ ricoh_alarm[address] = (value & (0x0C ^ 0xFF));
+ break;
+ case 0x0A:
+ ricoh_alarm[address] = (value & (0x0E ^ 0xFF));
+ break;
+ default:
+ ricoh_alarm[address] = value;
+ break;
+ }
+ //printf("Write to Ricoh alarm @%.2X: %.2X -> %.2X\n", address, value, ricoh_alarm[address]);
+ return;
+ }
+ else if (address >= 0x0D) {
+ rtc_mystery_reg[address - 0x0D] = value;
+ return;
+ }
+ }
+}
+
+uint8_t get_rtc_byte(uint32_t address_, uint8_t rtc_type) {
+ uint32_t address = address_ & 0x3F;
+
+ if ((address & 3) == 2 || (address & 3) == 0) {
+ //printf("Garbage byte read.\n");
+ return 0;
+ }
+
+ address >>= 2;
+ time_t t;
+ time(&t);
+ struct tm *rtc_time = localtime(&t);
+
+ if (rtc_type == RTC_TYPE_RICOH) {
+ int rtc_bank = (rtc_mystery_reg[0] & 0x03);
+ if ((rtc_bank & 0x02) && address < 0x0D) {
+ // Get low/high nibble from memory (bank 2/3)
+ return ((ricoh_memory[address] >> (rtc_bank & 0x01) ? 4 : 0) & 0x0F);
+ }
+ else if ((rtc_bank & 0x01) && address < 0x0D) {
+ // Get byte from alarm
+ return ricoh_alarm[address];
+ }
+ }
+
+ //printf("Read byte %.2X.\n", address);
+
+ switch (address) {
+ case 0x00: // Seconds low?
+ return rtc_time->tm_sec % 10;
+ case 0x01: // Seconds high?
+ return rtc_time->tm_sec / 10;
+ case 0x02: // Minutes low?
+ return rtc_time->tm_min % 10;
+ case 0x03: // Minutes high?
+ return rtc_time->tm_min / 10;
+ case 0x04: // Hours low?
+ return rtc_time->tm_hour % 10;
+ case 0x05: // Hours high?
+ if (rtc_type == RTC_TYPE_MSM) {
+ if (rtc_mystery_reg[2] & 4) {
+ return (((rtc_time->tm_hour % 12) / 10) | (rtc_time->tm_hour >= 12) ? 0x04 : 0x00);
+ }
+ else
+ return rtc_time->tm_hour / 10;
+ }
+ else {
+ if (ricoh_alarm[10] & 0x01) {
+ return rtc_time->tm_hour / 10;
+ }
+ else {
+ return (((rtc_time->tm_hour % 12) / 10) | (rtc_time->tm_hour >= 12) ? 0x02 : 0x00);
+ }
+ break;
+ }
+ case 0x06: // Day low?
+ if (rtc_type == RTC_TYPE_MSM)
+ return rtc_time->tm_mday % 10;
+ else
+ return rtc_time->tm_wday;
+ case 0x07: // Day high?
+ if (rtc_type == RTC_TYPE_MSM)
+ return rtc_time->tm_mday / 10;
+ else
+ return rtc_time->tm_mday % 10;
+ case 0x08: // Month low?
+ if (rtc_type == RTC_TYPE_MSM)
+ return (rtc_time->tm_mon + 1) % 10;
+ else
+ return rtc_time->tm_mday / 10;
+ case 0x09: // Month high?
+ if (rtc_type == RTC_TYPE_MSM)
+ return (rtc_time->tm_mon + 1) / 10;
+ else
+ return (rtc_time->tm_mon + 1) % 10;
+ case 0x0A: // Year low?
+ if (rtc_type == RTC_TYPE_MSM)
+ return rtc_time->tm_year % 10;
+ else
+ return (rtc_time->tm_mon + 1) / 10;
+ case 0x0B: // Year high?
+ if (rtc_type == RTC_TYPE_MSM)
+ return rtc_time->tm_year / 10;
+ else
+ return rtc_time->tm_year % 10;
+ case 0x0C: // Day of week?
+ if (rtc_type == RTC_TYPE_MSM)
+ return rtc_time->tm_wday;
+ else
+ return rtc_time->tm_year / 10;
+ case 0x0D: // Mystery register D-F?
+ case 0x0E:
+ case 0x0F:
+ if (rtc_type == RTC_TYPE_MSM) {
+ return rtc_mystery_reg[address - 0x0D];
+ }
+ else {
+ if (address == 0x0D) return rtc_mystery_reg[address - 0x0D];
+ return 0;
+ }
+ default:
+ break;
+ }
+
+ return 0x00;
+}
--- /dev/null
+void put_rtc_byte(uint32_t address_, uint8_t value, uint8_t rtc_type);
+uint8_t get_rtc_byte(uint32_t address_, uint8_t rtc_type);
+
+enum rtc_types {
+ RTC_TYPE_MSM,
+ RTC_TYPE_RICOH,
+ RTC_TYPE_NONE,
+};
\ No newline at end of file
--- /dev/null
+!Copyright (C) 2020 Intel Corporation. All rights reserved.
+!Your use of Intel Corporation's design tools, logic functions
+!and other software and tools, and any partner logic
+!functions, and any output files from any of the foregoing
+!(including device programming or simulation files), and any
+!associated documentation or information are expressly subject
+!to the terms and conditions of the Intel Program License
+!Subscription Agreement, the Intel Quartus Prime License Agreement,
+!the Intel FPGA IP License Agreement, or other applicable license
+!agreement, including, without limitation, that your use is for
+!the sole purpose of programming logic devices manufactured by
+!Intel and sold by Intel or its authorized distributors. Please
+!refer to the applicable agreement for further details, at
+!https://fpgasoftware.intel.com/eula.
+!
+!Quartus Prime SVF converter 20.1
+!
+!Device #1: EPM570 - output_files/pistorm.pof Sun Feb 21 11:49:40 2021
+!
+!NOTE "USERCODE" "003373BC";
+!
+!NOTE "CHECKSUM" "003373EC";
+!
+!
+!
+FREQUENCY 1.00E+05 HZ;
+!
+!
+!
+TRST ABSENT;
+ENDDR IDLE;
+ENDIR IRPAUSE;
+STATE IDLE;
+SIR 10 TDI (005);
+RUNTEST IDLE 4 TCK ENDSTATE IDLE;
+SDR 480 TDI (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
+SIR 10 TDI (3FF);
+RUNTEST 103 TCK;
+SIR 10 TDI (2CC);
+RUNTEST 103 TCK;
+!
+!
+!
+!CHECKING SILICON ID
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0111);
+SIR 10 TDI (205);
+RUNTEST 4 TCK;
+SDR 16 TDI (FFFF) TDO (8232) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (2AA2);
+SDR 16 TDI (FFFF) TDO (4A82);
+SDR 16 TDI (FFFF) TDO (0C2C);
+SDR 16 TDI (FFFF) TDO (0000);
+!
+!
+!
+!BULK ERASE
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0021);
+SIR 10 TDI (2F2);
+RUNTEST 50003 TCK;
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0001);
+SIR 10 TDI (2F2);
+RUNTEST 50003 TCK;
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0000);
+SIR 10 TDI (2F2);
+RUNTEST 50003 TCK;
+!
+!
+!
+!PROGRAM
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0000);
+SIR 10 TDI (2F4);
+RUNTEST 4 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF9E);
+RUNTEST 10 TCK;
+SDR 16 TDI (AF9E);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CF9);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CF9);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFC);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F3E);
+RUNTEST 10 TCK;
+SDR 16 TDI (79F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (BCFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (E7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDED);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EE7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EE6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF9F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AD5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BD5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF4);
+RUNTEST 10 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B2FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B2FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AD5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF4);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BD5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B3BF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B999);
+RUNTEST 10 TCK;
+SDR 16 TDI (99DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B999);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BABF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B999);
+RUNTEST 10 TCK;
+SDR 16 TDI (99DE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7E7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AABF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BEA);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDBD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFC6);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FE8F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (DBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FC1F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B000);
+RUNTEST 10 TCK;
+SDR 16 TDI (01F5);
+RUNTEST 10 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FC1D);
+RUNTEST 10 TCK;
+SDR 16 TDI (B800);
+RUNTEST 10 TCK;
+SDR 16 TDI (01FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FC0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B808);
+RUNTEST 10 TCK;
+SDR 16 TDI (81F4);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FC0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B800);
+RUNTEST 10 TCK;
+SDR 16 TDI (81FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CEC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB91);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9EB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DCCA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B19C);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B737);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7E7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FCFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F5B);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (ABBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (DF7E);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F9F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF9);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFD7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F4F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BE7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F80);
+RUNTEST 10 TCK;
+SDR 16 TDI (C00F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B019);
+RUNTEST 10 TCK;
+SDR 16 TDI (98F5);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F20);
+RUNTEST 10 TCK;
+SDR 16 TDI (C00D);
+RUNTEST 10 TCK;
+SDR 16 TDI (B819);
+RUNTEST 10 TCK;
+SDR 16 TDI (997F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F48);
+RUNTEST 10 TCK;
+SDR 16 TDI (C007);
+RUNTEST 10 TCK;
+SDR 16 TDI (B819);
+RUNTEST 10 TCK;
+SDR 16 TDI (9C75);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F28);
+RUNTEST 10 TCK;
+SDR 16 TDI (C00F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B819);
+RUNTEST 10 TCK;
+SDR 16 TDI (9A7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (674C);
+RUNTEST 10 TCK;
+SDR 16 TDI (ECEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB99);
+RUNTEST 10 TCK;
+SDR 16 TDI (997F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77CD);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCCA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B199);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F6E);
+RUNTEST 10 TCK;
+SDR 16 TDI (F77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FB7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FE6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBA);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFD3);
+RUNTEST 10 TCK;
+SDR 16 TDI (EBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFCF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FCED);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB9F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (F33F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B18E);
+RUNTEST 10 TCK;
+SDR 16 TDI (6075);
+RUNTEST 10 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (F33F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B996);
+RUNTEST 10 TCK;
+SDR 16 TDI (607F);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (F03F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9C6);
+RUNTEST 10 TCK;
+SDR 16 TDI (0075);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (F03F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9A6);
+RUNTEST 10 TCK;
+SDR 16 TDI (002F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CE);
+RUNTEST 10 TCK;
+SDR 16 TDI (C4E7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBB3);
+RUNTEST 10 TCK;
+SDR 16 TDI (93FE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DC);
+RUNTEST 10 TCK;
+SDR 16 TDI (D8CA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B189);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7F7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BCBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BD7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (65FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (65FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF7E);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFD7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FD7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7E);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F2F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B007);
+RUNTEST 10 TCK;
+SDR 16 TDI (E074);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF8F);
+RUNTEST 10 TCK;
+SDR 16 TDI (A827);
+RUNTEST 10 TCK;
+SDR 16 TDI (E27E);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F1F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B807);
+RUNTEST 10 TCK;
+SDR 16 TDI (E075);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF8F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B847);
+RUNTEST 10 TCK;
+SDR 16 TDI (E42F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (678C);
+RUNTEST 10 TCK;
+SDR 16 TDI (CC87);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB89);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDDA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B1DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (9CEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7E6D);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (D9DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF77);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF4);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7D);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7E);
+RUNTEST 10 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (57FE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF5D);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B8EB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FE8);
+RUNTEST 10 TCK;
+SDR 16 TDI (E9DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (0B0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B058);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F75);
+RUNTEST 10 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (0B0D);
+RUNTEST 10 TCK;
+SDR 16 TDI (BA00);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FED);
+RUNTEST 10 TCK;
+SDR 16 TDI (4B0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B87E);
+RUNTEST 10 TCK;
+SDR 16 TDI (0775);
+RUNTEST 10 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FED);
+RUNTEST 10 TCK;
+SDR 16 TDI (030F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B840);
+RUNTEST 10 TCK;
+SDR 16 TDI (073F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67EC);
+RUNTEST 10 TCK;
+SDR 16 TDI (4DC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B859);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (8CCA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B19D);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B37F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FED);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BCFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7E7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A77F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (ABFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF5);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DD3F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BABF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FD0);
+RUNTEST 10 TCK;
+SDR 16 TDI (AF2F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDB);
+RUNTEST 10 TCK;
+SDR 16 TDI (885F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0E);
+RUNTEST 10 TCK;
+SDR 16 TDI (A02F);
+RUNTEST 10 TCK;
+SDR 16 TDI (B199);
+RUNTEST 10 TCK;
+SDR 16 TDI (85DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (A00F);
+RUNTEST 10 TCK;
+SDR 16 TDI (A991);
+RUNTEST 10 TCK;
+SDR 16 TDI (819F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (80DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9F9);
+RUNTEST 10 TCK;
+SDR 16 TDI (A79F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0F);
+RUNTEST 10 TCK;
+SDR 16 TDI (80CF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9F9);
+RUNTEST 10 TCK;
+SDR 16 TDI (A7BF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67C8);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB99);
+RUNTEST 10 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77CD);
+RUNTEST 10 TCK;
+SDR 16 TDI (9CCA);
+RUNTEST 10 TCK;
+SDR 16 TDI (B199);
+RUNTEST 10 TCK;
+SDR 16 TDI (9CBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (777F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (6EEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EF6);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7EF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FD7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FA97);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEEC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FA97);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF77);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EB6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (EB7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F79F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FCFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F2C);
+RUNTEST 10 TCK;
+SDR 16 TDI (897F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BA21);
+RUNTEST 10 TCK;
+SDR 16 TDI (077F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F0C);
+RUNTEST 10 TCK;
+SDR 16 TDI (CFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B622);
+RUNTEST 10 TCK;
+SDR 16 TDI (87FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FA57);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F2C);
+RUNTEST 10 TCK;
+SDR 16 TDI (C3FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AF10);
+RUNTEST 10 TCK;
+SDR 16 TDI (8FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (D68F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BE44);
+RUNTEST 10 TCK;
+SDR 16 TDI (80FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FA6F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F73);
+RUNTEST 10 TCK;
+SDR 16 TDI (D2CF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9E06);
+RUNTEST 10 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67EE);
+RUNTEST 10 TCK;
+SDR 16 TDI (8E87);
+RUNTEST 10 TCK;
+SDR 16 TDI (999B);
+RUNTEST 10 TCK;
+SDR 16 TDI (B8E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (999E);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCCF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A666);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (DCD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B5D9);
+RUNTEST 10 TCK;
+SDR 16 TDI (9DEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (2AEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (9DDE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (72AE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (E957);
+RUNTEST 10 TCK;
+SDR 16 TDI (6EEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B3BF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (8FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9DFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAB7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (AABF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9ABB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FA97);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF57);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBDB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEBE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F6D);
+RUNTEST 10 TCK;
+SDR 16 TDI (66BF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB61);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FD6);
+RUNTEST 10 TCK;
+SDR 16 TDI (DD4F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (0CEB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B2B9);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAA7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (0CEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAF9);
+RUNTEST 10 TCK;
+SDR 16 TDI (787F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF0);
+RUNTEST 10 TCK;
+SDR 16 TDI (250F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB78);
+RUNTEST 10 TCK;
+SDR 16 TDI (037F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FE8);
+RUNTEST 10 TCK;
+SDR 16 TDI (08DF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BA78);
+RUNTEST 10 TCK;
+SDR 16 TDI (04FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (4666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CEE7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BB99);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBE6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (B99E);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (47CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCCF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A666);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (5777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77D9);
+RUNTEST 10 TCK;
+SDR 16 TDI (DCC2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B1CD);
+RUNTEST 10 TCK;
+SDR 16 TDI (99EE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (2AEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDDE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (52AE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (E957);
+RUNTEST 10 TCK;
+SDR 16 TDI (6EEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7EF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAA7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAA7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FD57);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BAEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF5F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAA7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B55F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FAAF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6667);
+RUNTEST 10 TCK;
+SDR 16 TDI (B333);
+RUNTEST 10 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (7999);
+RUNTEST 10 TCK;
+SDR 16 TDI (B31F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3333);
+RUNTEST 10 TCK;
+SDR 16 TDI (67CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 10 TCK;
+SDR 16 TDI (B999);
+RUNTEST 10 TCK;
+SDR 16 TDI (99E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (B99E);
+RUNTEST 10 TCK;
+SDR 16 TDI (6666);
+RUNTEST 10 TCK;
+SDR 16 TDI (47CC);
+RUNTEST 10 TCK;
+SDR 16 TDI (CCCF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A666);
+RUNTEST 10 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 10 TCK;
+SDR 16 TDI (6CCC);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (6957);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (B777);
+RUNTEST 10 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7777);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (B74A);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 10 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 10 TCK;
+SDR 16 TDI (2AEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDDE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (52AE);
+RUNTEST 10 TCK;
+SDR 16 TDI (EEEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AEEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (E957);
+RUNTEST 10 TCK;
+SDR 16 TDI (6EEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (6F7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BF7D);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (D7FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FECE);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFEE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 10 TCK;
+SDR 16 TDI (7B3F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (AEFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (DDDF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFBB);
+RUNTEST 10 TCK;
+SDR 16 TDI (BECE);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7B9B);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF77);
+RUNTEST 10 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FCDC);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FF6);
+RUNTEST 10 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFDC);
+RUNTEST 10 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (777F);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 10 TCK;
+SDR 16 TDI (F9E7);
+RUNTEST 10 TCK;
+SDR 16 TDI (79F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (CFFE);
+RUNTEST 10 TCK;
+SDR 16 TDI (AF9E);
+RUNTEST 10 TCK;
+SDR 16 TDI (7CF9);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFCF);
+RUNTEST 10 TCK;
+SDR 16 TDI (A7CF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9E7F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F9F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFF3);
+RUNTEST 10 TCK;
+SDR 16 TDI (FF9F);
+RUNTEST 10 TCK;
+SDR 16 TDI (7F9F);
+RUNTEST 10 TCK;
+SDR 16 TDI (3E79);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F3FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (73FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (9FFC);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 10 TCK;
+SDR 16 TDI (F9F3);
+RUNTEST 10 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0001);
+SIR 10 TDI (2F4);
+RUNTEST 4 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+!
+!
+!
+!VERIFY
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0000);
+SIR 10 TDI (205);
+RUNTEST 4 TCK;
+SDR 16 TDI (FFFF) TDO (7FFF) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (F9FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FF9E);
+SDR 16 TDI (FFFF) TDO (AF9E);
+SDR 16 TDI (FFFF) TDO (7CF9);
+SDR 16 TDI (FFFF) TDO (7CF9);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFC);
+SDR 16 TDI (FFFF) TDO (7F3E);
+SDR 16 TDI (FFFF) TDO (79F3);
+SDR 16 TDI (FFFF) TDO (BCFF);
+SDR 16 TDI (FFFF) TDO (E7FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FEEE);
+SDR 16 TDI (FFFF) TDO (7FFB);
+SDR 16 TDI (FFFF) TDO (BBBF);
+SDR 16 TDI (FFFF) TDO (BFEE);
+SDR 16 TDI (FFFF) TDO (EFFD);
+SDR 16 TDI (FFFF) TDO (7BBB);
+SDR 16 TDI (FFFF) TDO (FFF3);
+SDR 16 TDI (FFFF) TDO (BEFF);
+SDR 16 TDI (FFFF) TDO (DDED);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (BBBF);
+SDR 16 TDI (FFFF) TDO (BEEF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FEFE);
+SDR 16 TDI (FFFF) TDO (7FFB);
+SDR 16 TDI (FFFF) TDO (BBFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (B9FF);
+SDR 16 TDI (FFFF) TDO (EE7F);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFD);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFE7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FEFE);
+SDR 16 TDI (FFFF) TDO (7FFB);
+SDR 16 TDI (FFFF) TDO (BBFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (B9FF);
+SDR 16 TDI (FFFF) TDO (EE6F);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFD);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FEF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFEF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BDFE);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (B7FF);
+SDR 16 TDI (FFFF) TDO (FFBF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BBFF);
+SDR 16 TDI (FFFF) TDO (FF9F);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BBFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FEF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFBF);
+SDR 16 TDI (FFFF) TDO (BDFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BBBF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FF7F);
+SDR 16 TDI (FFFF) TDO (BDFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0001);
+SIR 10 TDI (205);
+RUNTEST 4 TCK;
+SDR 16 TDI (FFFF) TDO (FFFF) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SIR 10 TDI (203);
+RUNTEST 4 TCK;
+SDR 14 TDI (0000);
+SIR 10 TDI (2F4);
+RUNTEST 4 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 10 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 10 TCK;
+SIR 10 TDI (201);
+RUNTEST 103 TCK;
+SIR 10 TDI (3FF);
+RUNTEST 100 TCK;
+STATE IDLE;
--- /dev/null
+set quartus_bin_path=C:\intelFPGA_lite\20.1\quartus\bin64
+set piaddress=192.168.1.144
+
+%quartus_bin_path%\quartus_sh --flow compile pistorm
+if %errorlevel% neq 0 GOTO ERRORCOMPILE
+
+%quartus_bin_path%\quartus_cpf -c -q 100KHz -g 3.3 -n p output_files\pistorm.pof bitstream.svf
+if %errorlevel% neq 0 GOTO ERRORSVF
+
+echo y | pscp -l pi -pw raspberry -P 22 bitstream.svf %piaddress%:./pistorm/bitstream.svf
+if %errorlevel% neq 0 GOTO ERRORSCP
+
+echo y | plink -l pi -pw raspberry -P 22 %piaddress% "cd pistorm && ./nprog.sh"
+if %errorlevel% neq 0 GOTO ERRORPROG
+
+goto done
+
+:ERRORCOMPILE
+echo "ERROR COMPILE"
+goto done
+
+:ERRORSVF
+echo "ERROR SVF"
+goto done
+
+:ERRORSCP
+echo "ERROR SCP"
+goto done
+
+:ERRORPROG
+echo "ERROR PROGRAMM"
+
+:DONE
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:34:25 December 20, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "12:34:25 December 20, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "pistorm"
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:34:25 December 20, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# pistorm_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM570T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY pistorm
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:34:25 DECEMBER 20, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
+
+set_location_assignment PIN_12 -to PI_CLK
+set_location_assignment PIN_34 -to PI_UNUSED
+set_location_assignment PIN_28 -to PI_A[1]
+set_location_assignment PIN_27 -to PI_A[0]
+set_location_assignment PIN_2 -to PI_D[0]
+set_location_assignment PIN_3 -to PI_D[1]
+set_location_assignment PIN_4 -to PI_D[2]
+set_location_assignment PIN_5 -to PI_D[3]
+set_location_assignment PIN_6 -to PI_D[4]
+set_location_assignment PIN_7 -to PI_D[5]
+set_location_assignment PIN_26 -to PI_D[6]
+set_location_assignment PIN_21 -to PI_D[7]
+set_location_assignment PIN_17 -to PI_D[8]
+set_location_assignment PIN_16 -to PI_D[9]
+set_location_assignment PIN_20 -to PI_D[10]
+set_location_assignment PIN_8 -to PI_D[11]
+set_location_assignment PIN_15 -to PI_D[12]
+set_location_assignment PIN_14 -to PI_D[13]
+set_location_assignment PIN_19 -to PI_D[14]
+set_location_assignment PIN_18 -to PI_D[15]
+set_location_assignment PIN_30 -to PI_TXN_IN_PROGRESS
+set_location_assignment PIN_33 -to PI_IPL_ZERO
+set_location_assignment PIN_35 -to PI_RD
+set_location_assignment PIN_29 -to PI_WR
+
+set_location_assignment PIN_44 -to LTCH_A_0
+set_location_assignment PIN_42 -to LTCH_A_8
+set_location_assignment PIN_47 -to LTCH_A_16
+set_location_assignment PIN_48 -to LTCH_A_24
+set_location_assignment PIN_43 -to LTCH_A_OE_n
+set_location_assignment PIN_50 -to LTCH_D_RD_U
+set_location_assignment PIN_49 -to LTCH_D_RD_L
+set_location_assignment PIN_38 -to LTCH_D_RD_OE_n
+set_location_assignment PIN_36 -to LTCH_D_WR_U
+set_location_assignment PIN_40 -to LTCH_D_WR_L
+set_location_assignment PIN_41 -to LTCH_D_WR_OE_n
+
+set_location_assignment PIN_62 -to M68K_CLK
+set_location_assignment PIN_52 -to M68K_VMA_n
+set_location_assignment PIN_53 -to M68K_E
+set_location_assignment PIN_54 -to M68K_VPA_n
+set_location_assignment PIN_55 -to M68K_BERR_n
+set_location_assignment PIN_56 -to M68K_IPL_n[0]
+set_location_assignment PIN_57 -to M68K_FC[2]
+set_location_assignment PIN_58 -to M68K_IPL_n[1]
+set_location_assignment PIN_61 -to M68K_IPL_n[2]
+set_location_assignment PIN_64 -to M68K_FC[1]
+set_location_assignment PIN_66 -to M68K_FC[0]
+set_location_assignment PIN_67 -to M68K_RESET_n
+set_location_assignment PIN_68 -to M68K_HALT_n
+set_location_assignment PIN_69 -to M68K_BR_n
+set_location_assignment PIN_70 -to M68K_BGACK_n
+set_location_assignment PIN_71 -to M68K_BG_n
+set_location_assignment PIN_72 -to M68K_AS_n
+set_location_assignment PIN_73 -to M68K_UDS_n
+set_location_assignment PIN_74 -to M68K_LDS_n
+set_location_assignment PIN_75 -to M68K_RW
+set_location_assignment PIN_76 -to M68K_DTACK_n
+
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name SDC_FILE pistorm.sdc
+set_global_assignment -name VERILOG_FILE pistorm.v
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
\ No newline at end of file
--- /dev/null
+## Generated SDC file "pistorm.sdc"
+
+## Copyright (C) 2020 Intel Corporation. All rights reserved.
+## Your use of Intel Corporation's design tools, logic functions
+## and other software and tools, and any partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Intel Program License
+## Subscription Agreement, the Intel Quartus Prime License Agreement,
+## the Intel FPGA IP License Agreement, or other applicable license
+## agreement, including, without limitation, that your use is for
+## the sole purpose of programming logic devices manufactured by
+## Intel and sold by Intel or its authorized distributors. Please
+## refer to the applicable agreement for further details, at
+## https://fpgasoftware.intel.com/eula.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+
+## DATE "Sun Dec 20 15:18:48 2020"
+
+##
+## DEVICE "EPM570T100C5"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {PI_CLK} -period 5.000 [get_ports {PI_CLK}]
+create_clock -name {M68K_CLK} -period 141.000 [get_ports {M68K_CLK}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_ports {M68K_CLK M68K_DTACK_n M68K_VPA_n M68K_IPL_n[*] PI_A[*] PI_D[*] PI_RD PI_WR}]
+set_false_path -to [get_ports {LTCH_A_0 LTCH_A_8 LTCH_A_16 LTCH_A_24 LTCH_A_OE_n LTCH_D_RD_L LTCH_D_RD_OE_n LTCH_D_RD_U LTCH_D_WR_L LTCH_D_WR_OE_n LTCH_D_WR_U M68K_AS_n M68K_BG_n M68K_E M68K_FC[*] M68K_HALT_n M68K_LDS_n M68K_RESET_n M68K_RW M68K_UDS_n M68K_VMA_n PI_TXN_IN_PROGRESS PI_IPL_ZERO PI_D[*]}]
+
+set_false_path -from [get_clocks {M68K_CLK}] -to [get_clocks {PI_CLK}]
+set_false_path -from [get_clocks {PI_CLK}] -to [get_clocks {M68K_CLK}]
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
--- /dev/null
+/*
+ * Copyright 2020 Claude Schwarz
+ * Copyright 2020 Niklas Ekström - rewrite in Verilog
+ */
+module pistorm(
+ output reg PI_TXN_IN_PROGRESS, // GPIO0
+ output reg PI_IPL_ZERO, // GPIO1
+ input [1:0] PI_A, // GPIO[3..2]
+ input PI_CLK, // GPIO4
+ input PI_UNUSED, // GPIO5
+ input PI_RD, // GPIO6
+ input PI_WR, // GPIO7
+ inout [15:0] PI_D, // GPIO[23..8]
+
+ output reg LTCH_A_0,
+ output reg LTCH_A_8,
+ output reg LTCH_A_16,
+ output reg LTCH_A_24,
+ output reg LTCH_A_OE_n,
+ output reg LTCH_D_RD_U,
+ output reg LTCH_D_RD_L,
+ output reg LTCH_D_RD_OE_n,
+ output reg LTCH_D_WR_U,
+ output reg LTCH_D_WR_L,
+ output reg LTCH_D_WR_OE_n,
+
+ input M68K_CLK,
+ output reg [2:0] M68K_FC,
+
+ output reg M68K_AS_n,
+ output reg M68K_UDS_n,
+ output reg M68K_LDS_n,
+ output reg M68K_RW,
+
+ input M68K_DTACK_n,
+ input M68K_BERR_n,
+
+ input M68K_VPA_n,
+ output reg M68K_E,
+ output reg M68K_VMA_n,
+
+ input [2:0] M68K_IPL_n,
+
+ inout M68K_RESET_n,
+ inout M68K_HALT_n,
+
+ input M68K_BR_n,
+ output reg M68K_BG_n,
+ input M68K_BGACK_n
+ );
+
+ wire c200m = PI_CLK;
+ wire c7m = M68K_CLK;
+
+ localparam REG_DATA = 2'd0;
+ localparam REG_ADDR_LO = 2'd1;
+ localparam REG_ADDR_HI = 2'd2;
+ localparam REG_STATUS = 2'd3;
+
+ initial begin
+ PI_TXN_IN_PROGRESS <= 1'b0;
+ PI_IPL_ZERO <= 1'b0;
+
+ M68K_FC <= 3'd0;
+
+ M68K_RW <= 1'b1;
+
+ M68K_E <= 1'b0;
+ M68K_VMA_n <= 1'b1;
+
+ M68K_BG_n <= 1'b1;
+ end
+
+ reg [1:0] rd_sync;
+ reg [1:0] wr_sync;
+
+ always @(posedge c200m) begin
+ rd_sync <= {rd_sync[0], PI_RD};
+ wr_sync <= {wr_sync[0], PI_WR};
+ end
+
+ wire rd_rising = !rd_sync[1] && rd_sync[0];
+ wire wr_rising = !wr_sync[1] && wr_sync[0];
+
+ reg [15:0] data_out;
+ assign PI_D = PI_A == REG_STATUS && PI_RD ? data_out : 16'bz;
+
+ always @(posedge c200m) begin
+ if (rd_rising && PI_A == REG_STATUS) begin
+ data_out <= {ipl, 13'd0};
+ end
+ end
+
+ reg [15:0] status;
+ wire reset_out = !status[1];
+
+ assign M68K_RESET_n = reset_out ? 1'b0 : 1'bz;
+ assign M68K_HALT_n = reset_out ? 1'b0 : 1'bz;
+
+ reg op_req = 1'b0;
+ reg op_rw = 1'b1;
+ reg op_uds_n = 1'b1;
+ reg op_lds_n = 1'b1;
+
+ always @(*) begin
+ LTCH_D_WR_U <= PI_A == REG_DATA && PI_WR;
+ LTCH_D_WR_L <= PI_A == REG_DATA && PI_WR;
+
+ LTCH_A_0 <= PI_A == REG_ADDR_LO && PI_WR;
+ LTCH_A_8 <= PI_A == REG_ADDR_LO && PI_WR;
+
+ LTCH_A_16 <= PI_A == REG_ADDR_HI && PI_WR;
+ LTCH_A_24 <= PI_A == REG_ADDR_HI && PI_WR;
+
+ LTCH_D_RD_OE_n <= !(PI_A == REG_DATA && PI_RD);
+ end
+
+ reg [2:0] s1_sync;
+ reg [2:0] s7_sync;
+
+ always @(posedge c200m) begin
+ s1_sync <= {s1_sync[1:0], S1};
+ s7_sync <= {s7_sync[1:0], S7};
+ end
+
+ wire rising_s1 = !s1_sync[2] && s1_sync[1];
+ wire rising_s7 = !s7_sync[2] && s7_sync[1];
+
+ reg a0;
+
+ always @(posedge c200m) begin
+ if (rising_s1)
+ op_req <= 1'b0;
+
+ if (rising_s7)
+ PI_TXN_IN_PROGRESS <= 1'b0;
+
+ if (wr_rising) begin
+ case (PI_A)
+ REG_ADDR_LO: begin
+ a0 <= PI_D[0];
+ PI_TXN_IN_PROGRESS <= 1'b1;
+ end
+ REG_ADDR_HI: begin
+ op_req <= 1'b1;
+ op_rw <= PI_D[9];
+ op_uds_n <= PI_D[8] ? a0 : 1'b0;
+ op_lds_n <= PI_D[8] ? !a0 : 1'b0;
+ end
+ REG_STATUS: begin
+ status <= PI_D;
+ end
+ endcase
+ end
+ end
+
+ reg [2:0] c7m_sync;
+
+ always @(posedge c200m) begin
+ c7m_sync <= {c7m_sync[1:0], M68K_CLK};
+ end
+
+ wire c7m_rising = !c7m_sync[2] && c7m_sync[1];
+ wire c7m_falling = c7m_sync[2] && !c7m_sync[1];
+
+ reg [2:0] ipl;
+ reg [2:0] ipl_1;
+ reg [2:0] ipl_2;
+
+ always @(posedge c200m) begin
+ if (c7m_falling) begin
+ ipl_1 <= ~M68K_IPL_n;
+ ipl_2 <= ipl_1;
+ end
+
+ if (ipl_2 == ipl_1)
+ ipl <= ipl_2;
+
+ PI_IPL_ZERO <= ipl == 3'd0;
+ end
+
+ reg [3:0] e_counter = 4'd0;
+
+ always @(negedge c7m) begin
+ if (e_counter == 4'd9)
+ e_counter <= 4'd0;
+ else
+ e_counter <= e_counter + 4'd1;
+ end
+
+ always @(negedge c7m) begin
+ if (e_counter == 4'd9)
+ M68K_E <= 1'b0;
+ else if (e_counter == 4'd5)
+ M68K_E <= 1'b1;
+ end
+
+ reg [1:0] state = 2'd0;
+ reg wait_req = 1'b1;
+ reg wait_dtack = 1'b0;
+
+ wire S0 = state == 2'd0 && c7m && !wait_req;
+ wire Sr = state == 2'd0 && wait_req;
+ wire S1 = state == 2'd1 && !c7m;
+ wire S2 = state == 2'd1 && c7m;
+ wire S3 = state == 2'd2 && !c7m && !wait_dtack;
+ wire S4 = state == 2'd2 && c7m && !wait_dtack;
+ wire Sw = state == 2'd2 && wait_dtack;
+ wire S5 = state == 2'd3 && !c7m;
+ wire S6 = state == 2'd3 && c7m;
+ wire S7 = state == 2'd0 && !c7m && !wait_req;
+
+ always @(*) begin
+ LTCH_A_OE_n <= !(S1 || S2 || S3 || S4 || Sw || S5 || S6 || S7);
+ LTCH_D_WR_OE_n <= !(!op_rw && (S3 || S4 || Sw || S5 || S6 || S7));
+
+ LTCH_D_RD_U <= S7;
+ LTCH_D_RD_L <= S7;
+
+ M68K_AS_n <= !(S2 || S3 || S4 || Sw || S5 || S6);
+ M68K_UDS_n <= (op_rw && (S2 || S3)) || (S4 || Sw || S5 || S6) ? op_uds_n : 1'b1;
+ M68K_LDS_n <= (op_rw && (S2 || S3)) || (S4 || Sw || S5 || S6) ? op_lds_n : 1'b1;
+ end
+
+ always @(negedge c7m) begin
+ case (state)
+ 2'd0: begin // S0|Sr -> S1|Sr
+ if (op_req_sync) begin
+ wait_req <= 1'b0;
+ state <= state + 2'd1;
+ end
+ else begin
+ wait_req <= 1'b1;
+ end
+ end
+
+ 2'd1: begin // S2 -> S3
+ state <= state + 2'd1;
+ end
+
+ 2'd2: begin // S4|Sw -> S5|Sw
+ if (!M68K_DTACK_n || (!M68K_VMA_n && e_counter == 4'd8)) begin
+ wait_dtack <= 1'b0;
+ state <= state + 2'd1;
+ end
+ else begin
+ if (!M68K_VPA_n && e_counter == 4'd2) begin
+ M68K_VMA_n <= 1'b0;
+ end
+ wait_dtack <= 1'b1;
+ end
+ end
+
+ 2'd3: begin // S6 -> S7
+ M68K_VMA_n <= 1'b1;
+ state <= state + 2'd1;
+ end
+ endcase
+ end
+
+ reg op_req_sync;
+
+ always @(posedge c7m) begin
+ op_req_sync <= op_req;
+
+ case (state)
+ 2'd0: M68K_RW <= 1'b1; // S7 -> S0
+ 2'd1: M68K_RW <= op_rw; // S1 -> S2
+ endcase
+ end
+
+endmodule
+++ /dev/null
-taskset 0x8 sudo ./emulator
=============================================================================*/
-#include "../m68kcpu.h" // which includes softfloat.h after defining the basic types
+#include "m68kcpu.h" // which includes softfloat.h after defining the basic types
/*----------------------------------------------------------------------------
| Floating-point rounding mode, extended double-precision rounding precision,
projects / pistorm / commitdiff