1 /*****************************************************************************
3 *****************************************************************************
4 * Copyright (C) 2003-2012 x264 project
6 * Authors: Loren Merritt <lorenm@u.washington.edu>
7 * Laurent Aimar <fenrir@via.ecp.fr>
8 * Fiona Glaser <fiona@x264.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
24 * This program is also available under a commercial proprietary license.
25 * For more information, contact us at licensing@x264.com.
26 *****************************************************************************/
28 #define _GNU_SOURCE // for sched_getaffinity
32 #if HAVE_POSIXTHREAD && SYS_LINUX
36 #include <kernel/OS.h>
38 #if SYS_MACOSX || SYS_FREEBSD
39 #include <sys/types.h>
40 #include <sys/sysctl.h>
43 #include <sys/param.h>
44 #include <sys/sysctl.h>
45 #include <machine/cpu.h>
48 const x264_cpu_name_t x264_cpu_names[] =
50 {"Altivec", X264_CPU_ALTIVEC},
51 // {"MMX", X264_CPU_MMX}, // we don't support asm on mmx1 cpus anymore
52 {"MMX2", X264_CPU_MMX|X264_CPU_MMX2},
53 {"MMXEXT", X264_CPU_MMX|X264_CPU_MMX2},
54 // {"SSE", X264_CPU_MMX|X264_CPU_MMX2|X264_CPU_SSE}, // there are no sse1 functions in x264
55 #define SSE2 X264_CPU_MMX|X264_CPU_MMX2|X264_CPU_SSE|X264_CPU_SSE2
56 {"SSE2Slow", SSE2|X264_CPU_SSE2_IS_SLOW},
58 {"SSE2Fast", SSE2|X264_CPU_SSE2_IS_FAST},
59 {"SSE3", SSE2|X264_CPU_SSE3},
60 {"SSSE3", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3},
61 {"FastShuffle", SSE2|X264_CPU_SHUFFLE_IS_FAST},
62 {"SSE4.1", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4},
63 {"SSE4", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4},
64 {"SSE4.2", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42},
65 {"AVX", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42|X264_CPU_AVX},
66 {"XOP", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42|X264_CPU_AVX|X264_CPU_XOP},
67 {"FMA4", SSE2|X264_CPU_SSE3|X264_CPU_SSSE3|X264_CPU_SSE4|X264_CPU_SSE42|X264_CPU_AVX|X264_CPU_FMA4},
69 {"Cache32", X264_CPU_CACHELINE_32},
70 {"Cache64", X264_CPU_CACHELINE_64},
71 {"SSEMisalign", X264_CPU_SSE_MISALIGN},
72 {"LZCNT", X264_CPU_LZCNT},
73 {"Slow_mod4_stack", X264_CPU_STACK_MOD4},
74 {"ARMv6", X264_CPU_ARMV6},
75 {"NEON", X264_CPU_NEON},
76 {"Fast_NEON_MRC", X264_CPU_FAST_NEON_MRC},
77 {"SlowCTZ", X264_CPU_SLOW_CTZ},
78 {"SlowAtom", X264_CPU_SLOW_ATOM},
82 #if (ARCH_PPC && SYS_LINUX) || (ARCH_ARM && !HAVE_NEON)
85 static sigjmp_buf jmpbuf;
86 static volatile sig_atomic_t canjump = 0;
88 static void sigill_handler( int sig )
92 signal( sig, SIG_DFL );
97 siglongjmp( jmpbuf, 1 );
102 int x264_cpu_cpuid_test( void );
103 void x264_cpu_cpuid( uint32_t op, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx );
104 void x264_cpu_xgetbv( uint32_t op, uint32_t *eax, uint32_t *edx );
106 uint32_t x264_cpu_detect( void )
109 uint32_t eax, ebx, ecx, edx;
110 uint32_t vendor[4] = {0};
111 uint32_t max_extended_cap;
115 if( !x264_cpu_cpuid_test() )
119 x264_cpu_cpuid( 0, &eax, vendor+0, vendor+2, vendor+1 );
123 x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
129 cpu |= X264_CPU_MMX2|X264_CPU_SSE;
131 cpu |= X264_CPU_SSE2;
133 cpu |= X264_CPU_SSE3;
135 cpu |= X264_CPU_SSSE3;
137 cpu |= X264_CPU_SSE4;
139 cpu |= X264_CPU_SSE42;
140 /* Check OXSAVE and AVX bits */
141 if( (ecx&0x18000000) == 0x18000000 )
143 /* Check for OS support */
144 x264_cpu_xgetbv( 0, &eax, &edx );
145 if( (eax&0x6) == 0x6 )
149 if( cpu & X264_CPU_SSSE3 )
150 cpu |= X264_CPU_SSE2_IS_FAST;
151 if( cpu & X264_CPU_SSE4 )
152 cpu |= X264_CPU_SHUFFLE_IS_FAST;
154 x264_cpu_cpuid( 0x80000000, &eax, &ebx, &ecx, &edx );
155 max_extended_cap = eax;
157 if( !strcmp((char*)vendor, "AuthenticAMD") && max_extended_cap >= 0x80000001 )
159 cpu |= X264_CPU_SLOW_CTZ;
160 x264_cpu_cpuid( 0x80000001, &eax, &ebx, &ecx, &edx );
162 cpu |= X264_CPU_MMX2;
163 if( cpu & X264_CPU_SSE2 )
165 if( ecx&0x00000040 ) /* SSE4a */
167 cpu |= X264_CPU_SSE2_IS_FAST;
168 cpu |= X264_CPU_LZCNT;
169 cpu |= X264_CPU_SHUFFLE_IS_FAST;
170 cpu &= ~X264_CPU_SLOW_CTZ;
173 cpu |= X264_CPU_SSE2_IS_SLOW;
175 if( ecx&0x00000080 ) /* Misalign SSE */
177 cpu |= X264_CPU_SSE_MISALIGN;
178 x264_cpu_mask_misalign_sse();
181 if( cpu & X264_CPU_AVX )
183 if( ecx&0x00000800 ) /* XOP */
185 if( ecx&0x00010000 ) /* FMA4 */
186 cpu |= X264_CPU_FMA4;
191 if( !strcmp((char*)vendor, "GenuineIntel") )
193 x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
194 int family = ((eax>>8)&0xf) + ((eax>>20)&0xff);
195 int model = ((eax>>4)&0xf) + ((eax>>12)&0xf0);
198 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
199 * theoretically support sse2, but it's significantly slower than mmx for
200 * almost all of x264's functions, so let's just pretend they don't. */
201 if( model == 9 || model == 13 || model == 14 )
203 cpu &= ~(X264_CPU_SSE2|X264_CPU_SSE3);
204 assert(!(cpu&(X264_CPU_SSSE3|X264_CPU_SSE4)));
206 /* Detect Atom CPU */
207 else if( model == 28 )
209 cpu |= X264_CPU_SLOW_ATOM;
210 cpu |= X264_CPU_SLOW_CTZ;
212 /* Some Penryns and Nehalems are pointlessly crippled (SSE4 disabled), so
213 * detect them here. */
214 else if( model >= 23 )
215 cpu |= X264_CPU_SHUFFLE_IS_FAST;
219 if( (!strcmp((char*)vendor, "GenuineIntel") || !strcmp((char*)vendor, "CyrixInstead")) && !(cpu&X264_CPU_SSE42))
221 /* cacheline size is specified in 3 places, any of which may be missing */
222 x264_cpu_cpuid( 1, &eax, &ebx, &ecx, &edx );
223 cache = (ebx&0xff00)>>5; // cflush size
224 if( !cache && max_extended_cap >= 0x80000006 )
226 x264_cpu_cpuid( 0x80000006, &eax, &ebx, &ecx, &edx );
227 cache = ecx&0xff; // cacheline size
231 // Cache and TLB Information
232 static const char cache32_ids[] = { 0x0a, 0x0c, 0x41, 0x42, 0x43, 0x44, 0x45, 0x82, 0x83, 0x84, 0x85, 0 };
233 static const char cache64_ids[] = { 0x22, 0x23, 0x25, 0x29, 0x2c, 0x46, 0x47, 0x49, 0x60, 0x66, 0x67,
234 0x68, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7c, 0x7f, 0x86, 0x87, 0 };
238 x264_cpu_cpuid( 2, buf+0, buf+1, buf+2, buf+3 );
241 for( int j = 0; j < 4; j++ )
245 if( strchr( cache32_ids, buf[j]&0xff ) )
247 if( strchr( cache64_ids, buf[j]&0xff ) )
251 } while( ++i < max );
255 cpu |= X264_CPU_CACHELINE_32;
256 else if( cache == 64 )
257 cpu |= X264_CPU_CACHELINE_64;
259 x264_log( NULL, X264_LOG_WARNING, "unable to determine cacheline size\n" );
262 #if BROKEN_STACK_ALIGNMENT
263 cpu |= X264_CPU_STACK_MOD4;
271 #if SYS_MACOSX || SYS_OPENBSD
272 #include <sys/sysctl.h>
273 uint32_t x264_cpu_detect( void )
278 int selectors[2] = { CTL_MACHDEP, CPU_ALTIVEC };
280 int selectors[2] = { CTL_HW, HW_VECTORUNIT };
283 size_t length = sizeof( has_altivec );
284 int error = sysctl( selectors, 2, &has_altivec, &length, NULL, 0 );
286 if( error == 0 && has_altivec != 0 )
287 cpu |= X264_CPU_ALTIVEC;
294 uint32_t x264_cpu_detect( void )
296 static void (*oldsig)( int );
298 oldsig = signal( SIGILL, sigill_handler );
299 if( sigsetjmp( jmpbuf, 1 ) )
301 signal( SIGILL, oldsig );
306 asm volatile( "mtspr 256, %0\n\t"
312 signal( SIGILL, oldsig );
314 return X264_CPU_ALTIVEC;
320 void x264_cpu_neon_test( void );
321 int x264_cpu_fast_neon_mrc_test( void );
323 uint32_t x264_cpu_detect( void )
327 flags |= X264_CPU_ARMV6;
329 // don't do this hack if compiled with -mfpu=neon
331 static void (* oldsig)( int );
332 oldsig = signal( SIGILL, sigill_handler );
333 if( sigsetjmp( jmpbuf, 1 ) )
335 signal( SIGILL, oldsig );
340 x264_cpu_neon_test();
342 signal( SIGILL, oldsig );
345 flags |= X264_CPU_NEON;
347 // fast neon -> arm (Cortex-A9) detection relies on user access to the
348 // cycle counter; this assumes ARMv7 performance counters.
349 // NEON requires at least ARMv7, ARMv8 may require changes here, but
350 // hopefully this hacky detection method will have been replaced by then.
351 // Note that there is potential for a race condition if another program or
352 // x264 instance disables or reinits the counters while x264 is using them,
353 // which may result in incorrect detection and the counters stuck enabled.
354 flags |= x264_cpu_fast_neon_mrc_test() ? X264_CPU_FAST_NEON_MRC : 0;
355 // TODO: write dual issue test? currently it's A8 (dual issue) vs. A9 (fast mrc)
362 uint32_t x264_cpu_detect( void )
369 int x264_cpu_num_processors( void )
375 return x264_pthread_num_processors_np();
378 return sysconf( _SC_NPROCESSORS_ONLN );
382 memset( &p_aff, 0, sizeof(p_aff) );
383 if( sched_getaffinity( 0, sizeof(p_aff), &p_aff ) )
386 return CPU_COUNT(&p_aff);
389 for( unsigned int bit = 0; bit < 8 * sizeof(p_aff); bit++ )
390 np += (((uint8_t *)&p_aff)[bit / 8] >> (bit % 8)) & 1;
396 get_system_info( &info );
397 return info.cpu_count;
399 #elif SYS_MACOSX || SYS_FREEBSD || SYS_OPENBSD
401 size_t length = sizeof( ncpu );
403 int mib[2] = { CTL_HW, HW_NCPU };
404 if( sysctl(mib, 2, &ncpu, &length, NULL, 0) )
406 if( sysctlbyname("hw.ncpu", &ncpu, &length, NULL, 0) )