1 ;*****************************************************************************
2 ;* dct-32.asm: h264 encoder library
3 ;*****************************************************************************
4 ;* Copyright (C) 2003-2008 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Holger Lubitz <holger@lubitz.org>
8 ;* Laurent Aimar <fenrir@via.ecp.fr>
9 ;* Min Chen <chenm001.163.com>
10 ;* Christian Heine <sennindemokrit@gmx.net>
12 ;* This program is free software; you can redistribute it and/or modify
13 ;* it under the terms of the GNU General Public License as published by
14 ;* the Free Software Foundation; either version 2 of the License, or
15 ;* (at your option) any later version.
17 ;* This program is distributed in the hope that it will be useful,
18 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;* GNU General Public License for more details.
22 ;* You should have received a copy of the GNU General Public License
23 ;* along with this program; if not, write to the Free Software
24 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
25 ;*****************************************************************************
28 %include "x86util.asm"
33 hsub_mul: times 8 db 1, -1
38 ; out: 0,4,6 in mem, rest in regs
40 SUMSUB_BA m%8, m%1 ; %8 = s07, %1 = d07
41 SUMSUB_BA m%7, m%2 ; %7 = s16, %2 = d16
42 SUMSUB_BA m%6, m%3 ; %6 = s25, %3 = d25
43 SUMSUB_BA m%5, m%4 ; %5 = s34, %4 = d34
44 SUMSUB_BA m%5, m%8 ; %5 = a0, %8 = a2
45 SUMSUB_BA m%6, m%7 ; %6 = a1, %7 = a3
46 SUMSUB_BA m%6, m%5 ; %6 = dst0, %5 = dst4
51 paddw m%6, m%8 ; a2 + (a3>>1)
53 psubw m%8, m%7 ; (a2>>1) - a3
57 paddw m%5, m%3 ; d25+(d25>>1)
59 psubw m%7, m%4 ; a5 = d07-d34-(d25+(d25>>1))
63 paddw m%5, m%2 ; d16+(d16>>1)
66 psubw m%8, m%5 ; a6 = d07+d34-(d16+(d16>>1))
69 paddw m%5, m%1 ; d07+(d07>>1)
71 paddw m%5, m%3 ; a4 = d16+d25+(d07+(d07>>1))
74 paddw m%1, m%4 ; d34+(d34>>1)
76 psubw m%1, m%3 ; a7 = d16-d25+(d34+(d34>>1))
79 paddw m%4, m%5 ; a4 + (a7>>2)
82 paddw m%3, m%7 ; a5 + (a6>>2)
85 psubw m%5, m%1 ; (a4>>2) - a7
86 psubw m%8, m%7 ; a6 - (a5>>2)
87 SWAP %2, %4, %3, %6, %8, %5
90 ; in: 0,4 in mem, rest in regs
143 LOAD_DIFF m0, m7, none, [r1+0*FENC_STRIDE], [r2+0*FDEC_STRIDE]
144 LOAD_DIFF m1, m7, none, [r1+1*FENC_STRIDE], [r2+1*FDEC_STRIDE]
145 LOAD_DIFF m2, m7, none, [r1+2*FENC_STRIDE], [r2+2*FDEC_STRIDE]
146 LOAD_DIFF m3, m7, none, [r1+3*FENC_STRIDE], [r2+3*FDEC_STRIDE]
147 LOAD_DIFF m4, m7, none, [r1+4*FENC_STRIDE], [r2+4*FDEC_STRIDE]
148 LOAD_DIFF m5, m7, none, [r1+5*FENC_STRIDE], [r2+5*FDEC_STRIDE]
150 LOAD_DIFF m6, m7, none, [r1+6*FENC_STRIDE], [r2+6*FDEC_STRIDE]
151 LOAD_DIFF m7, m0, none, [r1+7*FENC_STRIDE], [r2+7*FDEC_STRIDE]
158 DCT8_1D 0,1,2,3,4,5,6,7,r0
159 SAVE_MM_PERMUTATION dct8_mmx
162 %macro SPILL_SHUFFLE 3-* ; ptr, list of regs, list of memory offsets
167 mova [%%base + %2*16], %%tmp
172 %macro UNSPILL_SHUFFLE 3-*
177 mova %%tmp, [%%base + %2*16]
182 %macro SPILL 2+ ; assume offsets are the same as reg numbers
183 SPILL_SHUFFLE %1, %2, %2
187 UNSPILL_SHUFFLE %1, %2, %2
190 ;-----------------------------------------------------------------------------
191 ; void x264_sub8x8_dct8_mmx( int16_t dct[8][8], uint8_t *pix1, uint8_t *pix2 )
192 ;-----------------------------------------------------------------------------
193 cglobal x264_sub8x8_dct8_mmx, 3,3
194 global x264_sub8x8_dct8_mmx.skip_prologue
197 call load_diff_4x8_mmx
200 TRANSPOSE4x4W 0,1,2,3,4
203 TRANSPOSE4x4W 4,5,6,7,0
209 call load_diff_4x8_mmx
215 TRANSPOSE4x4W 4,5,6,7,0
218 TRANSPOSE4x4W 0,1,2,3,5
220 SPILL_SHUFFLE r0, 0,1,2,3, 4,5,6,7
221 movq mm4, m6 ; depends on the permutation to not produce conflicts
227 UNSPILL r0+8, 4,5,6,7
231 SPILL r0+8, 1,2,3,5,7
233 UNSPILL r0, 0,1,2,3,4,5,6,7
241 IDCT8_1D 0,1,2,3,4,5,6,7,r1
242 SAVE_MM_PERMUTATION idct8_mmx
245 %macro ADD_STORE_ROW 3
246 movq m1, [r0+%1*FDEC_STRIDE]
253 movq [r0+%1*FDEC_STRIDE], m1
256 ;-----------------------------------------------------------------------------
257 ; void x264_add8x8_idct8_mmx( uint8_t *dst, int16_t dct[8][8] )
258 ;-----------------------------------------------------------------------------
259 cglobal x264_add8x8_idct8_mmx, 2,2
260 global x264_add8x8_idct8_mmx.skip_prologue
264 UNSPILL r1, 1,2,3,5,6,7
267 TRANSPOSE4x4W 0,1,2,3,7
270 TRANSPOSE4x4W 4,5,6,7,0
273 UNSPILL r1+8, 1,2,3,5,6,7
278 TRANSPOSE4x4W 0,1,2,3,7
281 TRANSPOSE4x4W 4,5,6,7,0
288 ; memory layout at this time:
297 UNSPILL_SHUFFLE r1, 1,2,3, 5,6,7
310 movq [r1+0x08], m0 ; mm4
311 movq [r1+0x48], m4 ; mm5
312 movq [r1+0x58], m5 ; mm0
313 movq [r1+0x68], m6 ; mm2
314 movq [r1+0x78], m7 ; mm6
317 movq [r1+0x18], m1 ; mm1
318 movq [r1+0x28], m2 ; mm7
320 movq [r1+0x38], m3 ; mm3
335 ADD_STORE_ROW 0, [r1+0x00], [r1+0x08]
336 ADD_STORE_ROW 1, [r1+0x10], [r1+0x18]
337 ADD_STORE_ROW 2, [r1+0x20], [r1+0x28]
338 ADD_STORE_ROW 3, m3, [r1+0x38]
339 ADD_STORE_ROW 4, m4, [r1+0x48]
340 ADD_STORE_ROW 5, m5, [r1+0x58]
341 ADD_STORE_ROW 6, m6, [r1+0x68]
342 ADD_STORE_ROW 7, m7, [r1+0x78]
347 cglobal x264_sub8x8_dct_%1, 3,3
348 add r2, 4*FDEC_STRIDE
349 global x264_sub8x8_dct_%1.skip_prologue
354 LOAD_DIFF8x4 0, 1, 2, 3, 6, 7, r1, r2-4*FDEC_STRIDE
357 LOAD_DIFF8x4 4, 5, 6, 7, 1, 2, r1, r2-4*FDEC_STRIDE
362 DCT4_1D 0, 1, 2, 3, 7
363 TRANSPOSE2x4x4W 0, 1, 2, 3, 7
366 DCT4_1D 4, 5, 6, 7, 2
367 TRANSPOSE2x4x4W 4, 5, 6, 7, 2
370 DCT4_1D 0, 1, 2, 3, 6
372 STORE_DCT 0, 1, 2, 3, r0, 0
373 DCT4_1D 4, 5, 6, 7, 3
374 STORE_DCT 4, 5, 6, 7, r0, 64
377 ;-----------------------------------------------------------------------------
378 ; void x264_sub8x8_dct8_sse2( int16_t dct[8][8], uint8_t *pix1, uint8_t *pix2 )
379 ;-----------------------------------------------------------------------------
380 cglobal x264_sub8x8_dct8_%1, 3,3
381 add r2, 4*FDEC_STRIDE
382 global x264_sub8x8_dct8_%1.skip_prologue
385 LOAD_DIFF m0, m7, none, [r1+0*FENC_STRIDE], [r2-4*FDEC_STRIDE]
386 LOAD_DIFF m1, m7, none, [r1+1*FENC_STRIDE], [r2-3*FDEC_STRIDE]
387 LOAD_DIFF m2, m7, none, [r1+2*FENC_STRIDE], [r2-2*FDEC_STRIDE]
388 LOAD_DIFF m3, m7, none, [r1+3*FENC_STRIDE], [r2-1*FDEC_STRIDE]
389 LOAD_DIFF m4, m7, none, [r1+4*FENC_STRIDE], [r2+0*FDEC_STRIDE]
390 LOAD_DIFF m5, m7, none, [r1+5*FENC_STRIDE], [r2+1*FDEC_STRIDE]
392 LOAD_DIFF m6, m7, none, [r1+6*FENC_STRIDE], [r2+2*FDEC_STRIDE]
393 LOAD_DIFF m7, m0, none, [r1+7*FENC_STRIDE], [r2+3*FDEC_STRIDE]
397 LOAD_DIFF8x4 0, 1, 2, 3, 4, 7, r1, r2-4*FDEC_STRIDE
400 LOAD_DIFF8x4 4, 5, 6, 7, 0, 1, r1, r2-4*FDEC_STRIDE
403 DCT8_1D 0,1,2,3,4,5,6,7,r0
405 TRANSPOSE8x8W 0,1,2,3,4,5,6,7,[r0+0x60],[r0+0x40],1
407 DCT8_1D 0,1,2,3,4,5,6,7,r0
412 %define LOAD_DIFF8x4 LOAD_DIFF8x4_SSE2
413 %define movdqa movaps
414 %define punpcklqdq movlhps
418 %define LOAD_DIFF8x4 LOAD_DIFF8x4_SSSE3
421 ;-----------------------------------------------------------------------------
422 ; void x264_add8x8_idct_sse2( uint8_t *pix, int16_t dct[4][4][4] )
423 ;-----------------------------------------------------------------------------
424 cglobal x264_add8x8_idct_sse2, 2,2
425 add r0, 4*FDEC_STRIDE
426 global x264_add8x8_idct_sse2.skip_prologue
428 UNSPILL_SHUFFLE r1, 0,2,1,3, 0,1,2,3
429 SBUTTERFLY qdq, 0, 1, 4
430 SBUTTERFLY qdq, 2, 3, 4
431 UNSPILL_SHUFFLE r1, 4,6,5,7, 4,5,6,7
433 SBUTTERFLY qdq, 4, 5, 0
434 SBUTTERFLY qdq, 6, 7, 0
438 TRANSPOSE2x4x4W 0,1,2,3,4
442 TRANSPOSE2x4x4W 4,5,6,7,0
450 DIFFx2 m0, m1, m6, m7, [r0-4*FDEC_STRIDE], [r0-3*FDEC_STRIDE]; m5
451 DIFFx2 m2, m3, m6, m7, [r0-2*FDEC_STRIDE], [r0-1*FDEC_STRIDE]; m5
452 UNSPILL_SHUFFLE r1, 0,2, 6,7
453 DIFFx2 m4, m5, m6, m7, [r0+0*FDEC_STRIDE], [r0+1*FDEC_STRIDE]; m5
454 DIFFx2 m0, m2, m6, m7, [r0+2*FDEC_STRIDE], [r0+3*FDEC_STRIDE]; m5
455 STORE_IDCT m1, m3, m5, m2
458 ;-----------------------------------------------------------------------------
459 ; void x264_add8x8_idct8_sse2( uint8_t *p_dst, int16_t dct[8][8] )
460 ;-----------------------------------------------------------------------------
461 cglobal x264_add8x8_idct8_sse2, 2,2
462 add r0, 4*FDEC_STRIDE
463 global x264_add8x8_idct8_sse2.skip_prologue
465 UNSPILL r1, 1,2,3,5,6,7
466 IDCT8_1D 0,1,2,3,4,5,6,7,r1
468 TRANSPOSE8x8W 0,1,2,3,4,5,6,7,[r1+0x60],[r1+0x40],1
471 IDCT8_1D 0,1,2,3,4,5,6,7,r1
474 DIFFx2 m0, m1, m6, m7, [r0-4*FDEC_STRIDE], [r0-3*FDEC_STRIDE]; m5
475 DIFFx2 m2, m3, m6, m7, [r0-2*FDEC_STRIDE], [r0-1*FDEC_STRIDE]; m5
476 UNSPILL_SHUFFLE r1, 0,2, 6,7
477 DIFFx2 m4, m5, m6, m7, [r0+0*FDEC_STRIDE], [r0+1*FDEC_STRIDE]; m5
478 DIFFx2 m0, m2, m6, m7, [r0+2*FDEC_STRIDE], [r0+3*FDEC_STRIDE]; m5
479 STORE_IDCT m1, m3, m5, m2