1 ;*****************************************************************************
2 ;* dct-32.asm: x86_32 transform and zigzag
3 ;*****************************************************************************
4 ;* Copyright (C) 2003-2011 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Holger Lubitz <holger@lubitz.org>
8 ;* Laurent Aimar <fenrir@via.ecp.fr>
9 ;* Min Chen <chenm001.163.com>
10 ;* Christian Heine <sennindemokrit@gmx.net>
12 ;* This program is free software; you can redistribute it and/or modify
13 ;* it under the terms of the GNU General Public License as published by
14 ;* the Free Software Foundation; either version 2 of the License, or
15 ;* (at your option) any later version.
17 ;* This program is distributed in the hope that it will be useful,
18 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;* GNU General Public License for more details.
22 ;* You should have received a copy of the GNU General Public License
23 ;* along with this program; if not, write to the Free Software
24 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
26 ;* This program is also available under a commercial proprietary license.
27 ;* For more information, contact us at licensing@x264.com.
28 ;*****************************************************************************
31 %include "x86util.asm"
35 %ifndef HIGH_BIT_DEPTH
40 ; out: 0,4,6 in mem, rest in regs
42 SUMSUB_BA w, %8, %1 ; %8 = s07, %1 = d07
43 SUMSUB_BA w, %7, %2 ; %7 = s16, %2 = d16
44 SUMSUB_BA w, %6, %3 ; %6 = s25, %3 = d25
45 SUMSUB_BA w, %5, %4 ; %5 = s34, %4 = d34
46 SUMSUB_BA w, %5, %8 ; %5 = a0, %8 = a2
47 SUMSUB_BA w, %6, %7 ; %6 = a1, %7 = a3
48 SUMSUB_BA w, %6, %5 ; %6 = dst0, %5 = dst4
51 psraw m%6, m%7, 1 ; a3>>1
52 paddw m%6, m%8 ; a2 + (a3>>1)
54 psubw m%8, m%7 ; (a2>>1) - a3
57 paddw m%5, m%3 ; d25+(d25>>1)
58 psubw m%7, m%1, m%4 ; a5 = d07-d34-(d25+(d25>>1))
61 paddw m%5, m%2 ; d16+(d16>>1)
63 psubw m%8, m%5 ; a6 = d07+d34-(d16+(d16>>1))
65 paddw m%5, m%1 ; d07+(d07>>1)
67 paddw m%5, m%3 ; a4 = d16+d25+(d07+(d07>>1))
69 paddw m%1, m%4 ; d34+(d34>>1)
71 psubw m%1, m%3 ; a7 = d16-d25+(d34+(d34>>1))
73 paddw m%4, m%5 ; a4 + (a7>>2)
75 paddw m%3, m%7 ; a5 + (a6>>2)
78 psubw m%5, m%1 ; (a4>>2) - a7
79 psubw m%8, m%7 ; a6 - (a5>>2)
80 SWAP %2, %4, %3, %6, %8, %5
83 ; in: 0,4 in mem, rest in regs
132 LOAD_DIFF m0, m7, none, [r1+0*FENC_STRIDE], [r2+0*FDEC_STRIDE]
133 LOAD_DIFF m1, m7, none, [r1+1*FENC_STRIDE], [r2+1*FDEC_STRIDE]
134 LOAD_DIFF m2, m7, none, [r1+2*FENC_STRIDE], [r2+2*FDEC_STRIDE]
135 LOAD_DIFF m3, m7, none, [r1+3*FENC_STRIDE], [r2+3*FDEC_STRIDE]
136 LOAD_DIFF m4, m7, none, [r1+4*FENC_STRIDE], [r2+4*FDEC_STRIDE]
137 LOAD_DIFF m5, m7, none, [r1+5*FENC_STRIDE], [r2+5*FDEC_STRIDE]
139 LOAD_DIFF m6, m7, none, [r1+6*FENC_STRIDE], [r2+6*FDEC_STRIDE]
140 LOAD_DIFF m7, m0, none, [r1+7*FENC_STRIDE], [r2+7*FDEC_STRIDE]
145 DCT8_1D 0,1,2,3,4,5,6,7,r0
149 %macro SPILL_SHUFFLE 3-* ; ptr, list of regs, list of memory offsets
154 mova [%%base + %2*16], %%tmp
159 %macro UNSPILL_SHUFFLE 3-*
164 mova %%tmp, [%%base + %2*16]
169 %macro SPILL 2+ ; assume offsets are the same as reg numbers
170 SPILL_SHUFFLE %1, %2, %2
174 UNSPILL_SHUFFLE %1, %2, %2
177 ;-----------------------------------------------------------------------------
178 ; void sub8x8_dct8( int16_t dct[8][8], uint8_t *pix1, uint8_t *pix2 )
179 ;-----------------------------------------------------------------------------
180 cglobal sub8x8_dct8_mmx, 3,3
181 global sub8x8_dct8_mmx.skip_prologue
184 call load_diff_4x8_mmx
187 TRANSPOSE4x4W 0,1,2,3,4
190 TRANSPOSE4x4W 4,5,6,7,0
196 call load_diff_4x8_mmx
202 TRANSPOSE4x4W 4,5,6,7,0
205 TRANSPOSE4x4W 0,1,2,3,5
207 SPILL_SHUFFLE r0, 0,1,2,3, 4,5,6,7
208 movq mm4, m6 ; depends on the permutation to not produce conflicts
214 UNSPILL r0+8, 4,5,6,7
218 SPILL r0+8, 1,2,3,5,7
220 UNSPILL r0, 0,1,2,3,4,5,6,7
226 IDCT8_1D 0,1,2,3,4,5,6,7,r1
230 %macro ADD_STORE_ROW 3
231 movq m1, [r0+%1*FDEC_STRIDE]
237 movq [r0+%1*FDEC_STRIDE], m1
240 ;-----------------------------------------------------------------------------
241 ; void add8x8_idct8( uint8_t *dst, int16_t dct[8][8] )
242 ;-----------------------------------------------------------------------------
243 cglobal add8x8_idct8_mmx, 2,2
244 global add8x8_idct8_mmx.skip_prologue
248 UNSPILL r1, 1,2,3,5,6,7
251 TRANSPOSE4x4W 0,1,2,3,7
254 TRANSPOSE4x4W 4,5,6,7,0
257 UNSPILL r1+8, 1,2,3,5,6,7
262 TRANSPOSE4x4W 0,1,2,3,7
265 TRANSPOSE4x4W 4,5,6,7,0
272 ; memory layout at this time:
281 UNSPILL_SHUFFLE r1, 1,2,3, 5,6,7
294 movq [r1+0x08], m0 ; mm4
295 movq [r1+0x48], m4 ; mm5
296 movq [r1+0x58], m5 ; mm0
297 movq [r1+0x68], m6 ; mm2
298 movq [r1+0x78], m7 ; mm6
301 movq [r1+0x18], m1 ; mm1
302 movq [r1+0x28], m2 ; mm7
304 movq [r1+0x38], m3 ; mm3
319 ADD_STORE_ROW 0, [r1+0x00], [r1+0x08]
320 ADD_STORE_ROW 1, [r1+0x10], [r1+0x18]
321 ADD_STORE_ROW 2, [r1+0x20], [r1+0x28]
322 ADD_STORE_ROW 3, m3, [r1+0x38]
323 ADD_STORE_ROW 4, m4, [r1+0x48]
324 ADD_STORE_ROW 5, m5, [r1+0x58]
325 ADD_STORE_ROW 6, m6, [r1+0x68]
326 ADD_STORE_ROW 7, m7, [r1+0x78]
330 cglobal sub8x8_dct, 3,3
331 add r2, 4*FDEC_STRIDE
332 global current_function %+ .skip_prologue
337 LOAD_DIFF8x4 0, 1, 2, 3, 6, 7, r1, r2-4*FDEC_STRIDE
340 LOAD_DIFF8x4 4, 5, 6, 7, 1, 2, r1, r2-4*FDEC_STRIDE
345 DCT4_1D 0, 1, 2, 3, 7
346 TRANSPOSE2x4x4W 0, 1, 2, 3, 7
349 DCT4_1D 4, 5, 6, 7, 2
350 TRANSPOSE2x4x4W 4, 5, 6, 7, 2
353 DCT4_1D 0, 1, 2, 3, 6
355 STORE_DCT 0, 1, 2, 3, r0, 0
356 DCT4_1D 4, 5, 6, 7, 3
357 STORE_DCT 4, 5, 6, 7, r0, 64
360 ;-----------------------------------------------------------------------------
361 ; void sub8x8_dct8( int16_t dct[8][8], uint8_t *pix1, uint8_t *pix2 )
362 ;-----------------------------------------------------------------------------
363 cglobal sub8x8_dct8, 3,3
364 add r2, 4*FDEC_STRIDE
365 global current_function %+ .skip_prologue
369 LOAD_DIFF8x4 0, 1, 2, 3, 4, 7, r1, r2-4*FDEC_STRIDE
372 LOAD_DIFF8x4 4, 5, 6, 7, 0, 1, r1, r2-4*FDEC_STRIDE
375 LOAD_DIFF m0, m7, none, [r1+0*FENC_STRIDE], [r2-4*FDEC_STRIDE]
376 LOAD_DIFF m1, m7, none, [r1+1*FENC_STRIDE], [r2-3*FDEC_STRIDE]
377 LOAD_DIFF m2, m7, none, [r1+2*FENC_STRIDE], [r2-2*FDEC_STRIDE]
378 LOAD_DIFF m3, m7, none, [r1+3*FENC_STRIDE], [r2-1*FDEC_STRIDE]
379 LOAD_DIFF m4, m7, none, [r1+4*FENC_STRIDE], [r2+0*FDEC_STRIDE]
380 LOAD_DIFF m5, m7, none, [r1+5*FENC_STRIDE], [r2+1*FDEC_STRIDE]
382 LOAD_DIFF m6, m7, none, [r1+6*FENC_STRIDE], [r2+2*FDEC_STRIDE]
383 LOAD_DIFF m7, m0, none, [r1+7*FENC_STRIDE], [r2+3*FDEC_STRIDE]
386 DCT8_1D 0,1,2,3,4,5,6,7,r0
388 TRANSPOSE8x8W 0,1,2,3,4,5,6,7,[r0+0x60],[r0+0x40],1
390 DCT8_1D 0,1,2,3,4,5,6,7,r0
396 %define movdqa movaps
397 %define punpcklqdq movlhps
406 ;-----------------------------------------------------------------------------
407 ; void add8x8_idct( uint8_t *pix, int16_t dct[4][4][4] )
408 ;-----------------------------------------------------------------------------
410 cglobal add8x8_idct, 2,2
411 add r0, 4*FDEC_STRIDE
412 global current_function %+ .skip_prologue
414 UNSPILL_SHUFFLE r1, 0,2,1,3, 0,1,2,3
415 SBUTTERFLY qdq, 0, 1, 4
416 SBUTTERFLY qdq, 2, 3, 4
417 UNSPILL_SHUFFLE r1, 4,6,5,7, 4,5,6,7
419 SBUTTERFLY qdq, 4, 5, 0
420 SBUTTERFLY qdq, 6, 7, 0
422 IDCT4_1D w,0,1,2,3,r1
424 TRANSPOSE2x4x4W 0,1,2,3,4
426 IDCT4_1D w,4,5,6,7,r1
428 TRANSPOSE2x4x4W 4,5,6,7,0
431 IDCT4_1D w,0,1,2,3,r1
433 IDCT4_1D w,4,5,6,7,r1
436 DIFFx2 m0, m1, m6, m7, [r0-4*FDEC_STRIDE], [r0-3*FDEC_STRIDE]; m5
437 DIFFx2 m2, m3, m6, m7, [r0-2*FDEC_STRIDE], [r0-1*FDEC_STRIDE]; m5
438 UNSPILL_SHUFFLE r1, 0,2, 6,7
439 DIFFx2 m4, m5, m6, m7, [r0+0*FDEC_STRIDE], [r0+1*FDEC_STRIDE]; m5
440 DIFFx2 m0, m2, m6, m7, [r0+2*FDEC_STRIDE], [r0+3*FDEC_STRIDE]; m5
441 STORE_IDCT m1, m3, m5, m2
450 ;-----------------------------------------------------------------------------
451 ; void add8x8_idct8( uint8_t *p_dst, int16_t dct[8][8] )
452 ;-----------------------------------------------------------------------------
453 %macro ADD8x8_IDCT8 0
454 cglobal add8x8_idct8, 2,2
455 add r0, 4*FDEC_STRIDE
456 global current_function %+ .skip_prologue
458 UNSPILL r1, 1,2,3,5,6,7
459 IDCT8_1D 0,1,2,3,4,5,6,7,r1
461 TRANSPOSE8x8W 0,1,2,3,4,5,6,7,[r1+0x60],[r1+0x40],1
464 IDCT8_1D 0,1,2,3,4,5,6,7,r1
467 DIFFx2 m0, m1, m6, m7, [r0-4*FDEC_STRIDE], [r0-3*FDEC_STRIDE]; m5
468 DIFFx2 m2, m3, m6, m7, [r0-2*FDEC_STRIDE], [r0-1*FDEC_STRIDE]; m5
469 UNSPILL_SHUFFLE r1, 0,2, 6,7
470 DIFFx2 m4, m5, m6, m7, [r0+0*FDEC_STRIDE], [r0+1*FDEC_STRIDE]; m5
471 DIFFx2 m0, m2, m6, m7, [r0+2*FDEC_STRIDE], [r0+3*FDEC_STRIDE]; m5
472 STORE_IDCT m1, m3, m5, m2
474 %endmacro ; ADD8x8_IDCT8
480 %endif ; !HIGH_BIT_DEPTH