1 ;*****************************************************************************
2 ;* pixel.asm: x86 pixel metrics
3 ;*****************************************************************************
4 ;* Copyright (C) 2003-2013 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Holger Lubitz <holger@lubitz.org>
8 ;* Laurent Aimar <fenrir@via.ecp.fr>
9 ;* Alex Izvorski <aizvorksi@gmail.com>
10 ;* Fiona Glaser <fiona@x264.com>
11 ;* Oskar Arvidsson <oskar@irock.se>
13 ;* This program is free software; you can redistribute it and/or modify
14 ;* it under the terms of the GNU General Public License as published by
15 ;* the Free Software Foundation; either version 2 of the License, or
16 ;* (at your option) any later version.
18 ;* This program is distributed in the hope that it will be useful,
19 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
20 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 ;* GNU General Public License for more details.
23 ;* You should have received a copy of the GNU General Public License
24 ;* along with this program; if not, write to the Free Software
25 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
27 ;* This program is also available under a commercial proprietary license.
28 ;* For more information, contact us at licensing@x264.com.
29 ;*****************************************************************************
32 %include "x86util.asm"
35 mask_ff: times 16 db 0xff
38 ssim_c1: times 4 dd 6697.7856 ; .01*.01*1023*1023*64
39 ssim_c2: times 4 dd 3797644.4352 ; .03*.03*1023*1023*64*63
40 pf_64: times 4 dd 64.0
41 pf_128: times 4 dd 128.0
43 ssim_c1: times 4 dd 1671 ; .01*.01*511*511*64
44 ssim_c2: times 4 dd 947556 ; .03*.03*511*511*64*63
46 ssim_c1: times 4 dd 416 ; .01*.01*255*255*64
47 ssim_c2: times 4 dd 235963 ; .03*.03*255*255*64*63
49 mask_ac4: dw 0, -1, -1, -1, 0, -1, -1, -1
50 mask_ac4b: dw 0, -1, 0, -1, -1, -1, -1, -1
51 mask_ac8: dw 0, -1, -1, -1, -1, -1, -1, -1
52 hmul_4p: times 2 db 1, 1, 1, 1, 1, -1, 1, -1
55 mask_10: times 4 dw 0, -1
56 mask_1100: times 2 dd 0, -1
57 pb_pppm: times 4 db 1,1,1,-1
58 deinterleave_shuf: db 0, 2, 4, 6, 8, 10, 12, 14, 1, 3, 5, 7, 9, 11, 13, 15
59 intrax3_shuf: db 7,6,7,6,5,4,5,4,3,2,3,2,1,0,1,0
61 intrax9a_ddlr1: db 6, 7, 8, 9, 7, 8, 9,10, 4, 5, 6, 7, 3, 4, 5, 6
62 intrax9a_ddlr2: db 8, 9,10,11, 9,10,11,12, 2, 3, 4, 5, 1, 2, 3, 4
63 intrax9a_hdu1: db 15, 4, 5, 6,14, 3,15, 4,14, 2,13, 1,13, 1,12, 0
64 intrax9a_hdu2: db 13, 2,14, 3,12, 1,13, 2,12, 0,11,11,11,11,11,11
65 intrax9a_vrl1: db 10,11,12,13, 3, 4, 5, 6,11,12,13,14, 5, 6, 7, 8
66 intrax9a_vrl2: db 2,10,11,12, 1, 3, 4, 5,12,13,14,15, 6, 7, 8, 9
67 intrax9a_vh1: db 6, 7, 8, 9, 6, 7, 8, 9, 4, 4, 4, 4, 3, 3, 3, 3
68 intrax9a_vh2: db 6, 7, 8, 9, 6, 7, 8, 9, 2, 2, 2, 2, 1, 1, 1, 1
69 intrax9a_dc: db 1, 2, 3, 4, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1
70 intrax9a_lut: db 0x60,0x68,0x80,0x00,0x08,0x20,0x40,0x28,0x48,0,0,0,0,0,0,0
71 pw_s01234567: dw 0x8000,0x8001,0x8002,0x8003,0x8004,0x8005,0x8006,0x8007
72 pw_s01234657: dw 0x8000,0x8001,0x8002,0x8003,0x8004,0x8006,0x8005,0x8007
73 intrax9_edge: db 0, 0, 1, 2, 3, 7, 8, 9,10,11,12,13,14,15,15,15
75 intrax9b_ddlr1: db 6, 7, 8, 9, 4, 5, 6, 7, 7, 8, 9,10, 3, 4, 5, 6
76 intrax9b_ddlr2: db 8, 9,10,11, 2, 3, 4, 5, 9,10,11,12, 1, 2, 3, 4
77 intrax9b_hdu1: db 15, 4, 5, 6,14, 2,13, 1,14, 3,15, 4,13, 1,12, 0
78 intrax9b_hdu2: db 13, 2,14, 3,12, 0,11,11,12, 1,13, 2,11,11,11,11
79 intrax9b_vrl1: db 10,11,12,13,11,12,13,14, 3, 4, 5, 6, 5, 6, 7, 8
80 intrax9b_vrl2: db 2,10,11,12,12,13,14,15, 1, 3, 4, 5, 6, 7, 8, 9
81 intrax9b_vh1: db 6, 7, 8, 9, 4, 4, 4, 4, 6, 7, 8, 9, 3, 3, 3, 3
82 intrax9b_vh2: db 6, 7, 8, 9, 2, 2, 2, 2, 6, 7, 8, 9, 1, 1, 1, 1
83 intrax9b_edge2: db 6, 7, 8, 9, 6, 7, 8, 9, 4, 3, 2, 1, 4, 3, 2, 1
84 intrax9b_v1: db 0, 1,-1,-1,-1,-1,-1,-1, 4, 5,-1,-1,-1,-1,-1,-1
85 intrax9b_v2: db 2, 3,-1,-1,-1,-1,-1,-1, 6, 7,-1,-1,-1,-1,-1,-1
86 intrax9b_lut: db 0x60,0x64,0x80,0x00,0x04,0x20,0x40,0x24,0x44,0,0,0,0,0,0,0
88 intra8x9_h1: db 7, 7, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5
89 intra8x9_h2: db 6, 6, 6, 6, 6, 6, 6, 6, 4, 4, 4, 4, 4, 4, 4, 4
90 intra8x9_h3: db 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1
91 intra8x9_h4: db 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0
92 intra8x9_ddl1: db 1, 2, 3, 4, 5, 6, 7, 8, 3, 4, 5, 6, 7, 8, 9,10
93 intra8x9_ddl2: db 2, 3, 4, 5, 6, 7, 8, 9, 4, 5, 6, 7, 8, 9,10,11
94 intra8x9_ddl3: db 5, 6, 7, 8, 9,10,11,12, 7, 8, 9,10,11,12,13,14
95 intra8x9_ddl4: db 6, 7, 8, 9,10,11,12,13, 8, 9,10,11,12,13,14,15
96 intra8x9_vl1: db 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 8
97 intra8x9_vl2: db 1, 2, 3, 4, 5, 6, 7, 8, 2, 3, 4, 5, 6, 7, 8, 9
98 intra8x9_vl3: db 2, 3, 4, 5, 6, 7, 8, 9, 3, 4, 5, 6, 7, 8, 9,10
99 intra8x9_vl4: db 3, 4, 5, 6, 7, 8, 9,10, 4, 5, 6, 7, 8, 9,10,11
100 intra8x9_ddr1: db 8, 9,10,11,12,13,14,15, 6, 7, 8, 9,10,11,12,13
101 intra8x9_ddr2: db 7, 8, 9,10,11,12,13,14, 5, 6, 7, 8, 9,10,11,12
102 intra8x9_ddr3: db 4, 5, 6, 7, 8, 9,10,11, 2, 3, 4, 5, 6, 7, 8, 9
103 intra8x9_ddr4: db 3, 4, 5, 6, 7, 8, 9,10, 1, 2, 3, 4, 5, 6, 7, 8
104 intra8x9_vr1: db 8, 9,10,11,12,13,14,15, 7, 8, 9,10,11,12,13,14
105 intra8x9_vr2: db 8, 9,10,11,12,13,14,15, 6, 8, 9,10,11,12,13,14
106 intra8x9_vr3: db 5, 7, 8, 9,10,11,12,13, 3, 5, 7, 8, 9,10,11,12
107 intra8x9_vr4: db 4, 6, 8, 9,10,11,12,13, 2, 4, 6, 8, 9,10,11,12
108 intra8x9_hd1: db 3, 8, 9,10,11,12,13,14, 1, 6, 2, 7, 3, 8, 9,10
109 intra8x9_hd2: db 2, 7, 3, 8, 9,10,11,12, 0, 5, 1, 6, 2, 7, 3, 8
110 intra8x9_hd3: db 7, 8, 9,10,11,12,13,14, 3, 4, 5, 6, 7, 8, 9,10
111 intra8x9_hd4: db 5, 6, 7, 8, 9,10,11,12, 1, 2, 3, 4, 5, 6, 7, 8
112 intra8x9_hu1: db 13,12,11,10, 9, 8, 7, 6, 9, 8, 7, 6, 5, 4, 3, 2
113 intra8x9_hu2: db 11,10, 9, 8, 7, 6, 5, 4, 7, 6, 5, 4, 3, 2, 1, 0
114 intra8x9_hu3: db 5, 4, 3, 2, 1, 0,15,15, 1, 0,15,15,15,15,15,15
115 intra8x9_hu4: db 3, 2, 1, 0,15,15,15,15,15,15,15,15,15,15,15,15
116 pw_s00112233: dw 0x8000,0x8000,0x8001,0x8001,0x8002,0x8002,0x8003,0x8003
117 pw_s00001111: dw 0x8000,0x8000,0x8000,0x8000,0x8001,0x8001,0x8001,0x8001
119 transd_shuf1: SHUFFLE_MASK_W 0, 8, 2, 10, 4, 12, 6, 14
120 transd_shuf2: SHUFFLE_MASK_W 1, 9, 3, 11, 5, 13, 7, 15
123 sq_0f: dq 0xffffffff, 0
124 pd_f0: times 4 dd 0xffff0000
141 ;=============================================================================
143 ;=============================================================================
146 ;-----------------------------------------------------------------------------
147 ; int pixel_ssd_MxN( uint16_t *, intptr_t, uint16_t *, intptr_t )
148 ;-----------------------------------------------------------------------------
150 cglobal pixel_ssd_%1x%2, 4,5,6
161 %define offset mmsize
164 lea r0, [r0+r1*2*num_rows]
166 psubw m3, [r2+offset]
167 lea r2, [r2+r3*2*num_rows]
180 cglobal pixel_ssd_%1x%2, 4,5
181 mov r4, %1*%2/mmsize/2
188 mova m5, [r0+mmsize*2]
189 mova m6, [r2+mmsize*2]
190 mova m7, [r0+mmsize*3]
193 mova m2, [r2+mmsize*3]
228 %endif ; HIGH_BIT_DEPTH
230 %if HIGH_BIT_DEPTH == 0
231 %macro SSD_LOAD_FULL 5
275 DEINTB %2, %1, %4, %3, 7
290 %macro SSD_LOAD_HALF 5
291 LOAD 1, 2, [t0+%1], [t0+%3], 1
292 JOIN 1, 2, 3, 4, [t2+%2], [t2+%4], 1
293 LOAD 3, 4, [t0+%1], [t0+%3], %5
294 JOIN 3, 4, 5, 6, [t2+%2], [t2+%4], %5
307 punpcklbw m%2, m%1, m%5
309 punpcklbw m%4, m%3, m%5
318 %macro SSD_CORE_SSE2 7-8
320 DEINTB %6, %1, %7, %2, %5
324 DEINTB %6, %3, %7, %4, %5
335 %macro SSD_CORE_SSSE3 7-8
337 punpckhbw m%6, m%1, m%2
338 punpckhbw m%7, m%3, m%4
355 SSD_LOAD_%1 %2,%3,%4,%5,%6
356 SSD_CORE 1, 2, 3, 4, 7, 5, 6, %1
363 ;-----------------------------------------------------------------------------
364 ; int pixel_ssd_16x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
365 ;-----------------------------------------------------------------------------
368 %assign function_align 8
370 %assign function_align 16
372 cglobal pixel_ssd_%1x%2, 0,0,0
373 mov al, %1*%2/mmsize/2
376 jmp mangle(x264_pixel_ssd_%1x%1 %+ SUFFIX %+ .startloop)
381 DECLARE_REG_TMP 0,1,2,3
385 DECLARE_REG_TMP 1,2,3,4
394 %elifidn cpuname, sse2
404 SSD_ITER FULL, 0, 0, mmsize, mmsize, 1
406 SSD_ITER FULL, 0, 0, t1, t3, 2
408 SSD_ITER HALF, 0, 0, t1, t3, 2
434 %define SSD_CORE SSD_CORE_SSE2
435 %define JOIN JOIN_SSE2
442 %define SSD_CORE SSD_CORE_SSSE3
443 %define JOIN JOIN_SSSE3
465 %assign function_align 16
466 %endif ; !HIGH_BIT_DEPTH
468 ;-----------------------------------------------------------------------------
469 ; void pixel_ssd_nv12_core( uint16_t *pixuv1, intptr_t stride1, uint16_t *pixuv2, intptr_t stride2,
470 ; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
472 ; The maximum width this function can handle without risk of overflow is given
473 ; in the following equation: (mmsize in bits)
475 ; 2 * mmsize/32 * (2^32 - 1) / (2^BIT_DEPTH - 1)^2
477 ; For 10-bit MMX this means width >= 16416 and for XMM >= 32832. At sane
478 ; distortion levels it will take much more than that though.
479 ;-----------------------------------------------------------------------------
482 cglobal pixel_ssd_nv12_core, 6,7,7
498 mova m1, [r0+r6+mmsize]
500 psubw m1, [r2+r6+mmsize]
501 PSHUFLW m0, m0, q3120
502 PSHUFLW m1, m1, q3120
504 pshufhw m0, m0, q3120
505 pshufhw m1, m1, q3120
513 %if mmsize==16 ; using HADDD would remove the mmsize/32 part from the
514 ; equation above, putting the width limit at 8208
523 %else ; unfortunately paddq is sse2
524 ; emulate 48 bit precision for mmx2 instead
545 %else ; fixup for mmx2
546 SBUTTERFLY dq, 4, 5, 0
551 SBUTTERFLY dq, 0, 5, 4
559 %endif ; HIGH_BIT_DEPTH
561 %if HIGH_BIT_DEPTH == 0
562 ;-----------------------------------------------------------------------------
563 ; void pixel_ssd_nv12_core( uint8_t *pixuv1, intptr_t stride1, uint8_t *pixuv2, intptr_t stride2,
564 ; int width, int height, uint64_t *ssd_u, uint64_t *ssd_v )
566 ; This implementation can potentially overflow on image widths >= 11008 (or
567 ; 6604 if interlaced), since it is called on blocks of height up to 12 (resp
568 ; 20). At sane distortion levels it will take much more than that though.
569 ;-----------------------------------------------------------------------------
571 cglobal pixel_ssd_nv12_core, 6,7
610 %endif ; !HIGH_BIT_DEPTH
619 ;=============================================================================
621 ;=============================================================================
625 pxor m6, m6 ; sum squared
626 %if HIGH_BIT_DEPTH == 0
632 %endif ; !HIGH_BIT_DEPTH
637 %if mmsize == 8 && %1*%2 == 256
642 %else ; !HIGH_BIT_DEPTH
644 %endif ; HIGH_BIT_DEPTH
677 mova m4, [r0+%1+mmsize]
678 %else ; !HIGH_BIT_DEPTH
684 %endif ; HIGH_BIT_DEPTH
690 %if HIGH_BIT_DEPTH == 0
693 %endif ; !HIGH_BIT_DEPTH
699 ;-----------------------------------------------------------------------------
700 ; int pixel_var_wxh( uint8_t *, intptr_t )
701 ;-----------------------------------------------------------------------------
703 cglobal pixel_var_16x16, 2,3
706 VAR_2ROW 8*SIZEOF_PIXEL, 16
709 cglobal pixel_var_8x16, 2,3
715 cglobal pixel_var_8x8, 2,3
723 cglobal pixel_var_16x16, 2,3,8
729 cglobal pixel_var_8x8, 2,3,8
752 %endif ; HIGH_BIT_DEPTH
754 %if HIGH_BIT_DEPTH == 0
756 cglobal pixel_var_16x16, 2,3,8
769 cglobal pixel_var_8x8, 2,4,8
785 cglobal pixel_var_8x16, 2,4,8
808 %endif ; !HIGH_BIT_DEPTH
818 sub eax, r1d ; sqr - (sum * sum >> shift)
822 ;-----------------------------------------------------------------------------
823 ; int pixel_var2_8x8( pixel *, intptr_t, pixel *, intptr_t, int * )
824 ;-----------------------------------------------------------------------------
825 %macro VAR2_8x8_MMX 2
826 cglobal pixel_var2_8x%1, 5,6
835 psubw m1, [r2+mmsize]
836 %else ; !HIGH_BIT_DEPTH
847 %endif ; HIGH_BIT_DEPTH
867 %macro VAR2_8x8_SSE2 2
868 cglobal pixel_var2_8x%1, 5,6,8
877 %else ; !HIGH_BIT_DEPTH
883 %endif ; HIGH_BIT_DEPTH
892 lea r0, [r0+r1*2*SIZEOF_PIXEL]
893 lea r2, [r2+r3*2*SIZEOF_PIXEL]
903 %if HIGH_BIT_DEPTH == 0
904 %macro VAR2_8x8_SSSE3 2
905 cglobal pixel_var2_8x%1, 5,6,8
907 pxor m6, m6 ; sum squared
955 %endif ; !HIGH_BIT_DEPTH
957 ;=============================================================================
959 ;=============================================================================
963 ; just use shufps on anything post conroe
966 ; join 2x 32 bit and duplicate them
967 ; emulating shufps is faster on conroe
971 ; doesn't need to dup. sse2 does things by zero extending to words and full h_2d
983 %macro DIFF_UNPACK_SSE2 5
992 %macro DIFF_SUMSUB_SSSE3 5
993 HSUMSUB %1, %2, %3, %4, %5
998 %macro LOAD_DUP_2x4P 4 ; dst, tmp, 2* pointer
1004 %macro LOAD_DUP_4x8P_CONROE 8 ; 4*dst, 4*pointer
1011 %macro LOAD_DUP_4x8P_PENRYN 8
1012 ; penryn and nehalem run punpcklqdq and movddup in different units
1021 %macro LOAD_SUMSUB_8x2P 9
1022 LOAD_DUP_4x8P %1, %2, %3, %4, %6, %7, %8, %9
1023 DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
1026 %macro LOAD_SUMSUB_8x4P_SSSE3 7-10 r0, r2, 0
1027 ; 4x dest, 2x tmp, 1x mul, [2* ptr], [increment?]
1028 LOAD_SUMSUB_8x2P %1, %2, %5, %6, %7, [%8], [%9], [%8+r1], [%9+r3]
1029 LOAD_SUMSUB_8x2P %3, %4, %5, %6, %7, [%8+2*r1], [%9+2*r3], [%8+r4], [%9+r5]
1036 %macro LOAD_SUMSUB_16P_SSSE3 7 ; 2*dst, 2*tmp, mul, 2*ptr
1042 DIFF_SUMSUB_SSSE3 %1, %3, %2, %4, %5
1045 %macro LOAD_SUMSUB_16P_SSE2 7 ; 2*dst, 2*tmp, mask, 2*ptr
1048 DEINTB %1, %2, %3, %4, %5
1051 SUMSUB_BA w, %1, %2, %3
1054 %macro LOAD_SUMSUB_16x4P 10-13 r0, r2, none
1055 ; 8x dest, 1x tmp, 1x mul, [2* ptr] [2nd tmp]
1056 LOAD_SUMSUB_16P %1, %5, %2, %3, %10, %11, %12
1057 LOAD_SUMSUB_16P %2, %6, %3, %4, %10, %11+r1, %12+r3
1058 LOAD_SUMSUB_16P %3, %7, %4, %9, %10, %11+2*r1, %12+2*r3
1059 LOAD_SUMSUB_16P %4, %8, %13, %9, %10, %11+r4, %12+r5
1062 ; in: r4=3*stride1, r5=3*stride2
1063 ; in: %2 = horizontal offset
1064 ; in: %3 = whether we need to increment pix1 and pix2
1067 %macro SATD_4x4_MMX 3
1069 %assign offset %2*SIZEOF_PIXEL
1070 LOAD_DIFF m4, m3, none, [r0+ offset], [r2+ offset]
1071 LOAD_DIFF m5, m3, none, [r0+ r1+offset], [r2+ r3+offset]
1072 LOAD_DIFF m6, m3, none, [r0+2*r1+offset], [r2+2*r3+offset]
1073 LOAD_DIFF m7, m3, none, [r0+ r4+offset], [r2+ r5+offset]
1078 HADAMARD4_2D 4, 5, 6, 7, 3, %%n
1083 %macro SATD_8x4_SSE 8-9
1085 HADAMARD4_2D_SSE %2, %3, %4, %5, %6, amax
1087 HADAMARD4_V %2, %3, %4, %5, %6
1088 ; doing the abs first is a slight advantage
1089 ABSW2 m%2, m%4, m%2, m%4, m%6, m%7
1090 ABSW2 m%3, m%5, m%3, m%5, m%6, m%7
1091 HADAMARD 1, max, %2, %4, %6, %7
1101 HADAMARD 1, max, %3, %5, %6, %7
1106 %macro SATD_START_MMX 0
1108 lea r4, [3*r1] ; 3*stride1
1109 lea r5, [3*r3] ; 3*stride2
1112 %macro SATD_END_MMX 0
1116 %else ; !HIGH_BIT_DEPTH
1117 pshufw m1, m0, q1032
1119 pshufw m1, m0, q2301
1123 %endif ; HIGH_BIT_DEPTH
1127 ; FIXME avoid the spilling of regs to hold 3*stride.
1128 ; for small blocks on x86_32, modify pixel pointer instead.
1130 ;-----------------------------------------------------------------------------
1131 ; int pixel_satd_16x16( uint8_t *, intptr_t, uint8_t *, intptr_t )
1132 ;-----------------------------------------------------------------------------
1134 cglobal pixel_satd_16x4_internal
1135 SATD_4x4_MMX m2, 0, 0
1136 SATD_4x4_MMX m1, 4, 0
1138 SATD_4x4_MMX m2, 8, 0
1140 SATD_4x4_MMX m1, 12, 0
1145 cglobal pixel_satd_8x8_internal
1146 SATD_4x4_MMX m2, 0, 0
1147 SATD_4x4_MMX m1, 4, 1
1150 pixel_satd_8x4_internal_mmx2:
1151 SATD_4x4_MMX m2, 0, 0
1152 SATD_4x4_MMX m1, 4, 0
1158 %macro SATD_MxN_MMX 3
1159 cglobal pixel_satd_%1x%2, 4,7
1162 call pixel_satd_%1x%3_internal_mmx2
1169 call pixel_satd_%1x%3_internal_mmx2
1180 SATD_MxN_MMX 16, 16, 4
1181 SATD_MxN_MMX 16, 8, 4
1182 SATD_MxN_MMX 8, 16, 8
1183 %endif ; HIGH_BIT_DEPTH
1185 %if HIGH_BIT_DEPTH == 0
1186 cglobal pixel_satd_16x16, 4,6
1190 call pixel_satd_16x4_internal_mmx2
1194 call pixel_satd_16x4_internal_mmx2
1199 cglobal pixel_satd_16x8, 4,6
1202 call pixel_satd_16x4_internal_mmx2
1205 call pixel_satd_16x4_internal_mmx2
1208 cglobal pixel_satd_8x16, 4,6
1211 call pixel_satd_8x8_internal_mmx2
1214 call pixel_satd_8x8_internal_mmx2
1216 %endif ; !HIGH_BIT_DEPTH
1218 cglobal pixel_satd_8x8, 4,6
1221 call pixel_satd_8x8_internal_mmx2
1224 cglobal pixel_satd_8x4, 4,6
1227 call pixel_satd_8x4_internal_mmx2
1230 cglobal pixel_satd_4x16, 4,6
1232 SATD_4x4_MMX m0, 0, 1
1233 SATD_4x4_MMX m1, 0, 1
1235 SATD_4x4_MMX m1, 0, 1
1237 SATD_4x4_MMX m1, 0, 0
1241 cglobal pixel_satd_4x8, 4,6
1243 SATD_4x4_MMX m0, 0, 1
1244 SATD_4x4_MMX m1, 0, 0
1248 cglobal pixel_satd_4x4, 4,6
1250 SATD_4x4_MMX m0, 0, 0
1253 %macro SATD_START_SSE2 2
1262 %macro SATD_END_SSE2 1
1268 %macro BACKUP_POINTERS 0
1278 %macro RESTORE_AND_INC_POINTERS 0
1293 %macro SATD_4x8_SSE 2
1310 %if cpuflag(ssse3) && %1==1
1312 DIFFOP 0, 4, 1, 5, 3
1314 DIFFOP 0, 4, 1, 5, 7
1328 %if cpuflag(ssse3) && %1==1
1330 DIFFOP 2, 6, 3, 5, 4
1332 DIFFOP 2, 6, 3, 5, 7
1334 SATD_8x4_SSE cpuname, 0, 1, 2, 3, 4, 5, 7, %2
1337 ;-----------------------------------------------------------------------------
1338 ; int pixel_satd_8x4( uint8_t *, intptr_t, uint8_t *, intptr_t )
1339 ;-----------------------------------------------------------------------------
1342 cglobal pixel_satd_4x4, 4, 6, 6
1345 LOAD_DUP_2x4P m2, m5, [r2], [r2+r3]
1346 LOAD_DUP_2x4P m3, m5, [r2+2*r3], [r2+r5]
1347 LOAD_DUP_2x4P m0, m5, [r0], [r0+r1]
1348 LOAD_DUP_2x4P m1, m5, [r0+2*r1], [r0+r4]
1349 DIFF_SUMSUB_SSSE3 0, 2, 1, 3, 4
1350 HADAMARD 0, sumsub, 0, 1, 2, 3
1351 HADAMARD 4, sumsub, 0, 1, 2, 3
1352 HADAMARD 1, amax, 0, 1, 2, 3
1358 cglobal pixel_satd_4x8, 4, 6, 8
1363 SATD_4x8_SSE 0, swap
1368 cglobal pixel_satd_4x16, 4, 6, 8
1373 SATD_4x8_SSE 0, swap
1381 cglobal pixel_satd_8x8_internal
1382 LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1
1383 SATD_8x4_SSE cpuname, 0, 1, 2, 3, 4, 5, 6
1384 %%pixel_satd_8x4_internal:
1385 LOAD_SUMSUB_8x4P 0, 1, 2, 3, 4, 5, 7, r0, r2, 1
1386 SATD_8x4_SSE cpuname, 0, 1, 2, 3, 4, 5, 6
1389 %if UNIX64 ; 16x8 regresses on phenom win64, 16x16 is almost the same
1390 cglobal pixel_satd_16x4_internal
1391 LOAD_SUMSUB_16x4P 0, 1, 2, 3, 4, 8, 5, 9, 6, 7, r0, r2, 11
1394 ; FIXME: this doesn't really mean ssse3, but rather selects between two different behaviors implemented with sse2?
1395 SATD_8x4_SSE ssse3, 0, 1, 2, 3, 6, 11, 10
1396 SATD_8x4_SSE ssse3, 4, 8, 5, 9, 6, 3, 10
1399 cglobal pixel_satd_16x8, 4,6,12
1400 SATD_START_SSE2 m10, m7
1401 %if notcpuflag(ssse3)
1404 jmp %%pixel_satd_16x8_internal
1406 cglobal pixel_satd_16x16, 4,6,12
1407 SATD_START_SSE2 m10, m7
1408 %if notcpuflag(ssse3)
1411 call pixel_satd_16x4_internal
1412 call pixel_satd_16x4_internal
1413 %%pixel_satd_16x8_internal:
1414 call pixel_satd_16x4_internal
1415 call pixel_satd_16x4_internal
1418 cglobal pixel_satd_16x8, 4,6,8
1419 SATD_START_SSE2 m6, m7
1421 call pixel_satd_8x8_internal
1422 RESTORE_AND_INC_POINTERS
1423 call pixel_satd_8x8_internal
1426 cglobal pixel_satd_16x16, 4,6,8
1427 SATD_START_SSE2 m6, m7
1429 call pixel_satd_8x8_internal
1430 call pixel_satd_8x8_internal
1431 RESTORE_AND_INC_POINTERS
1432 call pixel_satd_8x8_internal
1433 call pixel_satd_8x8_internal
1437 cglobal pixel_satd_8x16, 4,6,8
1438 SATD_START_SSE2 m6, m7
1439 call pixel_satd_8x8_internal
1440 call pixel_satd_8x8_internal
1443 cglobal pixel_satd_8x8, 4,6,8
1444 SATD_START_SSE2 m6, m7
1445 call pixel_satd_8x8_internal
1448 cglobal pixel_satd_8x4, 4,6,8
1449 SATD_START_SSE2 m6, m7
1450 call %%pixel_satd_8x4_internal
1452 %endmacro ; SATDS_SSE2
1467 %endif ; HIGH_BIT_DEPTH
1473 %else ; sse2 doesn't seem to like the horizontal way of doing things
1474 %define vertical (cpuflags == cpuflags_sse2)
1478 ;-----------------------------------------------------------------------------
1479 ; int pixel_sa8d_8x8( uint8_t *, intptr_t, uint8_t *, intptr_t )
1480 ;-----------------------------------------------------------------------------
1481 cglobal pixel_sa8d_8x8_internal
1484 LOAD_SUMSUB_8x4P 0, 1, 2, 8, 5, 6, 7, r0, r2
1485 LOAD_SUMSUB_8x4P 4, 5, 3, 9, 11, 6, 7, r6, r7
1487 HADAMARD8_2D 0, 1, 2, 8, 4, 5, 3, 9, 6, amax
1489 HADAMARD8_2D_HMUL 0, 1, 2, 8, 4, 5, 3, 9, 6, 11
1497 cglobal pixel_sa8d_8x8, 4,8,12
1504 call pixel_sa8d_8x8_internal
1509 %endif ; HIGH_BIT_DEPTH
1515 cglobal pixel_sa8d_16x16, 4,8,12
1522 call pixel_sa8d_8x8_internal ; pix[0]
1523 add r2, 8*SIZEOF_PIXEL
1524 add r0, 8*SIZEOF_PIXEL
1529 call pixel_sa8d_8x8_internal ; pix[8]
1533 call pixel_sa8d_8x8_internal ; pix[8*stride+8]
1534 sub r2, 8*SIZEOF_PIXEL
1535 sub r0, 8*SIZEOF_PIXEL
1537 call pixel_sa8d_8x8_internal ; pix[8*stride]
1540 %if HIGH_BIT_DEPTH == 0
1550 cglobal pixel_sa8d_8x8_internal
1551 %define spill0 [esp+4]
1552 %define spill1 [esp+20]
1553 %define spill2 [esp+36]
1555 LOAD_DIFF_8x4P 0, 1, 2, 3, 4, 5, 6, r0, r2, 1
1556 HADAMARD4_2D 0, 1, 2, 3, 4
1558 LOAD_DIFF_8x4P 4, 5, 6, 7, 3, 3, 2, r0, r2, 1
1559 HADAMARD4_2D 4, 5, 6, 7, 3
1560 HADAMARD2_2D 0, 4, 1, 5, 3, qdq, amax
1563 HADAMARD2_2D 2, 6, 3, 7, 5, qdq, amax
1566 LOAD_SUMSUB_8x4P 0, 1, 2, 3, 5, 6, 7, r0, r2, 1
1567 ; could do first HADAMARD4_V here to save spilling later
1568 ; surprisingly, not a win on conroe or even p4
1573 LOAD_SUMSUB_8x4P 4, 5, 6, 7, 2, 3, 1, r0, r2, 1
1574 HADAMARD4_V 4, 5, 6, 7, 3
1580 HADAMARD4_V 0, 1, 2, 3, 7
1581 SUMSUB_BADC w, 0, 4, 1, 5, 7
1582 HADAMARD 2, sumsub, 0, 4, 7, 6
1583 HADAMARD 2, sumsub, 1, 5, 7, 6
1584 HADAMARD 1, amax, 0, 4, 7, 6
1585 HADAMARD 1, amax, 1, 5, 7, 6
1589 SUMSUB_BADC w, 2, 6, 3, 7, 4
1590 HADAMARD 2, sumsub, 2, 6, 4, 5
1591 HADAMARD 2, sumsub, 3, 7, 4, 5
1592 HADAMARD 1, amax, 2, 6, 4, 5
1593 HADAMARD 1, amax, 3, 7, 4, 5
1594 %endif ; sse2/non-sse2
1599 %endif ; ifndef mmx2
1601 cglobal pixel_sa8d_8x8, 4,7
1608 call pixel_sa8d_8x8_internal
1613 %endif ; HIGH_BIT_DEPTH
1620 cglobal pixel_sa8d_16x16, 4,7
1627 call pixel_sa8d_8x8_internal
1636 call pixel_sa8d_8x8_internal
1639 add r0, 8*SIZEOF_PIXEL
1640 add r2, 8*SIZEOF_PIXEL
1643 call pixel_sa8d_8x8_internal
1650 mova [esp+64-mmsize], m0
1651 call pixel_sa8d_8x8_internal
1654 %else ; !HIGH_BIT_DEPTH
1655 paddusw m0, [esp+64-mmsize]
1672 %endif ; HIGH_BIT_DEPTH
1678 %endif ; !ARCH_X86_64
1681 ;=============================================================================
1683 ;=============================================================================
1694 ; intra_sa8d_x3_8x8 and intra_satd_x3_4x4 are obsoleted by x9 on ssse3+,
1695 ; and are only retained for old cpus.
1696 %macro INTRA_SA8D_SSE2 0
1698 ;-----------------------------------------------------------------------------
1699 ; void intra_sa8d_x3_8x8( uint8_t *fenc, uint8_t edge[36], int *res )
1700 ;-----------------------------------------------------------------------------
1701 cglobal intra_sa8d_x3_8x8, 3,3,14
1704 movq m0, [r0+0*FENC_STRIDE]
1705 movq m1, [r0+1*FENC_STRIDE]
1706 movq m2, [r0+2*FENC_STRIDE]
1707 movq m3, [r0+3*FENC_STRIDE]
1708 movq m4, [r0+4*FENC_STRIDE]
1709 movq m5, [r0+5*FENC_STRIDE]
1710 movq m6, [r0+6*FENC_STRIDE]
1711 movq m7, [r0+7*FENC_STRIDE]
1721 HADAMARD8_2D 0, 1, 2, 3, 4, 5, 6, 7, 8
1723 ABSW2 m8, m9, m2, m3, m2, m3
1724 ABSW2 m10, m11, m4, m5, m4, m5
1727 ABSW2 m10, m11, m6, m7, m6, m7
1734 ; 1D hadamard of edges
1740 HSUMSUB2 pmullw, m8, m9, m10, m11, m11, q1032, [pw_ppppmmmm]
1741 HSUMSUB2 pmullw, m8, m9, m10, m11, m11, q2301, [pw_ppmmppmm]
1742 pshuflw m10, m8, q2301
1743 pshuflw m11, m9, q2301
1744 pshufhw m10, m10, q2301
1745 pshufhw m11, m11, q2301
1746 pmullw m8, [pw_pmpmpmpm]
1747 pmullw m11, [pw_pmpmpmpm]
1757 psllw m8, 3 ; left edge
1760 ABSW2 m8, m10, m8, m10, m11, m12 ; 1x8 sum
1769 punpcklqdq m0, m4 ; transpose
1770 psllw m9, 3 ; top edge
1771 psrldq m2, m13, 2 ; 8x7 sum
1772 psubw m0, m9 ; 8x1 sum
1781 punpckhdq m3, m2, m8
1783 pshufd m5, m13, q3311
1786 punpckhqdq m0, m2, m5
1791 movq [r2], m0 ; i8x8_v, i8x8_h
1793 movd [r2+8], m0 ; i8x8_dc
1795 %endif ; ARCH_X86_64
1796 %endmacro ; INTRA_SA8D_SSE2
1799 ; out: m0..m3 = hadamard coefs
1801 cglobal hadamard_load
1802 ; not really a global, but otherwise cycles get attributed to the wrong function in profiling
1804 mova m0, [r0+0*FENC_STRIDEB]
1805 mova m1, [r0+1*FENC_STRIDEB]
1806 mova m2, [r0+2*FENC_STRIDEB]
1807 mova m3, [r0+3*FENC_STRIDEB]
1810 movd m0, [r0+0*FENC_STRIDE]
1811 movd m1, [r0+1*FENC_STRIDE]
1812 movd m2, [r0+2*FENC_STRIDE]
1813 movd m3, [r0+3*FENC_STRIDE]
1819 HADAMARD4_2D 0, 1, 2, 3, 4
1823 %macro SCALAR_HADAMARD 4-5 ; direction, offset, 3x tmp
1826 mova %3, [r1+%2*SIZEOF_PIXEL-FDEC_STRIDEB]
1828 movd %3, [r1+%2*SIZEOF_PIXEL-FDEC_STRIDEB]
1834 shl %2d, 5 ; log(FDEC_STRIDEB)
1836 movd %3, [r1+%2*SIZEOF_PIXEL-4+1*FDEC_STRIDEB]
1837 pinsrw %3, [r1+%2*SIZEOF_PIXEL-2+0*FDEC_STRIDEB], 0
1838 pinsrw %3, [r1+%2*SIZEOF_PIXEL-2+2*FDEC_STRIDEB], 2
1839 pinsrw %3, [r1+%2*SIZEOF_PIXEL-2+3*FDEC_STRIDEB], 3
1840 %if HIGH_BIT_DEPTH == 0
1848 %define %%sign psignw
1850 %define %%sign pmullw
1852 pshufw %4, %3, q1032
1853 %%sign %4, [pw_ppmmppmm]
1855 pshufw %4, %3, q2301
1856 %%sign %4, [pw_pmpmpmpm]
1859 mova [%1_1d+2*%2], %3
1862 %macro SUM_MM_X3 8 ; 3x sum, 4x tmp, op
1864 pshufw %4, %1, q1032
1865 pshufw %5, %2, q1032
1866 pshufw %6, %3, q1032
1873 pshufw %4, %1, q1032
1874 pshufw %5, %2, q1032
1875 pshufw %6, %3, q1032
1885 ABSW2 m4, m5, m1, m2, m1, m2
1892 ; out: m0 v, m4 h, m5 dc
1894 %macro SUM4x3 3 ; dc, left, top
1905 punpckldq m0, m2 ; transpose
1907 ABSW2 m4, m5, m4, m5, m2, m3 ; 1x4 sum
1908 ABSW m0, m0, m1 ; 4x1 sum
1911 %macro INTRA_X3_MMX 0
1912 ;-----------------------------------------------------------------------------
1913 ; void intra_satd_x3_4x4( uint8_t *fenc, uint8_t *fdec, int *res )
1914 ;-----------------------------------------------------------------------------
1915 cglobal intra_satd_x3_4x4, 3,3
1917 ; stack is 16 byte aligned because abi says so
1918 %define top_1d rsp-8 ; size 8
1919 %define left_1d rsp-16 ; size 8
1921 ; stack is 16 byte aligned at least in gcc, and we've pushed 3 regs + return address, so it's still aligned
1923 %define top_1d esp+8
1928 SCALAR_HADAMARD left, 0, m4, m5
1929 SCALAR_HADAMARD top, 0, m6, m5, m7
1932 pand m6, [sw_f0] ; dc
1935 SUM4x3 m6, [left_1d], [top_1d]
1939 psrlq m1, 16 ; 4x3 sum
1942 SUM_MM_X3 m0, m4, m5, m1, m2, m3, m6, pavgw
1943 movd [r2+0], m0 ; i4x4_v satd
1944 movd [r2+4], m4 ; i4x4_h satd
1945 movd [r2+8], m5 ; i4x4_dc satd
1946 %if ARCH_X86_64 == 0
1951 ;-----------------------------------------------------------------------------
1952 ; void intra_satd_x3_16x16( uint8_t *fenc, uint8_t *fdec, int *res )
1953 ;-----------------------------------------------------------------------------
1954 cglobal intra_satd_x3_16x16, 0,5
1955 %assign stack_pad 120 + ((stack_offset+120+gprsize)&15)
1956 ; not really needed on x86_64, just shuts up valgrind about storing data below the stack across a function call
1958 %define sums rsp+64 ; size 56
1959 %define top_1d rsp+32 ; size 32
1960 %define left_1d rsp ; size 32
1978 SCALAR_HADAMARD left, r3, m0, m1
1979 SCALAR_HADAMARD top, r3, m1, m2, m3
1985 pand m6, [sw_f0] ; dc
1996 SUM4x3 m6, [left_1d+8*(r3+4)], [top_1d+8*(r4+4)]
1999 paddw m0, [sums+ 0] ; i16x16_v satd
2000 paddw m4, [sums+ 8] ; i16x16_h satd
2001 paddw m5, [sums+16] ; i16x16_dc satd
2006 add r0, 4*SIZEOF_PIXEL
2023 punpckhwd m3, m5, m7
2033 add r0, 4*FENC_STRIDEB-16*SIZEOF_PIXEL
2042 HADDD m5, m7 ; DC satd
2043 HADDD m4, m7 ; H satd
2044 HADDD m0, m7 ; the part of V satd that doesn't overlap with DC
2046 psrlq m1, 32 ; DC[1]
2047 paddd m0, m3 ; DC[2]
2048 psrlq m3, 32 ; DC[3]
2053 SUM_MM_X3 m0, m4, m5, m3, m1, m2, m6, paddd
2060 movd [r2+8], m5 ; i16x16_dc satd
2061 movd [r2+4], m4 ; i16x16_h satd
2062 movd [r2+0], m0 ; i16x16_v satd
2072 ;-----------------------------------------------------------------------------
2073 ; void intra_satd_x3_8x8c( uint8_t *fenc, uint8_t *fdec, int *res )
2074 ;-----------------------------------------------------------------------------
2075 cglobal intra_satd_x3_8x8c, 0,6
2076 ; not really needed on x86_64, just shuts up valgrind about storing data below the stack across a function call
2078 %define sums rsp+48 ; size 24
2079 %define dc_1d rsp+32 ; size 16
2080 %define top_1d rsp+16 ; size 16
2081 %define left_1d rsp ; size 16
2091 SCALAR_HADAMARD left, r3, m0, m1
2092 SCALAR_HADAMARD top, r3, m0, m1, m2
2097 movzx t0d, word [left_1d+0]
2098 movzx r3d, word [top_1d+0]
2099 movzx r4d, word [left_1d+8]
2100 movzx r5d, word [top_1d+8]
2101 lea t0d, [t0 + r3 + 16]
2102 lea r3d, [r4 + r5 + 16]
2111 mov [dc_1d+ 0], t0d ; tl
2112 mov [dc_1d+ 4], r5d ; tr
2113 mov [dc_1d+ 8], r4d ; bl
2114 mov [dc_1d+12], r3d ; br
2127 SUM4x3 [r5+4*(r4+2)], [left_1d+8*(r3+2)], [top_1d+8*(r4+2)]
2130 paddw m0, [sums+16] ; i4x4_v satd
2131 paddw m4, [sums+8] ; i4x4_h satd
2132 paddw m5, [sums+0] ; i4x4_dc satd
2137 add r0, 4*SIZEOF_PIXEL
2140 add r0, 4*FENC_STRIDEB-8*SIZEOF_PIXEL
2153 SUM_MM_X3 m0, m1, m2, m3, m4, m5, m6, paddd
2159 SUM_MM_X3 m0, m1, m2, m3, m4, m5, m6, paddd
2162 movd [r2+0], m0 ; i8x8c_dc satd
2163 movd [r2+4], m1 ; i8x8c_h satd
2164 movd [r2+8], m2 ; i8x8c_v satd
2167 %endmacro ; INTRA_X3_MMX
2171 %macro PRED4x4_LOWPASS 5
2188 %macro INTRA_X9_PRED 2
2190 movu m1, [r1-1*FDEC_STRIDE-8]
2191 pinsrb m1, [r1+3*FDEC_STRIDE-1], 0
2192 pinsrb m1, [r1+2*FDEC_STRIDE-1], 1
2193 pinsrb m1, [r1+1*FDEC_STRIDE-1], 2
2194 pinsrb m1, [r1+0*FDEC_STRIDE-1], 3
2196 movd mm0, [r1+3*FDEC_STRIDE-4]
2197 punpcklbw mm0, [r1+2*FDEC_STRIDE-4]
2198 movd mm1, [r1+1*FDEC_STRIDE-4]
2199 punpcklbw mm1, [r1+0*FDEC_STRIDE-4]
2203 movu m1, [r1-1*FDEC_STRIDE-8]
2204 movss m1, m0 ; l3 l2 l1 l0 __ __ __ lt t0 t1 t2 t3 t4 t5 t6 t7
2206 pshufb m1, [intrax9_edge] ; l3 l3 l2 l1 l0 lt t0 t1 t2 t3 t4 t5 t6 t7 t7 __
2207 psrldq m0, m1, 1 ; l3 l2 l1 l0 lt t0 t1 t2 t3 t4 t5 t6 t7 t7 __ __
2208 psrldq m2, m1, 2 ; l2 l1 l0 lt t0 t1 t2 t3 t4 t5 t6 t7 t7 __ __ __
2209 pavgb m5, m0, m1 ; Gl3 Gl2 Gl1 Gl0 Glt Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 __ __ __ __ __
2211 PRED4x4_LOWPASS m0, m1, m2, m0, m4 ; Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 __ __ __
2213 ; Ft1 Ft2 Ft3 Ft4 Flt Ft0 Ft1 Ft2
2214 ; Ft2 Ft3 Ft4 Ft5 Fl0 Flt Ft0 Ft1
2215 ; Ft3 Ft4 Ft5 Ft6 Fl1 Fl0 Flt Ft0
2216 ; Ft4 Ft5 Ft6 Ft7 Fl2 Fl1 Fl0 Flt
2217 pshufb m2, m0, [%1_ddlr1] ; a: ddl row0, ddl row1, ddr row0, ddr row1 / b: ddl row0, ddr row0, ddl row1, ddr row1
2218 pshufb m3, m0, [%1_ddlr2] ; rows 2,3
2220 ; Glt Flt Ft0 Ft1 Gl0 Fl1 Gl1 Fl2
2221 ; Gl0 Fl0 Glt Flt Gl1 Fl2 Gl2 Fl3
2222 ; Gl1 Fl1 Gl0 Fl0 Gl2 Fl3 Gl3 Gl3
2223 ; Gl2 Fl2 Gl1 Fl1 Gl3 Gl3 Gl3 Gl3
2224 pslldq m0, 5 ; ___ ___ ___ ___ ___ Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5
2225 palignr m7, m5, m0, 5 ; Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Gl3 Gl2 Gl1 Gl0 Glt
2226 pshufb m6, m7, [%1_hdu1]
2227 pshufb m7, m7, [%1_hdu2]
2229 ; Gt0 Gt1 Gt2 Gt3 Gt1 Gt2 Gt3 Gt4
2230 ; Flt Ft0 Ft1 Ft2 Ft1 Ft2 Ft3 Ft4
2231 ; Fl0 Gt0 Gt1 Gt2 Gt2 Gt3 Gt4 Gt5
2232 ; Fl1 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5
2233 psrldq m5, 5 ; Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 ...
2234 palignr m5, m0, 6 ; ___ Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Gt0 Gt1 Gt2 Gt3 Gt4 Gt5
2235 pshufb m4, m5, [%1_vrl1]
2236 pshufb m5, m5, [%1_vrl2]
2237 %endmacro ; INTRA_X9_PRED
2239 %macro INTRA_X9_VHDC 5 ; edge, fenc01, fenc23, tmp, tmp
2240 pshufb m2, m%1, [intrax9b_vh1]
2241 pshufb m3, m%1, [intrax9b_vh2]
2242 mova [pred_buf+0x60], m2
2243 mova [pred_buf+0x70], m3
2244 pshufb m%1, [intrax9b_edge2] ; t0 t1 t2 t3 t0 t1 t2 t3 l0 l1 l2 l3 l0 l1 l2 l3
2245 pmaddubsw m%1, [hmul_4p]
2246 pshufhw m0, m%1, q2301
2247 pshuflw m0, m0, q2301
2248 psignw m%1, [pw_pmpmpmpm]
2250 psllw m0, 2 ; hadamard(top), hadamard(left)
2252 pshufb m1, m0, [intrax9b_v1]
2253 pshufb m2, m0, [intrax9b_v2]
2255 psignw m3, [pw_pmmpzzzz] ; FIXME could this be eliminated?
2257 pand m0, [sw_f0] ; dc
2258 ; This (as well as one of the steps in intra_satd_x9_4x4.satd_8x4) could be
2259 ; changed from a wd transpose to a qdq, with appropriate rearrangement of inputs.
2260 ; Which would be faster on conroe, but slower on penryn and sandybridge, and too invasive to ifdef.
2261 HADAMARD 0, sumsub, %2, %3, %4, %5
2262 HADAMARD 1, sumsub, %2, %3, %4, %5
2265 imul r3d, 0x01010101
2266 mov [pred_buf+0x80], r3d
2267 mov [pred_buf+0x88], r3d
2268 mov [pred_buf+0x90], r3d
2269 mov [pred_buf+0x98], r3d
2285 SBUTTERFLY qdq, 3, 0, 2
2296 pmaddwd m1, [pw_1] ; v, _, h, dc
2298 %endmacro ; INTRA_X9_VHDC
2300 %macro INTRA_X9_END 2
2302 phminposuw m0, m0 ; h,dc,ddl,ddr,vr,hd,vl,hu
2309 ; 4x4 sad is up to 12 bits; +bitcosts -> 13 bits; pack with 3 bit index
2311 paddw m0, [pw_s01234567] ; h,dc,ddl,ddr,vr,hd,vl,hu
2313 ; 4x4 satd is up to 13 bits; +bitcosts and saturate -> 13 bits; pack with 3 bit index
2316 paddw m0, [pw_s01234657] ; h,dc,ddl,ddr,vr,vl,hd,hu
2320 pshuflw m1, m0, q0032
2322 pshuflw m1, m0, q0001
2329 ; 1<<16: increment index to match intra4x4_pred_e. couldn't do this before because it had to fit in 3 bits
2330 ; 1<<12: undo sign manipulation
2331 lea eax, [rax+r2+(1<<16)+(1<<12)]
2336 ; output the predicted samples
2341 movzx r2d, byte [r2+r3]
2343 movzx r2d, byte [%2_lut+r3]
2346 movq mm0, [pred_buf+r2]
2347 movq mm1, [pred_buf+r2+16]
2348 movd [r1+0*FDEC_STRIDE], mm0
2349 movd [r1+2*FDEC_STRIDE], mm1
2352 movd [r1+1*FDEC_STRIDE], mm0
2353 movd [r1+3*FDEC_STRIDE], mm1
2357 mov r3d, [pred_buf+r2+8*i]
2358 mov [r1+i*FDEC_STRIDE], r3d
2362 %endmacro ; INTRA_X9_END
2365 ;-----------------------------------------------------------------------------
2366 ; int intra_sad_x9_4x4( uint8_t *fenc, uint8_t *fdec, uint16_t *bitcosts )
2367 ;-----------------------------------------------------------------------------
2369 cglobal intra_sad_x9_4x4, 3,4,9
2370 %assign pad 0xc0-gprsize-(stack_offset&15)
2371 %define pred_buf rsp
2374 INTRA_X9_PRED intrax9a, m8
2376 INTRA_X9_PRED intrax9a, [rsp+0xa0]
2385 movd m0, [r0+0*FENC_STRIDE]
2386 pinsrd m0, [r0+1*FENC_STRIDE], 1
2387 movd m1, [r0+2*FENC_STRIDE]
2388 pinsrd m1, [r0+3*FENC_STRIDE], 1
2390 movd mm0, [r0+0*FENC_STRIDE]
2391 punpckldq mm0, [r0+1*FENC_STRIDE]
2392 movd mm1, [r0+2*FENC_STRIDE]
2393 punpckldq mm1, [r0+3*FENC_STRIDE]
2414 %define %%zero [pb_0]
2416 pshufb m3, m7, [intrax9a_vh1]
2417 pshufb m5, m7, [intrax9a_vh2]
2418 pshufb m7, [intrax9a_dc]
2433 movzx r3d, word [r2]
2436 punpckhqdq m3, m0 ; h, dc
2437 shufps m3, m2, q2020
2443 INTRA_X9_END 1, intrax9a
2449 ;-----------------------------------------------------------------------------
2450 ; int intra_satd_x9_4x4( uint8_t *fenc, uint8_t *fdec, uint16_t *bitcosts )
2451 ;-----------------------------------------------------------------------------
2452 cglobal intra_satd_x9_4x4, 3,4,16
2453 %assign pad 0xb0-gprsize-(stack_offset&15)
2454 %define pred_buf rsp
2456 INTRA_X9_PRED intrax9b, m15
2463 movd m8, [r0+0*FENC_STRIDE]
2464 movd m9, [r0+1*FENC_STRIDE]
2465 movd m10, [r0+2*FENC_STRIDE]
2466 movd m11, [r0+3*FENC_STRIDE]
2477 pshufd m1, m2, q3232
2480 call .satd_8x4 ; ddr, ddl
2482 pshufd m3, m5, q3232
2485 pshufd m1, m4, q3232
2486 call .satd_8x4 ; vr, vl
2488 pshufd m3, m7, q3232
2491 pshufd m1, m6, q3232
2492 call .satd_8x4 ; hd, hu
2496 punpcklqdq m4, m0 ; conroe dislikes punpckldq, and ssse3 INTRA_X9_END can handle arbitrary orders whereas phminposuw can't
2498 mova m1, [pw_ppmmppmm]
2503 INTRA_X9_VHDC 15, 8, 10, 6, 7
2508 %if notcpuflag(sse4)
2509 pshufhw m0, m0, q3120 ; compensate for different order in unpack
2513 movzx r0d, word [r2]
2515 INTRA_X9_END 0, intrax9b
2518 RESET_MM_PERMUTATION
2529 SATD_8x4_SSE cpuname, 0, 1, 2, 3, 13, 14, 0, swap
2532 pshufd m1, m0, q0032
2536 paddd xmm0, m0, m1 ; consistent location of return value. only the avx version of hadamard permutes m0, so 3arg is free
2539 %else ; !ARCH_X86_64
2540 cglobal intra_satd_x9_4x4, 3,4,8
2541 %assign pad 0x120-gprsize-(stack_offset&15)
2542 %define fenc_buf rsp
2543 %define pred_buf rsp+0x40
2544 %define spill rsp+0xe0
2546 INTRA_X9_PRED intrax9b, [spill+0x20]
2547 mova [pred_buf+0x00], m2
2548 mova [pred_buf+0x10], m3
2549 mova [pred_buf+0x20], m4
2550 mova [pred_buf+0x30], m5
2551 mova [pred_buf+0x40], m6
2552 mova [pred_buf+0x50], m7
2553 movd m4, [r0+0*FENC_STRIDE]
2554 movd m5, [r0+1*FENC_STRIDE]
2555 movd m6, [r0+2*FENC_STRIDE]
2556 movd m0, [r0+3*FENC_STRIDE]
2566 mova [fenc_buf+0x00], m4
2567 mova [fenc_buf+0x10], m5
2568 mova [fenc_buf+0x20], m6
2569 mova [fenc_buf+0x30], m0
2571 pshufd m1, m2, q3232
2581 call .satd_8x4b ; ddr, ddl
2582 mova m3, [pred_buf+0x30]
2583 mova m1, [pred_buf+0x20]
2586 movq [spill+0x08], m0
2589 call .satd_8x4 ; vr, vl
2590 mova m3, [pred_buf+0x50]
2591 mova m1, [pred_buf+0x40]
2594 movq [spill+0x10], m0
2597 call .satd_8x4 ; hd, hu
2598 movq [spill+0x18], m0
2599 mova m1, [spill+0x20]
2600 mova m4, [fenc_buf+0x00]
2601 mova m5, [fenc_buf+0x20]
2602 mova m2, [pw_ppmmppmm]
2605 paddw m4, [fenc_buf+0x10]
2606 paddw m5, [fenc_buf+0x30]
2607 INTRA_X9_VHDC 1, 4, 5, 6, 7
2611 punpckhqdq m1, [spill+0x00]
2612 packssdw m1, [spill+0x10]
2614 pshufhw m1, m1, q3120
2616 pshufhw m0, m0, q3120
2619 movzx r0d, word [r2]
2621 INTRA_X9_END 0, intrax9b
2624 RESET_MM_PERMUTATION
2631 %xdefine fenc_buf fenc_buf+gprsize
2632 psubw m0, [fenc_buf+0x00]
2633 psubw m1, [fenc_buf+0x10]
2634 psubw m2, [fenc_buf+0x20]
2636 psubw m3, [fenc_buf+0x30]
2637 SATD_8x4_SSE cpuname, 0, 1, 2, 3, 4, 5, 0, swap
2640 pshufd m1, m0, q0032
2647 %endmacro ; INTRA_X9
2652 ;-----------------------------------------------------------------------------
2653 ; int intra_sad_x9_8x8( uint8_t *fenc, uint8_t *fdec, uint8_t edge[36], uint16_t *bitcosts, uint16_t *satds )
2654 ;-----------------------------------------------------------------------------
2655 cglobal intra_sad_x9_8x8, 5,6,9
2665 %assign padbase 0x10
2667 %assign pad 0x240+0x10+padbase-gprsize-(stack_offset&15)
2668 %define pred(i,j) [rsp+i*0x40+j*0x10+padbase]
2671 movq fenc02, [r0+FENC_STRIDE* 0]
2672 movq fenc13, [r0+FENC_STRIDE* 1]
2673 movq fenc46, [r0+FENC_STRIDE* 4]
2674 movq fenc57, [r0+FENC_STRIDE* 5]
2675 movhps fenc02, [r0+FENC_STRIDE* 2]
2676 movhps fenc13, [r0+FENC_STRIDE* 3]
2677 movhps fenc46, [r0+FENC_STRIDE* 6]
2678 movhps fenc57, [r0+FENC_STRIDE* 7]
2680 ; save instruction size: avoid 4-byte memory offsets
2681 lea r0, [intra8x9_h1+128]
2682 %define off(m) (r0+m-(intra8x9_h1+128))
2687 psadbw m1, m0, fenc02
2689 psadbw m2, m0, fenc13
2691 psadbw m3, m0, fenc46
2693 psadbw m0, m0, fenc57
2703 pshufb m1, m0, [off(intra8x9_h1)]
2704 pshufb m2, m0, [off(intra8x9_h2)]
2710 pshufb m3, m0, [off(intra8x9_h3)]
2711 pshufb m2, m0, [off(intra8x9_h4)]
2722 lea r5, [rsp+padbase+0x100]
2723 %define pred(i,j) [r5+i*0x40+j*0x10-0x100]
2735 psadbw m1, m0, fenc02
2737 psadbw m2, m0, fenc13
2739 psadbw m3, m0, fenc46
2741 psadbw m0, m0, fenc57
2750 ; Ft1 Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 Ft8
2751 ; Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 Ft8 Ft9
2752 ; Ft3 Ft4 Ft5 Ft6 Ft7 Ft8 Ft9 FtA
2753 ; Ft4 Ft5 Ft6 Ft7 Ft8 Ft9 FtA FtB
2754 ; Ft5 Ft6 Ft7 Ft8 Ft9 FtA FtB FtC
2755 ; Ft6 Ft7 Ft8 Ft9 FtA FtB FtC FtD
2756 ; Ft7 Ft8 Ft9 FtA FtB FtC FtD FtE
2757 ; Ft8 Ft9 FtA FtB FtC FtD FtE FtF
2761 pavgb m3, m0, m2 ; Gt1 Gt2 Gt3 Gt4 Gt5 Gt6 Gt7 Gt8 Gt9 GtA GtB ___ ___ ___ ___ ___
2762 PRED4x4_LOWPASS m0, m1, m2, m0, tmp ; ___ Ft1 Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 Ft8 Ft9 FtA FtB FtC FtD FtE FtF
2763 pshufb m1, m0, [off(intra8x9_ddl1)]
2764 pshufb m2, m0, [off(intra8x9_ddl2)]
2770 pshufb m2, m0, [off(intra8x9_ddl3)]
2774 pshufb m2, m0, [off(intra8x9_ddl4)]
2783 ; Gt1 Gt2 Gt3 Gt4 Gt5 Gt6 Gt7 Gt8
2784 ; Ft1 Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 Ft8
2785 ; Gt2 Gt3 Gt4 Gt5 Gt6 Gt7 Gt8 Gt9
2786 ; Ft2 Ft3 Ft4 Ft5 Ft6 Ft7 Ft8 Ft9
2787 ; Gt3 Gt4 Gt5 Gt6 Gt7 Gt8 Gt9 GtA
2788 ; Ft3 Ft4 Ft5 Ft6 Ft7 Ft8 Ft9 FtA
2789 ; Gt4 Gt5 Gt6 Gt7 Gt8 Gt9 GtA GtB
2790 ; Ft4 Ft5 Ft6 Ft7 Ft8 Ft9 FtA FtB
2791 pshufb m1, m3, [off(intra8x9_vl1)]
2792 pshufb m2, m0, [off(intra8x9_vl2)]
2793 pshufb m3, m3, [off(intra8x9_vl3)]
2794 pshufb m0, m0, [off(intra8x9_vl4)]
2809 pextrw [r4+14], m0, 0
2813 lea r5, [rsp+padbase+0x100]
2817 ; Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Ft6
2818 ; Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5
2819 ; Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4
2820 ; Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3
2821 ; Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2
2822 ; Fl4 Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1
2823 ; Fl5 Fl4 Fl3 Fl2 Fl1 Fl0 Flt Ft0
2824 ; Fl6 Fl5 Fl4 Fl3 Fl2 Fl1 Fl0 Flt
2828 pavgb m3, m2, m0 ; Gl6 Gl5 Gl4 Gl3 Gl2 Gl1 Gl0 Glt Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 Gt6 Gt7
2829 PRED4x4_LOWPASS m0, m1, m2, m0, tmp ; Fl7 Fl6 Fl5 Fl4 Fl3 Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Ft6
2830 pshufb m1, m0, [off(intra8x9_ddr1)]
2831 pshufb m2, m0, [off(intra8x9_ddr2)]
2837 pshufb m2, m0, [off(intra8x9_ddr3)]
2841 pshufb m2, m0, [off(intra8x9_ddr4)]
2851 %define off(m) (r0+m-(intra8x9_h1+256+128))
2852 %define pred(i,j) [r5+i*0x40+j*0x10-0x1C0]
2855 ; Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 Gt6 Gt7
2856 ; Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 Ft6
2857 ; Fl0 Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 Gt6
2858 ; Fl1 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5
2859 ; Fl2 Fl0 Gt0 Gt1 Gt2 Gt3 Gt4 Gt5
2860 ; Fl3 Fl1 Flt Ft0 Ft1 Ft2 Ft3 Ft4
2861 ; Fl4 Fl2 Fl0 Gt0 Gt1 Gt2 Gt3 Gt4
2862 ; Fl5 Fl3 Fl1 Flt Ft0 Ft1 Ft2 Ft3
2863 movsd m2, m3, m0 ; Fl7 Fl6 Fl5 Fl4 Fl3 Fl2 Fl1 Fl0 Gt0 Gt1 Gt2 Gt3 Gt4 Gt5 Gt6 Gt7
2864 pshufb m1, m2, [off(intra8x9_vr1)]
2865 pshufb m2, m2, [off(intra8x9_vr3)]
2871 pshufb m2, m0, [off(intra8x9_vr2)]
2875 pshufb m2, m0, [off(intra8x9_vr4)]
2884 ; Glt Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5
2885 ; Gl0 Fl0 Glt Flt Ft0 Ft1 Ft2 Ft3
2886 ; Gl1 Fl1 Gl0 Fl0 Glt Flt Ft0 Ft1
2887 ; Gl2 Fl2 Gl1 Fl1 Gl0 Fl0 Glt Flt
2888 ; Gl3 Fl3 Gl2 Fl2 Gl1 Fl1 Gl0 Fl0
2889 ; Gl4 Fl4 Gl3 Fl3 Gl2 Fl2 Gl1 Fl1
2890 ; Gl5 Fl5 Gl4 Fl4 Gl3 Fl3 Gl2 Fl2
2891 ; Gl6 Fl6 Gl5 Fl5 Gl4 Fl4 Gl3 Fl3
2892 pshufd m2, m3, q0001
2894 pblendw m2, m0, q3330 ; Gl2 Gl1 Gl0 Glt ___ Fl2 Fl1 Fl0 Flt Ft0 Ft1 Ft2 Ft3 Ft4 Ft5 ___
2899 punpcklbw m0, m3 ; Fl7 Gl6 Fl6 Gl5 Fl5 Gl4 Fl4 Gl3 Fl3 Gl2 Fl2 Gl1 Fl1 Gl0 Fl0 ___
2900 pshufb m1, m2, [off(intra8x9_hd1)]
2901 pshufb m2, m2, [off(intra8x9_hd2)]
2907 pshufb m2, m0, [off(intra8x9_hd3)]
2908 pshufb m3, m0, [off(intra8x9_hd4)]
2917 ; don't just store to [r4+12]. this is too close to the load of dqword [r4] and would cause a forwarding stall
2922 ; Gl0 Fl1 Gl1 Fl2 Gl2 Fl3 Gl3 Fl4
2923 ; Gl1 Fl2 Gl2 Fl3 Gl3 Fl4 Gl4 Fl5
2924 ; Gl2 Fl3 Gl3 Gl3 Gl4 Fl5 Gl5 Fl6
2925 ; Gl3 Gl3 Gl4 Fl5 Gl5 Fl6 Gl6 Fl7
2926 ; Gl4 Fl5 Gl5 Fl6 Gl6 Fl7 Gl7 Gl7
2927 ; Gl5 Fl6 Gl6 Fl7 Gl7 Gl7 Gl7 Gl7
2928 ; Gl6 Fl7 Gl7 Gl7 Gl7 Gl7 Gl7 Gl7
2929 ; Gl7 Gl7 Gl7 Gl7 Gl7 Gl7 Gl7 Gl7
2931 pinsrb m0, [r2+7], 15 ; Gl7
2938 pshufb m1, m0, [off(intra8x9_hu1)]
2939 pshufb m2, m0, [off(intra8x9_hu2)]
2945 pshufb m2, m0, [off(intra8x9_hu3)]
2946 pshufb m0, m0, [off(intra8x9_hu4)]
2961 movzx r5d, word [r3+16]
2966 phminposuw m0, m0 ; v,h,dc,ddl,ddr,vr,hd,vl
2969 ; 8x8 sad is up to 14 bits; +bitcosts and saturate -> 14 bits; pack with 2 bit index
2972 paddw m0, [off(pw_s00112233)]
2975 pshuflw m1, m0, q0032
2978 ; repack with 3 bit index
2986 ; reverse to phminposuw order
3000 add r1, 4*FDEC_STRIDE
3001 mova m0, [rsp+padbase+r2+0x00]
3002 mova m1, [rsp+padbase+r2+0x10]
3003 mova m2, [rsp+padbase+r2+0x20]
3004 mova m3, [rsp+padbase+r2+0x30]
3005 movq [r1+FDEC_STRIDE*-4], m0
3006 movhps [r1+FDEC_STRIDE*-2], m0
3007 movq [r1+FDEC_STRIDE*-3], m1
3008 movhps [r1+FDEC_STRIDE*-1], m1
3009 movq [r1+FDEC_STRIDE* 0], m2
3010 movhps [r1+FDEC_STRIDE* 2], m2
3011 movq [r1+FDEC_STRIDE* 1], m3
3012 movhps [r1+FDEC_STRIDE* 3], m3
3017 ;-----------------------------------------------------------------------------
3018 ; int intra_sa8d_x9_8x8( uint8_t *fenc, uint8_t *fdec, uint8_t edge[36], uint16_t *bitcosts, uint16_t *satds )
3019 ;-----------------------------------------------------------------------------
3020 cglobal intra_sa8d_x9_8x8, 5,6,16
3021 %assign pad 0x2c0+0x10-gprsize-(stack_offset&15)
3022 %define fenc_buf rsp
3023 %define pred_buf rsp+0x80
3029 movddup m %+ %%i, [r0+%%i*FENC_STRIDE]
3030 pmaddubsw m9, m %+ %%i, m15
3031 punpcklbw m %+ %%i, m8
3032 mova [fenc_buf+%%i*0x10], m9
3036 ; save instruction size: avoid 4-byte memory offsets
3037 lea r0, [intra8x9_h1+0x80]
3038 %define off(m) (r0+m-(intra8x9_h1+0x80))
3039 lea r5, [pred_buf+0x80]
3042 HADAMARD8_2D 0, 1, 2, 3, 4, 5, 6, 7, 8
3051 ; 1D hadamard of edges
3059 pshufb m9, [intrax3_shuf]
3060 pmaddubsw m8, [pb_pppm]
3061 pmaddubsw m9, [pb_pppm]
3062 HSUMSUB2 psignw, m8, m9, m12, m13, m9, q1032, [pw_ppppmmmm]
3063 HSUMSUB2 psignw, m8, m9, m12, m13, m9, q2301, [pw_ppmmppmm]
3079 psllw m8, 3 ; left edge
3082 pabsw m8, m8 ; 1x8 sum
3092 punpcklqdq m0, m4 ; transpose
3093 psllw m9, 3 ; top edge
3094 psrldq m10, m11, 2 ; 8x7 sum
3095 psubw m0, m9 ; 8x1 sum
3099 phaddd m10, m8 ; logically phaddw, but this is faster and it won't overflow
3105 pshufb m0, m3, [off(intra8x9_h1)]
3106 pshufb m1, m3, [off(intra8x9_h2)]
3107 pshufb m2, m3, [off(intra8x9_h3)]
3108 pshufb m3, m3, [off(intra8x9_h4)]
3119 PRED4x4_LOWPASS m8, m1, m2, m8, m3
3120 pshufb m0, m8, [off(intra8x9_ddl1)]
3121 pshufb m1, m8, [off(intra8x9_ddl2)]
3122 pshufb m2, m8, [off(intra8x9_ddl3)]
3123 pshufb m3, m8, [off(intra8x9_ddl4)]
3129 pshufb m0, m9, [off(intra8x9_vl1)]
3130 pshufb m1, m8, [off(intra8x9_vl2)]
3131 pshufb m2, m9, [off(intra8x9_vl3)]
3132 pshufb m3, m8, [off(intra8x9_vl4)]
3143 PRED4x4_LOWPASS m8, m1, m2, m8, m3
3144 pshufb m0, m8, [off(intra8x9_ddr1)]
3145 pshufb m1, m8, [off(intra8x9_ddr2)]
3146 pshufb m2, m8, [off(intra8x9_ddr3)]
3147 pshufb m3, m8, [off(intra8x9_ddr4)]
3153 %define off(m) (r0+m-(intra8x9_h1+0x180))
3157 pshufb m0, m2, [off(intra8x9_vr1)]
3158 pshufb m1, m8, [off(intra8x9_vr2)]
3159 pshufb m2, m2, [off(intra8x9_vr3)]
3160 pshufb m3, m8, [off(intra8x9_vr4)]
3167 pshufd m1, m9, q0001
3168 pblendw m1, m8, q3330
3170 pshufd m2, m9, q0001
3174 pshufb m0, m1, [off(intra8x9_hd1)]
3175 pshufb m1, m1, [off(intra8x9_hd2)]
3176 pshufb m2, m8, [off(intra8x9_hd3)]
3177 pshufb m3, m8, [off(intra8x9_hd4)]
3185 pinsrb m8, [r2+7], 15
3192 pshufb m0, m8, [off(intra8x9_hu1)]
3193 pshufb m1, m8, [off(intra8x9_hu2)]
3194 pshufb m2, m8, [off(intra8x9_hu3)]
3195 pshufb m3, m8, [off(intra8x9_hu4)]
3203 pshuflw m1, m0, q0032
3212 movzx r5d, word [r3+16]
3220 ; 8x8 sa8d is up to 15 bits; +bitcosts and saturate -> 15 bits; pack with 1 bit index
3222 paddw m0, [off(pw_s00001111)]
3225 pshuflw m1, m0, q0032
3228 pcmpgtw m2, m1 ; 2nd index bit
3231 ; repack with 3 bit index
3239 lea r3d, [ r3*4+r4+1]
3242 ; reverse to phminposuw order
3256 add r1, 4*FDEC_STRIDE
3257 mova m0, [pred_buf+r2+0x00]
3258 mova m1, [pred_buf+r2+0x10]
3259 mova m2, [pred_buf+r2+0x20]
3260 mova m3, [pred_buf+r2+0x30]
3261 movq [r1+FDEC_STRIDE*-4], m0
3262 movhps [r1+FDEC_STRIDE*-2], m0
3263 movq [r1+FDEC_STRIDE*-3], m1
3264 movhps [r1+FDEC_STRIDE*-1], m1
3265 movq [r1+FDEC_STRIDE* 0], m2
3266 movhps [r1+FDEC_STRIDE* 2], m2
3267 movq [r1+FDEC_STRIDE* 1], m3
3268 movhps [r1+FDEC_STRIDE* 3], m3
3275 %xdefine fenc_buf fenc_buf+gprsize
3288 PERMUTE 0,4, 1,5, 2,0, 3,1, 4,6, 5,7, 6,2, 7,3
3291 psubw m0, [fenc_buf+0x00]
3292 psubw m1, [fenc_buf+0x10]
3295 psubw m2, [fenc_buf+0x20]
3296 psubw m3, [fenc_buf+0x30]
3299 psubw m4, [fenc_buf+0x40]
3300 psubw m5, [fenc_buf+0x50]
3303 psubw m6, [fenc_buf+0x60]
3304 psubw m7, [fenc_buf+0x70]
3305 HADAMARD8_2D_HMUL 0, 1, 2, 3, 4, 5, 6, 7, 13, 14
3310 %endif ; ARCH_X86_64
3311 %endmacro ; INTRA8_X9
3313 ; in: r0=pix, r1=stride, r2=stride*3, r3=tmp, m6=mask_ac4, m7=0
3314 ; out: [tmp]=hadamard4, m0=satd
3316 cglobal hadamard_ac_4x4
3322 %else ; !HIGH_BIT_DEPTH
3331 %endif ; HIGH_BIT_DEPTH
3332 HADAMARD4_2D 0, 1, 2, 3, 4
3348 cglobal hadamard_ac_2x2max
3354 SUMSUB_BADC w, 0, 1, 2, 3, 4
3355 ABSW2 m0, m2, m0, m2, m4, m5
3356 ABSW2 m1, m3, m1, m3, m4, m5
3357 HADAMARD 0, max, 0, 2, 4, 5
3358 HADAMARD 0, max, 1, 3, 4, 5
3364 %else ; !HIGH_BIT_DEPTH
3367 %endif ; HIGH_BIT_DEPTH
3383 %endif ; HIGH_BIT_DEPTH
3386 cglobal hadamard_ac_8x8
3392 %endif ; HIGH_BIT_DEPTH
3393 call hadamard_ac_4x4_mmx2
3394 add r0, 4*SIZEOF_PIXEL
3398 call hadamard_ac_4x4_mmx2
3402 call hadamard_ac_4x4_mmx2
3403 sub r0, 4*SIZEOF_PIXEL
3406 call hadamard_ac_4x4_mmx2
3409 mova [rsp+gprsize+8], m5 ; save satd
3414 call hadamard_ac_2x2max_mmx2
3420 SUMSUB_BADC w, 0, 1, 2, 3, 4
3421 HADAMARD 0, sumsub, 0, 2, 4, 5
3422 ABSW2 m1, m3, m1, m3, m4, m5
3423 ABSW2 m0, m2, m0, m2, m4, m5
3424 HADAMARD 0, max, 1, 3, 4, 5
3435 %else ; !HIGH_BIT_DEPTH
3441 %endif ; HIGH_BIT_DEPTH
3442 mova [rsp+gprsize], m6 ; save sa8d
3447 %macro HADAMARD_AC_WXH_SUM_MMX 2
3448 mova m1, [rsp+1*mmsize]
3451 paddd m0, [rsp+2*mmsize]
3452 paddd m1, [rsp+3*mmsize]
3455 mova m2, [rsp+4*mmsize]
3456 paddd m1, [rsp+5*mmsize]
3457 paddd m2, [rsp+6*mmsize]
3459 paddd m1, [rsp+7*mmsize]
3466 %else ; !HIGH_BIT_DEPTH
3468 paddusw m0, [rsp+2*mmsize]
3469 paddusw m1, [rsp+3*mmsize]
3472 mova m2, [rsp+4*mmsize]
3473 paddusw m1, [rsp+5*mmsize]
3474 paddusw m2, [rsp+6*mmsize]
3476 paddusw m1, [rsp+7*mmsize]
3488 %endif ; HIGH_BIT_DEPTH
3491 %macro HADAMARD_AC_WXH_MMX 2
3492 cglobal pixel_hadamard_ac_%1x%2, 2,4
3493 %assign pad 16-gprsize-(stack_offset&15)
3499 call hadamard_ac_8x8_mmx2
3504 call hadamard_ac_8x8_mmx2
3509 lea r0, [r0+ysub*4+8*SIZEOF_PIXEL]
3511 call hadamard_ac_8x8_mmx2
3515 call hadamard_ac_8x8_mmx2
3518 HADAMARD_AC_WXH_SUM_MMX %1, %2
3526 add rsp, 128+%1*%2/4+pad
3528 %endmacro ; HADAMARD_AC_WXH_MMX
3530 HADAMARD_AC_WXH_MMX 16, 16
3531 HADAMARD_AC_WXH_MMX 8, 16
3532 HADAMARD_AC_WXH_MMX 16, 8
3533 HADAMARD_AC_WXH_MMX 8, 8
3535 %macro LOAD_INC_8x4W_SSE2 5
3544 %else ; !HIGH_BIT_DEPTH
3556 %endif ; HIGH_BIT_DEPTH
3559 %macro LOAD_INC_8x4W_SSSE3 5
3560 LOAD_DUP_4x8P %3, %4, %1, %2, [r0+r1*2], [r0+r2], [r0], [r0+r1]
3564 HSUMSUB %1, %2, %3, %4, %5
3567 %macro HADAMARD_AC_SSE2 0
3568 ; in: r0=pix, r1=stride, r2=stride*3
3569 ; out: [esp+16]=sa8d, [esp+32]=satd, r0+=stride*4
3570 cglobal hadamard_ac_8x8
3576 %define spill0 [rsp+gprsize]
3577 %define spill1 [rsp+gprsize+16]
3578 %define spill2 [rsp+gprsize+32]
3582 %elif cpuflag(ssse3)
3584 ;LOAD_INC loads sumsubs
3588 ;LOAD_INC only unpacks to words
3591 LOAD_INC_8x4W 0, 1, 2, 3, 7
3593 HADAMARD4_2D_SSE 0, 1, 2, 3, 4
3595 HADAMARD4_V 0, 1, 2, 3, 4
3599 LOAD_INC_8x4W 4, 5, 6, 7, 1
3601 HADAMARD4_2D_SSE 4, 5, 6, 7, 1
3603 HADAMARD4_V 4, 5, 6, 7, 1
3608 HADAMARD 1, sumsub, 0, 1, 6, 7
3609 HADAMARD 1, sumsub, 2, 3, 6, 7
3614 HADAMARD 1, sumsub, 4, 5, 1, 0
3615 HADAMARD 1, sumsub, 6, 7, 1, 0
3628 pand m1, [mask_ac4b]
3632 AC_PADD m1, m3, [pw_1]
3634 AC_PADD m1, m2, [pw_1]
3636 AC_PADD m1, m3, [pw_1]
3638 AC_PADD m1, m2, [pw_1]
3640 AC_PADD m1, m3, [pw_1]
3642 AC_PADD m1, m2, [pw_1]
3646 mova [rsp+gprsize+32], m1 ; save satd
3657 HADAMARD %%x, amax, 3, 7, 4
3658 HADAMARD %%x, amax, 2, 6, 7, 4
3660 HADAMARD %%x, amax, 1, 5, 6, 7
3661 HADAMARD %%x, sumsub, 0, 4, 5, 6
3663 AC_PADD m2, m3, [pw_1]
3664 AC_PADD m2, m1, [pw_1]
3669 %endif ; HIGH_BIT_DEPTH
3673 AC_PADD m2, m4, [pw_1]
3674 AC_PADD m2, m0, [pw_1]
3675 mova [rsp+gprsize+16], m2 ; save sa8d
3680 HADAMARD_AC_WXH_SSE2 16, 16
3681 HADAMARD_AC_WXH_SSE2 8, 16
3682 HADAMARD_AC_WXH_SSE2 16, 8
3683 HADAMARD_AC_WXH_SSE2 8, 8
3684 %endmacro ; HADAMARD_AC_SSE2
3686 %macro HADAMARD_AC_WXH_SUM_SSE2 2
3687 mova m1, [rsp+2*mmsize]
3690 paddd m0, [rsp+3*mmsize]
3691 paddd m1, [rsp+4*mmsize]
3694 paddd m0, [rsp+5*mmsize]
3695 paddd m1, [rsp+6*mmsize]
3696 paddd m0, [rsp+7*mmsize]
3697 paddd m1, [rsp+8*mmsize]
3702 %else ; !HIGH_BIT_DEPTH
3704 paddusw m0, [rsp+3*mmsize]
3705 paddusw m1, [rsp+4*mmsize]
3708 paddusw m0, [rsp+5*mmsize]
3709 paddusw m1, [rsp+6*mmsize]
3710 paddusw m0, [rsp+7*mmsize]
3711 paddusw m1, [rsp+8*mmsize]
3716 %endif ; HIGH_BIT_DEPTH
3719 ; struct { int satd, int sa8d; } pixel_hadamard_ac_16x16( uint8_t *pix, int stride )
3720 %macro HADAMARD_AC_WXH_SSE2 2
3721 cglobal pixel_hadamard_ac_%1x%2, 2,3,11
3722 %assign pad 16-gprsize-(stack_offset&15)
3727 call hadamard_ac_8x8
3732 call hadamard_ac_8x8
3737 lea r0, [r0+ysub*4+8*SIZEOF_PIXEL]
3739 call hadamard_ac_8x8
3743 call hadamard_ac_8x8
3746 HADAMARD_AC_WXH_SUM_SSE2 %1, %2
3749 shr edx, 2 - (%1*%2 >> 8)
3755 add rsp, 16+%1*%2/2+pad
3757 %endmacro ; HADAMARD_AC_WXH_SSE2
3761 %if ARCH_X86_64 == 0
3762 cextern pixel_sa8d_8x8_internal_mmx2
3767 %define TRANS TRANS_SSE2
3768 %define DIFFOP DIFF_UNPACK_SSE2
3769 %define LOAD_INC_8x4W LOAD_INC_8x4W_SSE2
3770 %define LOAD_SUMSUB_8x4P LOAD_DIFF_8x4P
3771 %define LOAD_SUMSUB_16P LOAD_SUMSUB_16P_SSE2
3772 %define movdqa movaps ; doesn't hurt pre-nehalem, might as well save size
3773 %define movdqu movups
3774 %define punpcklqdq movlhps
3778 %if HIGH_BIT_DEPTH == 0
3786 %define DIFFOP DIFF_SUMSUB_SSSE3
3787 %define LOAD_DUP_4x8P LOAD_DUP_4x8P_CONROE
3788 %if HIGH_BIT_DEPTH == 0
3789 %define LOAD_INC_8x4W LOAD_INC_8x4W_SSSE3
3790 %define LOAD_SUMSUB_8x4P LOAD_SUMSUB_8x4P_SSSE3
3791 %define LOAD_SUMSUB_16P LOAD_SUMSUB_16P_SSSE3
3797 %if HIGH_BIT_DEPTH == 0
3801 %undef movdqa ; nehalem doesn't like movaps
3802 %undef movdqu ; movups
3803 %undef punpcklqdq ; or movlhps
3804 %if HIGH_BIT_DEPTH == 0
3809 %define TRANS TRANS_SSE4
3810 %define LOAD_DUP_4x8P LOAD_DUP_4x8P_PENRYN
3815 %if HIGH_BIT_DEPTH == 0
3823 %if HIGH_BIT_DEPTH == 0
3829 %define TRANS TRANS_XOP
3833 %if HIGH_BIT_DEPTH == 0
3835 ; no xop INTRA8_X9. it's slower than avx on bulldozer. dunno why.
3839 ;=============================================================================
3841 ;=============================================================================
3843 ;-----------------------------------------------------------------------------
3844 ; void pixel_ssim_4x4x2_core( const uint8_t *pix1, intptr_t stride1,
3845 ; const uint8_t *pix2, intptr_t stride2, int sums[2][4] )
3846 ;-----------------------------------------------------------------------------
3849 movdqu m5, [r0+(%1&1)*r1]
3850 movdqu m6, [r2+(%1&1)*r3]
3852 movq m5, [r0+(%1&1)*r1]
3853 movq m6, [r2+(%1&1)*r3]
3871 ACCUM paddd, 3, 5, %1
3872 ACCUM paddd, 4, 7, %1
3877 cglobal pixel_ssim_4x4x2_core, 4,4,8
3887 pshufd m5, m3, q2301
3890 pshufd m6, m4, q2301
3893 pshufd m1, m1, q3120
3896 punpckhdq m5, m3, m4
3912 ;-----------------------------------------------------------------------------
3913 ; float pixel_ssim_end( int sum0[5][4], int sum1[5][4], int width )
3914 ;-----------------------------------------------------------------------------
3915 cglobal pixel_ssim_end4, 3,3,7
3930 movdqa m5, [ssim_c1]
3931 movdqa m6, [ssim_c2]
3932 TRANSPOSE4x4D 0, 1, 2, 3, 4
3934 ; s1=m0, s2=m1, ss=m2, s12=m3
3940 mulps m2, [pf_64] ; ss*64
3941 mulps m3, [pf_128] ; s12*128
3943 mulps m4, m0 ; s1*s2
3944 mulps m1, m1 ; s2*s2
3945 mulps m0, m0 ; s1*s1
3946 addps m4, m4 ; s1*s2*2
3947 addps m0, m1 ; s1*s1 + s2*s2
3949 subps m3, m4 ; covar*2
3950 addps m4, m5 ; s1*s2*2 + ssim_c1
3951 addps m0, m5 ; s1*s1 + s2*s2 + ssim_c1
3952 addps m2, m6 ; vars + ssim_c2
3953 addps m3, m6 ; covar*2 + ssim_c2
3955 pmaddwd m4, m1, m0 ; s1*s2
3958 pmaddwd m0, m0 ; s1*s1 + s2*s2
3962 psubd m3, m4 ; covar*2
3968 cvtdq2ps m0, m0 ; (float)(s1*s1 + s2*s2 + ssim_c1)
3969 cvtdq2ps m4, m4 ; (float)(s1*s2*2 + ssim_c1)
3970 cvtdq2ps m3, m3 ; (float)(covar*2 + ssim_c2)
3971 cvtdq2ps m2, m2 ; (float)(vars + ssim_c2)
3978 je .skip ; faster only if this is the common case; remove branch if we use ssim on a macroblock level
3981 lea r3, [mask_ff + 16]
3982 movdqu m1, [r3 + r2*4]
3984 movdqu m1, [mask_ff + r2*4 + 16]
3990 pshuflw m4, m0, q0032
3992 %if ARCH_X86_64 == 0
4004 ;-----------------------------------------------------------------------------
4005 ; int pixel_asd8( pixel *pix1, intptr_t stride1, pixel *pix2, intptr_t stride2, int height );
4006 ;-----------------------------------------------------------------------------
4008 cglobal pixel_asd8, 5,5
4071 ;=============================================================================
4072 ; Successive Elimination ADS
4073 ;=============================================================================
4087 %macro ADS_END 1 ; unroll_size
4093 WIN64_RESTORE_XMM rsp
4097 ;-----------------------------------------------------------------------------
4098 ; int pixel_ads4( int enc_dc[4], uint16_t *sums, int delta,
4099 ; uint16_t *cost_mvx, int16_t *mvs, int width, int thresh )
4100 ;-----------------------------------------------------------------------------
4102 cglobal pixel_ads4, 5,7
4106 pshufw mm6, mm6, q2222
4108 pshufw mm4, mm4, q2222
4118 movq mm3, [r1+r2+16]
4133 cglobal pixel_ads2, 5,7
4137 pshufw mm6, mm6, q2222
4154 cglobal pixel_ads1, 5,7
4176 cglobal pixel_ads4, 5,7,12
4178 pshuflw xmm7, xmm4, 0
4179 pshuflw xmm6, xmm4, q2222
4180 pshufhw xmm5, xmm4, 0
4181 pshufhw xmm4, xmm4, q2222
4182 punpcklqdq xmm7, xmm7
4183 punpcklqdq xmm6, xmm6
4184 punpckhqdq xmm5, xmm5
4185 punpckhqdq xmm4, xmm4
4187 pshuflw xmm8, r6m, 0
4188 punpcklqdq xmm8, xmm8
4191 movdqu xmm11, [r1+r2]
4193 psubw xmm0, xmm10, xmm7
4194 movdqu xmm10, [r1+16]
4195 psubw xmm1, xmm10, xmm6
4196 ABSW xmm0, xmm0, xmm2
4197 ABSW xmm1, xmm1, xmm3
4198 psubw xmm2, xmm11, xmm5
4199 movdqu xmm11, [r1+r2+16]
4201 psubw xmm3, xmm11, xmm4
4203 ABSW xmm2, xmm2, xmm1
4204 ABSW xmm3, xmm3, xmm1
4208 psubusw xmm1, xmm8, xmm0
4215 movdqu xmm1, [r1+16]
4218 ABSW xmm0, xmm0, xmm2
4219 ABSW xmm1, xmm1, xmm3
4220 movdqu xmm2, [r1+r2]
4221 movdqu xmm3, [r1+r2+16]
4225 ABSW xmm2, xmm2, xmm1
4226 ABSW xmm3, xmm3, xmm1
4231 pshuflw xmm1, xmm1, 0
4232 punpcklqdq xmm1, xmm1
4240 cglobal pixel_ads2, 5,7,8
4243 pshuflw xmm7, xmm6, 0
4244 pshuflw xmm6, xmm6, q2222
4245 pshuflw xmm5, xmm5, 0
4246 punpcklqdq xmm7, xmm7
4247 punpcklqdq xmm6, xmm6
4248 punpcklqdq xmm5, xmm5
4252 movdqu xmm1, [r1+r2]
4256 ABSW xmm0, xmm0, xmm2
4257 ABSW xmm1, xmm1, xmm3
4260 psubusw xmm1, xmm5, xmm0
4265 cglobal pixel_ads1, 5,7,8
4268 pshuflw xmm7, xmm7, 0
4269 pshuflw xmm6, xmm6, 0
4270 punpcklqdq xmm7, xmm7
4271 punpcklqdq xmm6, xmm6
4275 movdqu xmm1, [r1+16]
4279 movdqu xmm3, [r3+16]
4280 ABSW xmm0, xmm0, xmm4
4281 ABSW xmm1, xmm1, xmm5
4284 psubusw xmm4, xmm6, xmm0
4285 psubusw xmm5, xmm6, xmm1
4298 ; int pixel_ads_mvs( int16_t *mvs, uint8_t *masks, int width )
4301 ; *(uint32_t*)(masks+width) = 0;
4302 ; for( i=0; i<width; i+=8 )
4304 ; uint64_t mask = *(uint64_t*)(masks+i);
4305 ; if( !mask ) continue;
4306 ; for( j=0; j<8; j++ )
4307 ; if( mask & (255<<j*8) )
4315 test r2d, 0xff<<(%1*8)
4322 cglobal pixel_ads_mvs, 0,7,0
4329 ; clear last block in case width isn't divisible by 8. (assume divisible by 4, so clearing 4 bytes is enough.)