1 ;*****************************************************************************
2 ;* sad-a.asm: h264 encoder library
3 ;*****************************************************************************
4 ;* Copyright (C) 2003-2008 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Fiona Glaser <fiona@x264.com>
8 ;* Laurent Aimar <fenrir@via.ecp.fr>
9 ;* Alex Izvorski <aizvorksi@gmail.com>
11 ;* This program is free software; you can redistribute it and/or modify
12 ;* it under the terms of the GNU General Public License as published by
13 ;* the Free Software Foundation; either version 2 of the License, or
14 ;* (at your option) any later version.
16 ;* This program is distributed in the hope that it will be useful,
17 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;* GNU General Public License for more details.
21 ;* You should have received a copy of the GNU General Public License
22 ;* along with this program; if not, write to the Free Software
23 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
24 ;*****************************************************************************
27 %include "x86util.asm"
37 ;=============================================================================
39 ;=============================================================================
41 %macro SAD_INC_2x16P 0
72 punpckldq mm1, [r0+r1]
73 punpckldq mm2, [r2+r3]
80 ;-----------------------------------------------------------------------------
81 ; int pixel_sad_16x16( uint8_t *, int, uint8_t *, int )
82 ;-----------------------------------------------------------------------------
84 cglobal pixel_sad_%1x%2_mmxext, 4,4
103 ;=============================================================================
105 ;=============================================================================
107 %macro SAD_END_SSE2 0
115 ;-----------------------------------------------------------------------------
116 ; int pixel_sad_16x16( uint8_t *, int, uint8_t *, int )
117 ;-----------------------------------------------------------------------------
118 cglobal pixel_sad_16x16_%1, 4,4,8
182 ;-----------------------------------------------------------------------------
183 ; int pixel_sad_16x8( uint8_t *, int, uint8_t *, int )
184 ;-----------------------------------------------------------------------------
185 cglobal pixel_sad_16x8_%1, 4,4
224 %define movdqu movdqa
228 %macro SAD_INC_4x8P_SSE 1
251 ;Even on Nehalem, no sizes other than 8x16 benefit from this method.
252 cglobal pixel_sad_8x16_sse2, 4,4
260 ;-----------------------------------------------------------------------------
261 ; void intra_sad_x3_4x4( uint8_t *fenc, uint8_t *fdec, int res[3] );
262 ;-----------------------------------------------------------------------------
264 cglobal intra_sad_x3_4x4_mmxext, 3,3
266 movd mm0, [r1-FDEC_STRIDE]
267 movd mm1, [r0+FENC_STRIDE*0]
268 movd mm2, [r0+FENC_STRIDE*2]
270 punpckldq mm1, [r0+FENC_STRIDE*1]
271 punpckldq mm2, [r0+FENC_STRIDE*3]
277 movd [r2], mm0 ;V prediction cost
278 movd mm3, [r1+FDEC_STRIDE*0-4]
279 movd mm0, [r1+FDEC_STRIDE*1-4]
280 movd mm4, [r1+FDEC_STRIDE*2-4]
281 movd mm5, [r1+FDEC_STRIDE*3-4]
295 pshufw mm5, mm5, 0x0 ;DC prediction
303 movd [r2+8], mm5 ;DC prediction cost
304 movd [r2+4], mm1 ;H prediction cost
307 ;-----------------------------------------------------------------------------
308 ; void intra_sad_x3_8x8( uint8_t *fenc, uint8_t edge[33], int res[3]);
309 ;-----------------------------------------------------------------------------
320 %macro INTRA_SAD_HVDC_ITER 2
321 movq m5, [r0+FENC_STRIDE*%1]
346 cglobal intra_sad_x3_8x8_mmxext, 3,3
349 movq m6, [r1+16] ;V prediction
357 pshufw m0, m0, 0x0 ;DC prediction
359 INTRA_SAD_HVDC_ITER 0, 0xff
360 INTRA_SAD_HVDC_ITER 1, 0xaa
361 INTRA_SAD_HVDC_ITER 2, 0x55
362 INTRA_SAD_HVDC_ITER 3, 0x00
365 INTRA_SAD_HVDC_ITER 4, 0xff
366 INTRA_SAD_HVDC_ITER 5, 0xaa
367 INTRA_SAD_HVDC_ITER 6, 0x55
368 INTRA_SAD_HVDC_ITER 7, 0x00
374 ;-----------------------------------------------------------------------------
375 ; void intra_sad_x3_8x8c( uint8_t *fenc, uint8_t *fdec, int res[3] );
376 ;-----------------------------------------------------------------------------
378 %macro INTRA_SAD_HV_ITER 2
380 movd m1, [r1 + FDEC_STRIDE*(%1-4) - 4]
381 movd m3, [r1 + FDEC_STRIDE*(%1-3) - 4]
385 movq m1, [r1 + FDEC_STRIDE*(%1-4) - 8]
386 movq m3, [r1 + FDEC_STRIDE*(%1-3) - 8]
392 movq m4, [r0 + FENC_STRIDE*(%1+0)]
393 movq m5, [r0 + FENC_STRIDE*(%1+1)]
409 %macro INTRA_SAD_8x8C 1
410 cglobal intra_sad_x3_8x8c_%1, 3,3
411 movq m6, [r1 - FDEC_STRIDE]
412 add r1, FDEC_STRIDE*4
416 INTRA_SAD_HV_ITER 0, %1
417 INTRA_SAD_HV_ITER 2, %1
418 INTRA_SAD_HV_ITER 4, %1
419 INTRA_SAD_HV_ITER 6, %1
423 movq m2, [r1 + FDEC_STRIDE*-4 - 8]
424 movq m4, [r1 + FDEC_STRIDE*-2 - 8]
425 movq m3, [r1 + FDEC_STRIDE* 0 - 8]
426 movq m5, [r1 + FDEC_STRIDE* 2 - 8]
427 punpckhbw m2, [r1 + FDEC_STRIDE*-3 - 8]
428 punpckhbw m4, [r1 + FDEC_STRIDE*-1 - 8]
429 punpckhbw m3, [r1 + FDEC_STRIDE* 1 - 8]
430 punpckhbw m5, [r1 + FDEC_STRIDE* 3 - 8]
445 punpckldq m0, m2 ;s0 s1 s2 s3
446 pshufw m3, m0, 11110110b ;s2,s1,s3,s3
447 pshufw m0, m0, 01110100b ;s0,s1,s3,s1
450 pavgw m0, m7 ; s0+s2, s1, s3, s1+s3
453 pshufb xmm0, [pb_shuf8x8c]
454 movq xmm1, [r0+FENC_STRIDE*0]
455 movq xmm2, [r0+FENC_STRIDE*1]
456 movq xmm3, [r0+FENC_STRIDE*2]
457 movq xmm4, [r0+FENC_STRIDE*3]
458 movhps xmm1, [r0+FENC_STRIDE*4]
459 movhps xmm2, [r0+FENC_STRIDE*5]
460 movhps xmm3, [r0+FENC_STRIDE*6]
461 movhps xmm4, [r0+FENC_STRIDE*7]
476 punpcklbw m0, m0 ; 4x dc0 4x dc1
477 punpckhbw m1, m1 ; 4x dc2 4x dc3
478 movq m2, [r0+FENC_STRIDE*0]
479 movq m3, [r0+FENC_STRIDE*1]
480 movq m4, [r0+FENC_STRIDE*2]
481 movq m5, [r0+FENC_STRIDE*3]
482 movq m6, [r0+FENC_STRIDE*4]
483 movq m7, [r0+FENC_STRIDE*5]
488 movq m0, [r0+FENC_STRIDE*6]
492 psadbw m1, [r0+FENC_STRIDE*7]
506 INTRA_SAD_8x8C mmxext
510 ;-----------------------------------------------------------------------------
511 ; void intra_sad_x3_16x16( uint8_t *fenc, uint8_t *fdec, int res[3] );
512 ;-----------------------------------------------------------------------------
514 ;xmm7: DC prediction xmm6: H prediction xmm5: V prediction
515 ;xmm4: DC pred score xmm3: H pred score xmm2: V pred score
516 %macro INTRA_SAD16 1-2 0
517 cglobal intra_sad_x3_16x16_%1,3,5,%2
520 psadbw mm0, [r1-FDEC_STRIDE+0]
521 psadbw mm1, [r1-FDEC_STRIDE+8]
529 movzx r4d, byte [r1-1+FDEC_STRIDE*(x&3)]
530 %if (x&3)==3 && x!=15
531 add r1, FDEC_STRIDE*4
536 sub r1, FDEC_STRIDE*12
541 mova m5, [r1-FDEC_STRIDE]
545 mova m1, [r1-FDEC_STRIDE+8]
551 mov r3d, 15*FENC_STRIDE
553 SPLATB m6, r1+r3*2-1, m1
576 add r3d, -FENC_STRIDE
595 %define SPLATB SPLATB_MMX
599 %define SPLATB SPLATB_SSSE3
604 ;=============================================================================
606 ;=============================================================================
608 %macro SAD_X3_START_1x8P 0
631 %macro SAD_X3_START_2x4P 3
636 punpckldq mm3, [r0+FENC_STRIDE]
637 punpckldq %1, [r1+r4]
638 punpckldq %2, [r2+r4]
639 punpckldq %3, [r3+r4]
645 %macro SAD_X3_2x16P 1
652 SAD_X3_1x8P FENC_STRIDE, r4
653 SAD_X3_1x8P FENC_STRIDE+8, r4+8
654 add r0, 2*FENC_STRIDE
666 SAD_X3_1x8P FENC_STRIDE, r4
667 add r0, 2*FENC_STRIDE
675 SAD_X3_START_2x4P mm0, mm1, mm2
677 SAD_X3_START_2x4P mm4, mm5, mm6
682 add r0, 2*FENC_STRIDE
688 %macro SAD_X4_START_1x8P 0
715 %macro SAD_X4_START_2x4P 0
721 punpckldq mm7, [r0+FENC_STRIDE]
722 punpckldq mm0, [r1+r5]
723 punpckldq mm1, [r2+r5]
724 punpckldq mm2, [r3+r5]
725 punpckldq mm3, [r4+r5]
732 %macro SAD_X4_INC_2x4P 0
736 punpckldq mm7, [r0+FENC_STRIDE]
737 punpckldq mm4, [r1+r5]
738 punpckldq mm5, [r2+r5]
745 punpckldq mm4, [r3+r5]
746 punpckldq mm5, [r4+r5]
753 %macro SAD_X4_2x16P 1
760 SAD_X4_1x8P FENC_STRIDE, r5
761 SAD_X4_1x8P FENC_STRIDE+8, r5+8
762 add r0, 2*FENC_STRIDE
775 SAD_X4_1x8P FENC_STRIDE, r5
776 add r0, 2*FENC_STRIDE
789 add r0, 2*FENC_STRIDE
819 ;-----------------------------------------------------------------------------
820 ; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
821 ; uint8_t *pix2, int i_stride, int scores[3] )
822 ;-----------------------------------------------------------------------------
824 cglobal pixel_sad_x%1_%2x%3_mmxext, %1+2, %1+2
827 movsxd r %+ i, r %+ i %+ d
853 ;=============================================================================
855 ;=============================================================================
857 %macro SAD_X3_START_1x16P_SSE2 0
867 %macro SAD_X3_1x16P_SSE2 2
880 %macro SAD_X3_2x16P_SSE2 1
882 SAD_X3_START_1x16P_SSE2
884 SAD_X3_1x16P_SSE2 0, 0
886 SAD_X3_1x16P_SSE2 FENC_STRIDE, r4
887 add r0, 2*FENC_STRIDE
893 %macro SAD_X3_START_2x8P_SSE2 0
898 movhps xmm7, [r0+FENC_STRIDE]
907 %macro SAD_X3_2x8P_SSE2 0
912 movhps xmm7, [r0+FENC_STRIDE]
924 %macro SAD_X4_START_2x8P_SSE2 0
930 movhps xmm7, [r0+FENC_STRIDE]
941 %macro SAD_X4_2x8P_SSE2 0
948 movhps xmm7, [r0+FENC_STRIDE]
962 movhps xmm7, [r0+FENC_STRIDE]
980 %macro SAD_X4_START_1x16P_SSE2 0
992 %macro SAD_X4_1x16P_SSE2 2
1012 movdqu xmm4, [r4+%2]
1020 %macro SAD_X4_2x16P_SSE2 1
1022 SAD_X4_START_1x16P_SSE2
1024 SAD_X4_1x16P_SSE2 0, 0
1026 SAD_X4_1x16P_SSE2 FENC_STRIDE, r5
1027 add r0, 2*FENC_STRIDE
1034 %macro SAD_X3_2x8P_SSE2 1
1036 SAD_X3_START_2x8P_SSE2
1040 add r0, 2*FENC_STRIDE
1046 %macro SAD_X4_2x8P_SSE2 1
1048 SAD_X4_START_2x8P_SSE2
1052 add r0, 2*FENC_STRIDE
1059 %macro SAD_X3_END_SSE2 0
1079 %macro SAD_X4_END_SSE2 0
1094 %macro SAD_X3_START_1x16P_SSE2_MISALIGN 0
1103 %macro SAD_X3_1x16P_SSE2_MISALIGN 2
1104 movdqa xmm3, [r0+%1]
1105 movdqu xmm4, [r1+%2]
1106 movdqu xmm5, [r2+%2]
1109 psadbw xmm3, [r3+%2]
1115 %macro SAD_X4_START_1x16P_SSE2_MISALIGN 0
1126 %macro SAD_X4_1x16P_SSE2_MISALIGN 2
1127 movdqa xmm7, [r0+%1]
1128 movdqu xmm4, [r1+%2]
1129 movdqu xmm5, [r2+%2]
1130 movdqu xmm6, [r3+%2]
1134 psadbw xmm7, [r4+%2]
1141 %macro SAD_X3_2x16P_SSE2_MISALIGN 1
1143 SAD_X3_START_1x16P_SSE2_MISALIGN
1145 SAD_X3_1x16P_SSE2_MISALIGN 0, 0
1147 SAD_X3_1x16P_SSE2_MISALIGN FENC_STRIDE, r4
1148 add r0, 2*FENC_STRIDE
1154 %macro SAD_X4_2x16P_SSE2_MISALIGN 1
1156 SAD_X4_START_1x16P_SSE2_MISALIGN
1158 SAD_X4_1x16P_SSE2_MISALIGN 0, 0
1160 SAD_X4_1x16P_SSE2_MISALIGN FENC_STRIDE, r5
1161 add r0, 2*FENC_STRIDE
1168 ;-----------------------------------------------------------------------------
1169 ; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
1170 ; uint8_t *pix2, int i_stride, int scores[3] )
1171 ;-----------------------------------------------------------------------------
1173 cglobal pixel_sad_x%1_%2x%3_%4, 2+%1,2+%1,9
1176 movsxd r %+ i, r %+ i %+ d
1178 SAD_X%1_2x%2P_SSE2 1
1180 SAD_X%1_2x%2P_SSE2 0
1185 %macro SAD_X_SSE2_MISALIGN 4
1186 cglobal pixel_sad_x%1_%2x%3_%4_misalign, 2+%1,2+%1,9
1189 movsxd r %+ i, r %+ i %+ d
1191 SAD_X%1_2x%2P_SSE2_MISALIGN 1
1193 SAD_X%1_2x%2P_SSE2_MISALIGN 0
1198 SAD_X_SSE2 3, 16, 16, sse2
1199 SAD_X_SSE2 3, 16, 8, sse2
1200 SAD_X_SSE2 3, 8, 16, sse2
1201 SAD_X_SSE2 3, 8, 8, sse2
1202 SAD_X_SSE2 3, 8, 4, sse2
1203 SAD_X_SSE2 4, 16, 16, sse2
1204 SAD_X_SSE2 4, 16, 8, sse2
1205 SAD_X_SSE2 4, 8, 16, sse2
1206 SAD_X_SSE2 4, 8, 8, sse2
1207 SAD_X_SSE2 4, 8, 4, sse2
1209 SAD_X_SSE2_MISALIGN 3, 16, 16, sse2
1210 SAD_X_SSE2_MISALIGN 3, 16, 8, sse2
1211 SAD_X_SSE2_MISALIGN 4, 16, 16, sse2
1212 SAD_X_SSE2_MISALIGN 4, 16, 8, sse2
1214 %define movdqu lddqu
1215 SAD_X_SSE2 3, 16, 16, sse3
1216 SAD_X_SSE2 3, 16, 8, sse3
1217 SAD_X_SSE2 4, 16, 16, sse3
1218 SAD_X_SSE2 4, 16, 8, sse3
1223 ;=============================================================================
1224 ; SAD cacheline split
1225 ;=============================================================================
1227 ; Core2 (Conroe) can load unaligned data just as quickly as aligned data...
1228 ; unless the unaligned data spans the border between 2 cachelines, in which
1229 ; case it's really slow. The exact numbers may differ, but all Intel cpus prior
1230 ; to Nehalem have a large penalty for cacheline splits.
1231 ; (8-byte alignment exactly half way between two cachelines is ok though.)
1232 ; LDDQU was supposed to fix this, but it only works on Pentium 4.
1233 ; So in the split case we load aligned data and explicitly perform the
1234 ; alignment between registers. Like on archs that have only aligned loads,
1235 ; except complicated by the fact that PALIGNR takes only an immediate, not
1236 ; a variable alignment.
1237 ; It is also possible to hoist the realignment to the macroblock level (keep
1238 ; 2 copies of the reference frame, offset by 32 bytes), but the extra memory
1239 ; needed for that method makes it often slower.
1241 ; sad 16x16 costs on Core2:
1242 ; good offsets: 49 cycles (50/64 of all mvs)
1243 ; cacheline split: 234 cycles (14/64 of all mvs. ammortized: +40 cycles)
1244 ; page split: 3600 cycles (14/4096 of all mvs. ammortized: +11.5 cycles)
1245 ; cache or page split with palignr: 57 cycles (ammortized: +2 cycles)
1247 ; computed jump assumes this loop is exactly 80 bytes
1248 %macro SAD16_CACHELINE_LOOP_SSE2 1 ; alignment
1250 sad_w16_align%1_sse2:
1251 movdqa xmm1, [r2+16]
1252 movdqa xmm2, [r2+r3+16]
1254 movdqa xmm4, [r2+r3]
1262 psadbw xmm2, [r0+r1]
1268 jg sad_w16_align%1_sse2
1272 ; computed jump assumes this loop is exactly 64 bytes
1273 %macro SAD16_CACHELINE_LOOP_SSSE3 1 ; alignment
1275 sad_w16_align%1_ssse3:
1276 movdqa xmm1, [r2+16]
1277 movdqa xmm2, [r2+r3+16]
1278 palignr xmm1, [r2], %1
1279 palignr xmm2, [r2+r3], %1
1281 psadbw xmm2, [r0+r1]
1287 jg sad_w16_align%1_ssse3
1291 %macro SAD16_CACHELINE_FUNC 2 ; cpu, height
1292 cglobal pixel_sad_16x%2_cache64_%1
1296 jle pixel_sad_16x%2_sse2
1301 shl r4d, 6 ; code size = 64
1304 shl r4d, 4 ; code size = 80
1306 %define sad_w16_addr (sad_w16_align1_%1 + (sad_w16_align1_%1 - sad_w16_align2_%1))
1308 lea r5, [sad_w16_addr]
1311 lea r5, [sad_w16_addr + r4]
1323 %macro SAD_CACHELINE_START_MMX2 4 ; width, height, iterations, cacheline
1325 and eax, 0x17|%1|(%4>>1)
1326 cmp eax, 0x10|%1|(%4>>1)
1327 jle pixel_sad_%1x%2_mmxext
1339 %macro SAD16_CACHELINE_FUNC_MMX2 2 ; height, cacheline
1340 cglobal pixel_sad_16x%1_cache%2_mmxext
1341 SAD_CACHELINE_START_MMX2 16, %1, %1, %2
1365 %macro SAD8_CACHELINE_FUNC_MMX2 2 ; height, cacheline
1366 cglobal pixel_sad_8x%1_cache%2_mmxext
1367 SAD_CACHELINE_START_MMX2 8, %1, %1/2, %2
1391 ; sad_x3/x4_cache64: check each mv.
1392 ; if they're all within a cacheline, use normal sad_x3/x4.
1393 ; otherwise, send them individually to sad_cache64.
1394 %macro CHECK_SPLIT 3 ; pix, width, cacheline
1396 and eax, 0x17|%2|(%3>>1)
1397 cmp eax, 0x10|%2|(%3>>1)
1401 %macro SADX3_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
1402 cglobal pixel_sad_x3_%1x%2_cache%3_%6
1403 CHECK_SPLIT r1m, %1, %3
1404 CHECK_SPLIT r2m, %1, %3
1405 CHECK_SPLIT r3m, %1, %3
1406 jmp pixel_sad_x3_%1x%2_%4
1421 call pixel_sad_%1x%2_cache%3_%5
1429 call pixel_sad_%1x%2_cache%3_%5
1437 call pixel_sad_%1x%2_cache%3_%5
1450 call pixel_sad_%1x%2_cache%3_%5
1454 call pixel_sad_%1x%2_cache%3_%5
1458 call pixel_sad_%1x%2_cache%3_%5
1466 %macro SADX4_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
1467 cglobal pixel_sad_x4_%1x%2_cache%3_%6
1468 CHECK_SPLIT r1m, %1, %3
1469 CHECK_SPLIT r2m, %1, %3
1470 CHECK_SPLIT r3m, %1, %3
1471 CHECK_SPLIT r4m, %1, %3
1472 jmp pixel_sad_x4_%1x%2_%4
1487 call pixel_sad_%1x%2_cache%3_%5
1495 call pixel_sad_%1x%2_cache%3_%5
1503 call pixel_sad_%1x%2_cache%3_%5
1511 call pixel_sad_%1x%2_cache%3_%5
1524 call pixel_sad_%1x%2_cache%3_%5
1528 call pixel_sad_%1x%2_cache%3_%5
1532 call pixel_sad_%1x%2_cache%3_%5
1536 call pixel_sad_%1x%2_cache%3_%5
1544 %macro SADX34_CACHELINE_FUNC 1+
1545 SADX3_CACHELINE_FUNC %1
1546 SADX4_CACHELINE_FUNC %1
1550 ; instantiate the aligned sads
1553 SAD16_CACHELINE_FUNC_MMX2 8, 32
1554 SAD16_CACHELINE_FUNC_MMX2 16, 32
1555 SAD8_CACHELINE_FUNC_MMX2 4, 32
1556 SAD8_CACHELINE_FUNC_MMX2 8, 32
1557 SAD8_CACHELINE_FUNC_MMX2 16, 32
1558 SAD16_CACHELINE_FUNC_MMX2 8, 64
1559 SAD16_CACHELINE_FUNC_MMX2 16, 64
1560 %endif ; !ARCH_X86_64
1561 SAD8_CACHELINE_FUNC_MMX2 4, 64
1562 SAD8_CACHELINE_FUNC_MMX2 8, 64
1563 SAD8_CACHELINE_FUNC_MMX2 16, 64
1566 SADX34_CACHELINE_FUNC 16, 16, 32, mmxext, mmxext, mmxext
1567 SADX34_CACHELINE_FUNC 16, 8, 32, mmxext, mmxext, mmxext
1568 SADX34_CACHELINE_FUNC 8, 16, 32, mmxext, mmxext, mmxext
1569 SADX34_CACHELINE_FUNC 8, 8, 32, mmxext, mmxext, mmxext
1570 SADX34_CACHELINE_FUNC 16, 16, 64, mmxext, mmxext, mmxext
1571 SADX34_CACHELINE_FUNC 16, 8, 64, mmxext, mmxext, mmxext
1572 %endif ; !ARCH_X86_64
1573 SADX34_CACHELINE_FUNC 8, 16, 64, mmxext, mmxext, mmxext
1574 SADX34_CACHELINE_FUNC 8, 8, 64, mmxext, mmxext, mmxext
1577 SAD16_CACHELINE_FUNC sse2, 8
1578 SAD16_CACHELINE_FUNC sse2, 16
1581 SAD16_CACHELINE_LOOP_SSE2 i
1584 SADX34_CACHELINE_FUNC 16, 16, 64, sse2, sse2, sse2
1585 SADX34_CACHELINE_FUNC 16, 8, 64, sse2, sse2, sse2
1586 %endif ; !ARCH_X86_64
1587 SADX34_CACHELINE_FUNC 8, 16, 64, sse2, mmxext, sse2
1589 SAD16_CACHELINE_FUNC ssse3, 8
1590 SAD16_CACHELINE_FUNC ssse3, 16
1593 SAD16_CACHELINE_LOOP_SSSE3 i
1596 SADX34_CACHELINE_FUNC 16, 16, 64, sse2, ssse3, ssse3
1597 SADX34_CACHELINE_FUNC 16, 8, 64, sse2, ssse3, ssse3