1 ;*****************************************************************************
2 ;* sad-a.asm: x86 sad functions
3 ;*****************************************************************************
4 ;* Copyright (C) 2003-2011 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Fiona Glaser <fiona@x264.com>
8 ;* Laurent Aimar <fenrir@via.ecp.fr>
9 ;* Alex Izvorski <aizvorksi@gmail.com>
11 ;* This program is free software; you can redistribute it and/or modify
12 ;* it under the terms of the GNU General Public License as published by
13 ;* the Free Software Foundation; either version 2 of the License, or
14 ;* (at your option) any later version.
16 ;* This program is distributed in the hope that it will be useful,
17 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;* GNU General Public License for more details.
21 ;* You should have received a copy of the GNU General Public License
22 ;* along with this program; if not, write to the Free Software
23 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
25 ;* This program is also available under a commercial proprietary license.
26 ;* For more information, contact us at licensing@x264.com.
27 ;*****************************************************************************
30 %include "x86util.asm"
34 h4x4_pred_shuf: db 3,3,3,3,7,7,7,7,11,11,11,11,15,15,15,15
35 h4x4_pred_shuf2: db 3,7,11,15,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
36 h8x8_pred_shuf: times 8 db 1
52 ;=============================================================================
54 ;=============================================================================
56 %macro SAD_INC_2x16P 0
87 punpckldq mm1, [r0+r1]
88 punpckldq mm2, [r2+r3]
95 ;-----------------------------------------------------------------------------
96 ; int pixel_sad_16x16( uint8_t *, int, uint8_t *, int )
97 ;-----------------------------------------------------------------------------
99 cglobal pixel_sad_%1x%2_mmx2, 4,4
118 ;=============================================================================
120 ;=============================================================================
122 %macro SAD_END_SSE2 0
130 ;-----------------------------------------------------------------------------
131 ; int pixel_sad_16x16( uint8_t *, int, uint8_t *, int )
132 ;-----------------------------------------------------------------------------
133 cglobal pixel_sad_16x16, 4,4,8
197 ;-----------------------------------------------------------------------------
198 ; int pixel_sad_16x8( uint8_t *, int, uint8_t *, int )
199 ;-----------------------------------------------------------------------------
200 cglobal pixel_sad_16x8, 4,4
239 INIT_XMM sse2, aligned
242 %macro SAD_INC_4x8P_SSE 1
266 ;Even on Nehalem, no sizes other than 8x16 benefit from this method.
267 cglobal pixel_sad_8x16_sse2, 4,4
275 ;-----------------------------------------------------------------------------
276 ; void pixel_vsad( pixel *src, int stride );
277 ;-----------------------------------------------------------------------------
281 cglobal pixel_vsad_mmx2, 3,3
316 cglobal pixel_vsad_sse2, 3,3
340 ;-----------------------------------------------------------------------------
341 ; void intra_sad_x3_4x4( uint8_t *fenc, uint8_t *fdec, int res[3] );
342 ;-----------------------------------------------------------------------------
344 cglobal intra_sad_x3_4x4_mmx2, 3,3
346 movd mm0, [r1-FDEC_STRIDE]
347 movd mm1, [r0+FENC_STRIDE*0]
348 movd mm2, [r0+FENC_STRIDE*2]
350 punpckldq mm1, [r0+FENC_STRIDE*1]
351 punpckldq mm2, [r0+FENC_STRIDE*3]
357 movd [r2], mm0 ;V prediction cost
358 movd mm3, [r1+FDEC_STRIDE*0-4]
359 movd mm0, [r1+FDEC_STRIDE*1-4]
360 movd mm4, [r1+FDEC_STRIDE*2-4]
361 movd mm5, [r1+FDEC_STRIDE*3-4]
375 pshufw mm5, mm5, 0 ;DC prediction
383 movd [r2+8], mm5 ;DC prediction cost
384 movd [r2+4], mm1 ;H prediction cost
387 %macro INTRA_SADx3_4x4 0
388 cglobal intra_sad_x3_4x4, 3,3
389 movd xmm4, [r1+FDEC_STRIDE*0-4]
390 pinsrd xmm4, [r1+FDEC_STRIDE*1-4], 1
391 pinsrd xmm4, [r1+FDEC_STRIDE*2-4], 2
392 pinsrd xmm4, [r1+FDEC_STRIDE*3-4], 3
393 movd xmm2, [r1-FDEC_STRIDE]
395 pshufb xmm5, xmm4, [h4x4_pred_shuf] ; EEEEFFFFGGGGHHHH
396 pshufb xmm4, [h4x4_pred_shuf2] ; EFGH
397 pshufd xmm0, xmm2, 0 ; ABCDABCDABCDABCD
398 punpckldq xmm2, xmm4 ; ABCDEFGH
400 movd xmm1, [r0+FENC_STRIDE*0]
401 pinsrd xmm1, [r0+FENC_STRIDE*1], 1
402 pinsrd xmm1, [r0+FENC_STRIDE*2], 2
403 pinsrd xmm1, [r0+FENC_STRIDE*3], 3
408 pshufb xmm2, xmm3 ; DC prediction
409 punpckhqdq xmm3, xmm0, xmm5
410 punpcklqdq xmm0, xmm5
416 movq [r2], xmm0 ; V/H prediction costs
417 movd [r2+8], xmm2 ; DC prediction cost
419 %endmacro ; INTRA_SADx3_4x4
426 ;-----------------------------------------------------------------------------
427 ; void intra_sad_x3_8x8( uint8_t *fenc, uint8_t edge[36], int res[3]);
428 ;-----------------------------------------------------------------------------
439 %macro INTRA_SAD_HVDC_ITER 2
440 movq m5, [r0+FENC_STRIDE*%1]
465 cglobal intra_sad_x3_8x8_mmx2, 3,3
468 movq m6, [r1+16] ;V prediction
476 pshufw m0, m0, q0000 ;DC prediction
478 INTRA_SAD_HVDC_ITER 0, q3333
479 INTRA_SAD_HVDC_ITER 1, q2222
480 INTRA_SAD_HVDC_ITER 2, q1111
481 INTRA_SAD_HVDC_ITER 3, q0000
484 INTRA_SAD_HVDC_ITER 4, q3333
485 INTRA_SAD_HVDC_ITER 5, q2222
486 INTRA_SAD_HVDC_ITER 6, q1111
487 INTRA_SAD_HVDC_ITER 7, q0000
493 %macro INTRA_SADx3_8x8 0
494 cglobal intra_sad_x3_8x8, 3,4,9
496 lea r11, [h8x8_pred_shuf]
499 %define shuf h8x8_pred_shuf
501 movq m0, [r1+7] ; left pixels
502 movq m1, [r1+16] ; top pixels
508 pxor m3, m3 ; V score accumulator
511 punpcklqdq m1, m1 ; V prediction
512 pshufb m2, m3 ; DC prediction
513 pxor m4, m4 ; H score accumulator
514 pxor m5, m5 ; DC score accumulator
517 movq m6, [r0+FENC_STRIDE*0]
518 movhps m6, [r0+FENC_STRIDE*1]
519 pshufb m7, m0, [shuf+r3*8] ; H prediction
535 add r0, FENC_STRIDE*2
549 %endmacro ; INTRA_SADx3_8x8
556 ;-----------------------------------------------------------------------------
557 ; void intra_sad_x3_8x8c( uint8_t *fenc, uint8_t *fdec, int res[3] );
558 ;-----------------------------------------------------------------------------
560 %macro INTRA_SAD_HV_ITER 1
562 movd m1, [r1 + FDEC_STRIDE*(%1-4) - 4]
563 movd m3, [r1 + FDEC_STRIDE*(%1-3) - 4]
567 movq m1, [r1 + FDEC_STRIDE*(%1-4) - 8]
568 movq m3, [r1 + FDEC_STRIDE*(%1-3) - 8]
574 movq m4, [r0 + FENC_STRIDE*(%1+0)]
575 movq m5, [r0 + FENC_STRIDE*(%1+1)]
591 %macro INTRA_SAD_8x8C 0
592 cglobal intra_sad_x3_8x8c, 3,3
593 movq m6, [r1 - FDEC_STRIDE]
594 add r1, FDEC_STRIDE*4
605 movq m2, [r1 + FDEC_STRIDE*-4 - 8]
606 movq m4, [r1 + FDEC_STRIDE*-2 - 8]
607 movq m3, [r1 + FDEC_STRIDE* 0 - 8]
608 movq m5, [r1 + FDEC_STRIDE* 2 - 8]
609 punpckhbw m2, [r1 + FDEC_STRIDE*-3 - 8]
610 punpckhbw m4, [r1 + FDEC_STRIDE*-1 - 8]
611 punpckhbw m3, [r1 + FDEC_STRIDE* 1 - 8]
612 punpckhbw m5, [r1 + FDEC_STRIDE* 3 - 8]
627 punpckldq m0, m2 ;s0 s1 s2 s3
628 pshufw m3, m0, q3312 ;s2,s1,s3,s3
629 pshufw m0, m0, q1310 ;s0,s1,s3,s1
632 pavgw m0, m7 ; s0+s2, s1, s3, s1+s3
635 pshufb xmm0, [pb_shuf8x8c]
636 movq xmm1, [r0+FENC_STRIDE*0]
637 movq xmm2, [r0+FENC_STRIDE*1]
638 movq xmm3, [r0+FENC_STRIDE*2]
639 movq xmm4, [r0+FENC_STRIDE*3]
640 movhps xmm1, [r0+FENC_STRIDE*4]
641 movhps xmm2, [r0+FENC_STRIDE*5]
642 movhps xmm3, [r0+FENC_STRIDE*6]
643 movhps xmm4, [r0+FENC_STRIDE*7]
658 punpcklbw m0, m0 ; 4x dc0 4x dc1
659 punpckhbw m1, m1 ; 4x dc2 4x dc3
660 movq m2, [r0+FENC_STRIDE*0]
661 movq m3, [r0+FENC_STRIDE*1]
662 movq m4, [r0+FENC_STRIDE*2]
663 movq m5, [r0+FENC_STRIDE*3]
664 movq m6, [r0+FENC_STRIDE*4]
665 movq m7, [r0+FENC_STRIDE*5]
670 movq m0, [r0+FENC_STRIDE*6]
674 psadbw m1, [r0+FENC_STRIDE*7]
693 ;-----------------------------------------------------------------------------
694 ; void intra_sad_x3_16x16( uint8_t *fenc, uint8_t *fdec, int res[3] );
695 ;-----------------------------------------------------------------------------
697 ;xmm7: DC prediction xmm6: H prediction xmm5: V prediction
698 ;xmm4: DC pred score xmm3: H pred score xmm2: V pred score
700 cglobal intra_sad_x3_16x16, 3,5,8
703 psadbw mm0, [r1-FDEC_STRIDE+0]
704 psadbw mm1, [r1-FDEC_STRIDE+8]
712 movzx r4d, byte [r1-1+FDEC_STRIDE*(x&3)]
713 %if (x&3)==3 && x!=15
714 add r1, FDEC_STRIDE*4
719 sub r1, FDEC_STRIDE*12
724 mova m5, [r1-FDEC_STRIDE]
728 mova m1, [r1-FDEC_STRIDE+8]
734 mov r3d, 15*FENC_STRIDE
736 SPLATB_LOAD m6, r1+r3*2-1, m1
759 add r3d, -FENC_STRIDE
786 ;=============================================================================
788 ;=============================================================================
790 %macro SAD_X3_START_1x8P 0
813 %macro SAD_X3_START_2x4P 3
818 punpckldq mm3, [r0+FENC_STRIDE]
819 punpckldq %1, [r1+r4]
820 punpckldq %2, [r2+r4]
821 punpckldq %3, [r3+r4]
827 %macro SAD_X3_2x16P 1
834 SAD_X3_1x8P FENC_STRIDE, r4
835 SAD_X3_1x8P FENC_STRIDE+8, r4+8
836 add r0, 2*FENC_STRIDE
848 SAD_X3_1x8P FENC_STRIDE, r4
849 add r0, 2*FENC_STRIDE
857 SAD_X3_START_2x4P mm0, mm1, mm2
859 SAD_X3_START_2x4P mm4, mm5, mm6
864 add r0, 2*FENC_STRIDE
870 %macro SAD_X4_START_1x8P 0
897 %macro SAD_X4_START_2x4P 0
903 punpckldq mm7, [r0+FENC_STRIDE]
904 punpckldq mm0, [r1+r5]
905 punpckldq mm1, [r2+r5]
906 punpckldq mm2, [r3+r5]
907 punpckldq mm3, [r4+r5]
914 %macro SAD_X4_INC_2x4P 0
918 punpckldq mm7, [r0+FENC_STRIDE]
919 punpckldq mm4, [r1+r5]
920 punpckldq mm5, [r2+r5]
927 punpckldq mm4, [r3+r5]
928 punpckldq mm5, [r4+r5]
935 %macro SAD_X4_2x16P 1
942 SAD_X4_1x8P FENC_STRIDE, r5
943 SAD_X4_1x8P FENC_STRIDE+8, r5+8
944 add r0, 2*FENC_STRIDE
957 SAD_X4_1x8P FENC_STRIDE, r5
958 add r0, 2*FENC_STRIDE
971 add r0, 2*FENC_STRIDE
1001 ;-----------------------------------------------------------------------------
1002 ; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
1003 ; uint8_t *pix2, int i_stride, int scores[3] )
1004 ;-----------------------------------------------------------------------------
1006 cglobal pixel_sad_x%1_%2x%3_mmx2, %1+2, %1+2
1009 movsxd r %+ i, r %+ i %+ d
1036 ;=============================================================================
1038 ;=============================================================================
1040 %macro SAD_X3_START_1x16P_SSE2 0
1041 %if cpuflag(misalign)
1059 %macro SAD_X3_1x16P_SSE2 2
1060 %if cpuflag(misalign)
1066 psadbw xmm3, [r3+%2]
1084 %macro SAD_X3_2x16P_SSE2 1
1086 SAD_X3_START_1x16P_SSE2
1088 SAD_X3_1x16P_SSE2 0, 0
1090 SAD_X3_1x16P_SSE2 FENC_STRIDE, r4
1091 add r0, 2*FENC_STRIDE
1097 %macro SAD_X3_START_2x8P_SSE2 0
1102 movhps xmm7, [r0+FENC_STRIDE]
1103 movhps xmm0, [r1+r4]
1104 movhps xmm1, [r2+r4]
1105 movhps xmm2, [r3+r4]
1111 %macro SAD_X3_2x8P_SSE2 0
1116 movhps xmm7, [r0+FENC_STRIDE]
1117 movhps xmm3, [r1+r4]
1118 movhps xmm4, [r2+r4]
1119 movhps xmm5, [r3+r4]
1128 %macro SAD_X4_START_2x8P_SSE2 0
1134 movhps xmm7, [r0+FENC_STRIDE]
1135 movhps xmm0, [r1+r5]
1136 movhps xmm1, [r2+r5]
1137 movhps xmm2, [r3+r5]
1138 movhps xmm3, [r4+r5]
1145 %macro SAD_X4_2x8P_SSE2 0
1152 movhps xmm7, [r0+FENC_STRIDE]
1153 movhps xmm4, [r1+r5]
1154 movhps xmm5, [r2+r5]
1155 movhps xmm6, [r3+r5]
1156 movhps xmm8, [r4+r5]
1166 movhps xmm7, [r0+FENC_STRIDE]
1167 movhps xmm4, [r1+r5]
1168 movhps xmm5, [r2+r5]
1175 movhps xmm6, [r3+r5]
1176 movhps xmm4, [r4+r5]
1184 %macro SAD_X4_START_1x16P_SSE2 0
1185 %if cpuflag(misalign)
1207 %macro SAD_X4_1x16P_SSE2 2
1208 %if cpuflag(misalign)
1216 psadbw xmm7, [r4+%2]
1250 %macro SAD_X4_2x16P_SSE2 1
1252 SAD_X4_START_1x16P_SSE2
1254 SAD_X4_1x16P_SSE2 0, 0
1256 SAD_X4_1x16P_SSE2 FENC_STRIDE, r5
1257 add r0, 2*FENC_STRIDE
1264 %macro SAD_X3_2x8P_SSE2 1
1266 SAD_X3_START_2x8P_SSE2
1270 add r0, 2*FENC_STRIDE
1276 %macro SAD_X4_2x8P_SSE2 1
1278 SAD_X4_START_2x8P_SSE2
1282 add r0, 2*FENC_STRIDE
1289 %macro SAD_X3_END_SSE2 0
1309 %macro SAD_X4_END_SSE2 0
1324 ;-----------------------------------------------------------------------------
1325 ; void pixel_sad_x3_16x16( uint8_t *fenc, uint8_t *pix0, uint8_t *pix1,
1326 ; uint8_t *pix2, int i_stride, int scores[3] )
1327 ;-----------------------------------------------------------------------------
1329 cglobal pixel_sad_x%1_%2x%3, 2+%1,2+%1,9
1332 movsxd r %+ i, r %+ i %+ d
1334 SAD_X%1_2x%2P_SSE2 1
1336 SAD_X%1_2x%2P_SSE2 0
1342 SAD_X_SSE2 3, 16, 16
1347 SAD_X_SSE2 4, 16, 16
1353 INIT_XMM sse2, misalign
1354 SAD_X_SSE2 3, 16, 16
1356 SAD_X_SSE2 4, 16, 16
1360 SAD_X_SSE2 3, 16, 16
1362 SAD_X_SSE2 4, 16, 16
1367 ;=============================================================================
1368 ; SAD cacheline split
1369 ;=============================================================================
1371 ; Core2 (Conroe) can load unaligned data just as quickly as aligned data...
1372 ; unless the unaligned data spans the border between 2 cachelines, in which
1373 ; case it's really slow. The exact numbers may differ, but all Intel cpus prior
1374 ; to Nehalem have a large penalty for cacheline splits.
1375 ; (8-byte alignment exactly half way between two cachelines is ok though.)
1376 ; LDDQU was supposed to fix this, but it only works on Pentium 4.
1377 ; So in the split case we load aligned data and explicitly perform the
1378 ; alignment between registers. Like on archs that have only aligned loads,
1379 ; except complicated by the fact that PALIGNR takes only an immediate, not
1380 ; a variable alignment.
1381 ; It is also possible to hoist the realignment to the macroblock level (keep
1382 ; 2 copies of the reference frame, offset by 32 bytes), but the extra memory
1383 ; needed for that method makes it often slower.
1385 ; sad 16x16 costs on Core2:
1386 ; good offsets: 49 cycles (50/64 of all mvs)
1387 ; cacheline split: 234 cycles (14/64 of all mvs. ammortized: +40 cycles)
1388 ; page split: 3600 cycles (14/4096 of all mvs. ammortized: +11.5 cycles)
1389 ; cache or page split with palignr: 57 cycles (ammortized: +2 cycles)
1391 ; computed jump assumes this loop is exactly 80 bytes
1392 %macro SAD16_CACHELINE_LOOP_SSE2 1 ; alignment
1394 sad_w16_align%1_sse2:
1395 movdqa xmm1, [r2+16]
1396 movdqa xmm2, [r2+r3+16]
1398 movdqa xmm4, [r2+r3]
1406 psadbw xmm2, [r0+r1]
1412 jg sad_w16_align%1_sse2
1416 ; computed jump assumes this loop is exactly 64 bytes
1417 %macro SAD16_CACHELINE_LOOP_SSSE3 1 ; alignment
1419 sad_w16_align%1_ssse3:
1420 movdqa xmm1, [r2+16]
1421 movdqa xmm2, [r2+r3+16]
1422 palignr xmm1, [r2], %1
1423 palignr xmm2, [r2+r3], %1
1425 psadbw xmm2, [r0+r1]
1431 jg sad_w16_align%1_ssse3
1435 %macro SAD16_CACHELINE_FUNC 2 ; cpu, height
1436 cglobal pixel_sad_16x%2_cache64_%1
1440 jle pixel_sad_16x%2_sse2
1445 shl r4d, 6 ; code size = 64
1448 shl r4d, 4 ; code size = 80
1450 %define sad_w16_addr (sad_w16_align1_%1 + (sad_w16_align1_%1 - sad_w16_align2_%1))
1452 lea r5, [sad_w16_addr]
1455 lea r5, [sad_w16_addr + r4]
1467 %macro SAD_CACHELINE_START_MMX2 4 ; width, height, iterations, cacheline
1469 and eax, 0x17|%1|(%4>>1)
1470 cmp eax, 0x10|%1|(%4>>1)
1471 jle pixel_sad_%1x%2_mmx2
1483 %macro SAD16_CACHELINE_FUNC_MMX2 2 ; height, cacheline
1484 cglobal pixel_sad_16x%1_cache%2_mmx2
1485 SAD_CACHELINE_START_MMX2 16, %1, %1, %2
1509 %macro SAD8_CACHELINE_FUNC_MMX2 2 ; height, cacheline
1510 cglobal pixel_sad_8x%1_cache%2_mmx2
1511 SAD_CACHELINE_START_MMX2 8, %1, %1/2, %2
1535 ; sad_x3/x4_cache64: check each mv.
1536 ; if they're all within a cacheline, use normal sad_x3/x4.
1537 ; otherwise, send them individually to sad_cache64.
1538 %macro CHECK_SPLIT 3 ; pix, width, cacheline
1540 and eax, 0x17|%2|(%3>>1)
1541 cmp eax, 0x10|%2|(%3>>1)
1545 %macro SADX3_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
1546 cglobal pixel_sad_x3_%1x%2_cache%3_%6
1547 CHECK_SPLIT r1m, %1, %3
1548 CHECK_SPLIT r2m, %1, %3
1549 CHECK_SPLIT r3m, %1, %3
1550 jmp pixel_sad_x3_%1x%2_%4
1565 call pixel_sad_%1x%2_cache%3_%5
1573 call pixel_sad_%1x%2_cache%3_%5
1581 call pixel_sad_%1x%2_cache%3_%5
1594 call pixel_sad_%1x%2_cache%3_%5
1598 call pixel_sad_%1x%2_cache%3_%5
1602 call pixel_sad_%1x%2_cache%3_%5
1610 %macro SADX4_CACHELINE_FUNC 6 ; width, height, cacheline, normal_ver, split_ver, name
1611 cglobal pixel_sad_x4_%1x%2_cache%3_%6
1612 CHECK_SPLIT r1m, %1, %3
1613 CHECK_SPLIT r2m, %1, %3
1614 CHECK_SPLIT r3m, %1, %3
1615 CHECK_SPLIT r4m, %1, %3
1616 jmp pixel_sad_x4_%1x%2_%4
1631 call pixel_sad_%1x%2_cache%3_%5
1639 call pixel_sad_%1x%2_cache%3_%5
1647 call pixel_sad_%1x%2_cache%3_%5
1655 call pixel_sad_%1x%2_cache%3_%5
1668 call pixel_sad_%1x%2_cache%3_%5
1672 call pixel_sad_%1x%2_cache%3_%5
1676 call pixel_sad_%1x%2_cache%3_%5
1680 call pixel_sad_%1x%2_cache%3_%5
1688 %macro SADX34_CACHELINE_FUNC 1+
1689 SADX3_CACHELINE_FUNC %1
1690 SADX4_CACHELINE_FUNC %1
1694 ; instantiate the aligned sads
1698 SAD16_CACHELINE_FUNC_MMX2 8, 32
1699 SAD16_CACHELINE_FUNC_MMX2 16, 32
1700 SAD8_CACHELINE_FUNC_MMX2 4, 32
1701 SAD8_CACHELINE_FUNC_MMX2 8, 32
1702 SAD8_CACHELINE_FUNC_MMX2 16, 32
1703 SAD16_CACHELINE_FUNC_MMX2 8, 64
1704 SAD16_CACHELINE_FUNC_MMX2 16, 64
1705 %endif ; !ARCH_X86_64
1706 SAD8_CACHELINE_FUNC_MMX2 4, 64
1707 SAD8_CACHELINE_FUNC_MMX2 8, 64
1708 SAD8_CACHELINE_FUNC_MMX2 16, 64
1711 SADX34_CACHELINE_FUNC 16, 16, 32, mmx2, mmx2, mmx2
1712 SADX34_CACHELINE_FUNC 16, 8, 32, mmx2, mmx2, mmx2
1713 SADX34_CACHELINE_FUNC 8, 16, 32, mmx2, mmx2, mmx2
1714 SADX34_CACHELINE_FUNC 8, 8, 32, mmx2, mmx2, mmx2
1715 SADX34_CACHELINE_FUNC 16, 16, 64, mmx2, mmx2, mmx2
1716 SADX34_CACHELINE_FUNC 16, 8, 64, mmx2, mmx2, mmx2
1717 %endif ; !ARCH_X86_64
1718 SADX34_CACHELINE_FUNC 8, 16, 64, mmx2, mmx2, mmx2
1719 SADX34_CACHELINE_FUNC 8, 8, 64, mmx2, mmx2, mmx2
1722 SAD16_CACHELINE_FUNC sse2, 8
1723 SAD16_CACHELINE_FUNC sse2, 16
1726 SAD16_CACHELINE_LOOP_SSE2 i
1729 SADX34_CACHELINE_FUNC 16, 16, 64, sse2, sse2, sse2
1730 SADX34_CACHELINE_FUNC 16, 8, 64, sse2, sse2, sse2
1731 %endif ; !ARCH_X86_64
1732 SADX34_CACHELINE_FUNC 8, 16, 64, sse2, mmx2, sse2
1734 SAD16_CACHELINE_FUNC ssse3, 8
1735 SAD16_CACHELINE_FUNC ssse3, 16
1738 SAD16_CACHELINE_LOOP_SSSE3 i
1741 SADX34_CACHELINE_FUNC 16, 16, 64, sse2, ssse3, ssse3
1742 SADX34_CACHELINE_FUNC 16, 8, 64, sse2, ssse3, ssse3