1 ;*****************************************************************************
2 ;* x86inc.asm: x264asm abstraction layer
3 ;*****************************************************************************
4 ;* Copyright (C) 2005-2013 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Anton Mitrofanov <BugMaster@narod.ru>
8 ;* Fiona Glaser <fiona@x264.com>
9 ;* Henrik Gramner <hengar-6@student.ltu.se>
11 ;* Permission to use, copy, modify, and/or distribute this software for any
12 ;* purpose with or without fee is hereby granted, provided that the above
13 ;* copyright notice and this permission notice appear in all copies.
15 ;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 ;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 ;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 ;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 ;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 ;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 ;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 ;*****************************************************************************
24 ; This is a header file for the x264ASM assembly language, which uses
25 ; NASM/YASM syntax combined with a large number of macros to provide easy
26 ; abstraction between different calling conventions (x86_32, win64, linux64).
27 ; It also has various other useful features to simplify writing the kind of
28 ; DSP functions that are most often used in x264.
30 ; Unlike the rest of x264, this file is available under an ISC license, as it
31 ; has significant usefulness outside of x264 and we want it to be available
32 ; to the largest audience possible. Of course, if you modify it for your own
33 ; purposes to add a new feature, we strongly encourage contributing a patch
34 ; as this feature might be useful for others as well. Send patches or ideas
35 ; to x264-devel@videolan.org .
38 %define program_name x264
44 %ifidn __OUTPUT_FORMAT__,win32
46 %elifidn __OUTPUT_FORMAT__,win64
54 %define mangle(x) _ %+ x
59 ; Name of the .rodata section.
60 ; Kludge: Something on OS X fails to align .rodata even given an align attribute,
61 ; so use a different read-only section.
62 %macro SECTION_RODATA 0-1 16
63 %ifidn __OUTPUT_FORMAT__,macho64
64 SECTION .text align=%1
65 %elifidn __OUTPUT_FORMAT__,macho
66 SECTION .text align=%1
68 %elifidn __OUTPUT_FORMAT__,aout
71 SECTION .rodata align=%1
75 ; aout does not support align=
76 %macro SECTION_TEXT 0-1 16
77 %ifidn __OUTPUT_FORMAT__,aout
80 SECTION .text align=%1
86 %elif ARCH_X86_64 == 0
87 ; x86_32 doesn't require PIC.
88 ; Some distros prefer shared objects to be PIC, but nothing breaks if
89 ; the code contains a few textrels, so we'll skip that complexity.
96 ; Always use long nops (reduces 0x90 spam in disassembly on x86_32)
99 ; Macros to eliminate most code duplication between x86_32 and x86_64:
100 ; Currently this works only for leaf functions which load all their arguments
101 ; into registers at the start, and make no other use of the stack. Luckily that
102 ; covers most of x264's asm.
105 ; %1 = number of arguments. loads them from stack if needed.
106 ; %2 = number of registers used. pushes callee-saved regs if needed.
107 ; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
108 ; %4 = (optional) stack size to be allocated. If not aligned (x86-32 ICC 10.x,
109 ; MSVC or YMM), the stack will be manually aligned (to 16 or 32 bytes),
110 ; and an extra register will be allocated to hold the original stack
111 ; pointer (to not invalidate r0m etc.). To prevent the use of an extra
112 ; register as stack pointer, request a negative stack size.
113 ; %4+/%5+ = list of names to define to registers
114 ; PROLOGUE can also be invoked by adding the same options to cglobal
117 ; cglobal foo, 2,3,0, dst, src, tmp
118 ; declares a function (foo), taking two args (dst and src) and one local variable (tmp)
120 ; TODO Some functions can use some args directly from the stack. If they're the
121 ; last args then you can just not declare them, but if they're in the middle
122 ; we need more flexible macro.
125 ; Pops anything that was pushed by PROLOGUE, and returns.
128 ; Use this instead of RET if it's a branch target.
131 ; rN and rNq are the native-size register holding function argument N
132 ; rNd, rNw, rNb are dword, word, and byte size
133 ; rNh is the high 8 bits of the word size
134 ; rNm is the original location of arg N (a register or on the stack), dword
135 ; rNmp is native size
137 %macro DECLARE_REG 2-3
146 %elif ARCH_X86_64 ; memory
147 %define r%1m [rstk + stack_offset + %3]
148 %define r%1mp qword r %+ %1 %+ m
150 %define r%1m [rstk + stack_offset + %3]
151 %define r%1mp dword r %+ %1 %+ m
156 %macro DECLARE_REG_SIZE 3
172 DECLARE_REG_SIZE ax, al, ah
173 DECLARE_REG_SIZE bx, bl, bh
174 DECLARE_REG_SIZE cx, cl, ch
175 DECLARE_REG_SIZE dx, dl, dh
176 DECLARE_REG_SIZE si, sil, null
177 DECLARE_REG_SIZE di, dil, null
178 DECLARE_REG_SIZE bp, bpl, null
180 ; t# defines for when per-arch register allocation is more complex than just function arguments
182 %macro DECLARE_REG_TMP 1-*
185 CAT_XDEFINE t, %%i, r%1
191 %macro DECLARE_REG_TMP_SIZE 0-*
193 %define t%1q t%1 %+ q
194 %define t%1d t%1 %+ d
195 %define t%1w t%1 %+ w
196 %define t%1h t%1 %+ h
197 %define t%1b t%1 %+ b
202 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
213 %assign stack_offset stack_offset+gprsize
220 %assign stack_offset stack_offset-gprsize
224 %macro PUSH_IF_USED 1-*
233 %macro POP_IF_USED 1-*
242 %macro LOAD_IF_USED 1-*
245 mov r%1, r %+ %1 %+ mp
254 %assign stack_offset stack_offset+(%2)
261 %assign stack_offset stack_offset-(%2)
271 %macro movsxdifnidn 2
283 %macro DEFINE_ARGS 0-*
287 CAT_UNDEF arg_name %+ %%i, q
288 CAT_UNDEF arg_name %+ %%i, d
289 CAT_UNDEF arg_name %+ %%i, w
290 CAT_UNDEF arg_name %+ %%i, h
291 CAT_UNDEF arg_name %+ %%i, b
292 CAT_UNDEF arg_name %+ %%i, m
293 CAT_UNDEF arg_name %+ %%i, mp
294 CAT_UNDEF arg_name, %%i
299 %xdefine %%stack_offset stack_offset
300 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
303 %xdefine %1q r %+ %%i %+ q
304 %xdefine %1d r %+ %%i %+ d
305 %xdefine %1w r %+ %%i %+ w
306 %xdefine %1h r %+ %%i %+ h
307 %xdefine %1b r %+ %%i %+ b
308 %xdefine %1m r %+ %%i %+ m
309 %xdefine %1mp r %+ %%i %+ mp
310 CAT_XDEFINE arg_name, %%i, %1
314 %xdefine stack_offset %%stack_offset
315 %assign n_arg_names %0
318 %macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
321 %assign %%stack_alignment ((mmsize + 15) & ~15)
322 %assign stack_size %1
324 %assign stack_size -stack_size
327 %assign xmm_regs_used %2
329 %if mmsize <= 16 && HAVE_ALIGNED_STACK
330 %assign stack_size_padded stack_size + %%stack_alignment - gprsize - (stack_offset & (%%stack_alignment - 1))
331 %if xmm_regs_used > 6
332 %assign stack_size_padded stack_size_padded + (xmm_regs_used - 6) * 16
334 SUB rsp, stack_size_padded
336 %assign %%reg_num (regs_used - 1)
337 %xdefine rstk r %+ %%reg_num
338 ; align stack, and save original stack location directly above
339 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
340 ; stack in a single instruction (i.e. mov rsp, rstk or mov
341 ; rsp, [rsp+stack_size_padded])
343 %assign stack_size_padded stack_size
344 %if xmm_regs_used > 6
345 %assign stack_size_padded stack_size_padded + (xmm_regs_used - 6) * 16
346 %if mmsize == 32 && xmm_regs_used & 1
347 ; re-align to 32 bytes
348 %assign stack_size_padded (stack_size_padded + 16)
351 %if %1 < 0 ; need to store rsp on stack
352 sub rsp, gprsize+stack_size_padded
353 and rsp, ~(%%stack_alignment-1)
354 %xdefine rstkm [rsp+stack_size_padded]
356 %else ; can keep rsp in rstk during whole function
357 sub rsp, stack_size_padded
358 and rsp, ~(%%stack_alignment-1)
362 %if xmm_regs_used > 6
369 %macro SETUP_STACK_POINTER 1
371 %if %1 != 0 && (HAVE_ALIGNED_STACK == 0 || mmsize == 32)
373 %assign regs_used (regs_used + 1)
374 %elif ARCH_X86_64 && regs_used == num_args && num_args <= 4 + UNIX64 * 2
375 %warning "Stack pointer will overwrite register argument"
381 %macro DEFINE_ARGS_INTERNAL 3+
391 %if WIN64 ; Windows x64 ;=================================================
397 DECLARE_REG 4, R10, 40
398 DECLARE_REG 5, R11, 48
399 DECLARE_REG 6, rax, 56
400 DECLARE_REG 7, rdi, 64
401 DECLARE_REG 8, rsi, 72
402 DECLARE_REG 9, rbx, 80
403 DECLARE_REG 10, rbp, 88
404 DECLARE_REG 11, R12, 96
405 DECLARE_REG 12, R13, 104
406 DECLARE_REG 13, R14, 112
407 DECLARE_REG 14, R15, 120
409 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
412 ASSERT regs_used >= num_args
413 SETUP_STACK_POINTER %4
414 ASSERT regs_used <= 15
415 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
417 %if mmsize != 8 && stack_size == 0
420 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
421 DEFINE_ARGS_INTERNAL %0, %4, %5
424 %macro WIN64_PUSH_XMM 0
425 %assign %%i xmm_regs_used
426 %rep (xmm_regs_used-6)
428 movdqa [rsp + (%%i-6)*16 + stack_size + (~stack_offset&8)], xmm %+ %%i
432 %macro WIN64_SPILL_XMM 1
433 %assign xmm_regs_used %1
434 ASSERT xmm_regs_used <= 16
435 %if xmm_regs_used > 6
436 SUB rsp, (xmm_regs_used-6)*16+16
441 %macro WIN64_RESTORE_XMM_INTERNAL 1
442 %if xmm_regs_used > 6
443 %assign %%i xmm_regs_used
444 %rep (xmm_regs_used-6)
446 movdqa xmm %+ %%i, [%1 + (%%i-6)*16+stack_size+(~stack_offset&8)]
448 %if stack_size_padded == 0
449 add %1, (xmm_regs_used-6)*16+16
452 %if stack_size_padded > 0
453 %if stack_size > 0 && (mmsize == 32 || HAVE_ALIGNED_STACK == 0)
456 add %1, stack_size_padded
461 %macro WIN64_RESTORE_XMM 1
462 WIN64_RESTORE_XMM_INTERNAL %1
463 %assign stack_offset (stack_offset-stack_size_padded)
464 %assign xmm_regs_used 0
467 %define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
470 WIN64_RESTORE_XMM_INTERNAL rsp
471 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
478 %elif ARCH_X86_64 ; *nix x64 ;=============================================
486 DECLARE_REG 6, rax, 8
487 DECLARE_REG 7, R10, 16
488 DECLARE_REG 8, R11, 24
489 DECLARE_REG 9, rbx, 32
490 DECLARE_REG 10, rbp, 40
491 DECLARE_REG 11, R12, 48
492 DECLARE_REG 12, R13, 56
493 DECLARE_REG 13, R14, 64
494 DECLARE_REG 14, R15, 72
496 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
499 ASSERT regs_used >= num_args
500 SETUP_STACK_POINTER %4
501 ASSERT regs_used <= 15
502 PUSH_IF_USED 9, 10, 11, 12, 13, 14
504 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
505 DEFINE_ARGS_INTERNAL %0, %4, %5
508 %define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
511 %if stack_size_padded > 0
512 %if mmsize == 32 || HAVE_ALIGNED_STACK == 0
515 add rsp, stack_size_padded
518 POP_IF_USED 14, 13, 12, 11, 10, 9
525 %else ; X86_32 ;==============================================================
527 DECLARE_REG 0, eax, 4
528 DECLARE_REG 1, ecx, 8
529 DECLARE_REG 2, edx, 12
530 DECLARE_REG 3, ebx, 16
531 DECLARE_REG 4, esi, 20
532 DECLARE_REG 5, edi, 24
533 DECLARE_REG 6, ebp, 28
536 %macro DECLARE_ARG 1-*
538 %define r%1m [rstk + stack_offset + 4*%1 + 4]
539 %define r%1mp dword r%1m
544 DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
546 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
549 ASSERT regs_used >= num_args
556 SETUP_STACK_POINTER %4
557 ASSERT regs_used <= 7
558 PUSH_IF_USED 3, 4, 5, 6
560 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
561 DEFINE_ARGS_INTERNAL %0, %4, %5
564 %define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
567 %if stack_size_padded > 0
568 %if mmsize == 32 || HAVE_ALIGNED_STACK == 0
571 add rsp, stack_size_padded
574 POP_IF_USED 6, 5, 4, 3
581 %endif ;======================================================================
584 %macro WIN64_SPILL_XMM 1
586 %macro WIN64_RESTORE_XMM 1
588 %macro WIN64_PUSH_XMM 0
592 ; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
593 ; a branch or a branch target. So switch to a 2-byte form of ret in that case.
594 ; We can automatically detect "follows a branch", but not a branch target.
595 ; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
604 %define last_branch_adr $$
605 %macro AUTO_REP_RET 0
607 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
608 %elif notcpuflag(ssse3)
609 times ((last_branch_adr-$)>>31)+1 rep
614 %macro BRANCH_INSTR 0-*
619 %xdefine last_branch_adr %%branch_instr
625 BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
627 %macro TAIL_CALL 2 ; callee, is_nonadjacent
636 ;=============================================================================
637 ; arch-independent part
638 ;=============================================================================
640 %assign function_align 16
643 ; Applies any symbol mangling needed for C linkage, and sets up a define such that
644 ; subsequent uses of the function name automatically refer to the mangled version.
645 ; Appends cpuflags to the function name if cpuflags has been specified.
646 %macro cglobal 1-2+ "" ; name, [PROLOGUE args]
647 ; the "" is a workaround for nasm, which fails if SUFFIX is empty
648 ; and we call cglobal_internal with just %1 %+ SUFFIX (without %2)
649 cglobal_internal %1 %+ SUFFIX, %2
651 %macro cglobal_internal 1-2+
653 %xdefine %1 mangle(program_name %+ _ %+ %1)
654 %xdefine %1.skip_prologue %1 %+ .skip_prologue
655 CAT_XDEFINE cglobaled_, %1, 1
657 %xdefine current_function %1
658 %ifidn __OUTPUT_FORMAT__,elf
659 global %1:function hidden
665 RESET_MM_PERMUTATION ; not really needed, but makes disassembly somewhat nicer
667 %assign stack_offset 0
669 %assign stack_size_padded 0
670 %assign xmm_regs_used 0
677 %xdefine %1 mangle(program_name %+ _ %+ %1)
678 CAT_XDEFINE cglobaled_, %1, 1
682 ; like cextern, but without the prefix
683 %macro cextern_naked 1
684 %xdefine %1 mangle(%1)
685 CAT_XDEFINE cglobaled_, %1, 1
690 %xdefine %1 mangle(program_name %+ _ %+ %1)
695 ; This is needed for ELF, otherwise the GNU linker assumes the stack is
696 ; executable by default.
697 %ifidn __OUTPUT_FORMAT__,elf
698 SECTION .note.GNU-stack noalloc noexec nowrite progbits
703 %assign cpuflags_mmx (1<<0)
704 %assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
705 %assign cpuflags_3dnow (1<<2) | cpuflags_mmx
706 %assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
707 %assign cpuflags_sse (1<<4) | cpuflags_mmx2
708 %assign cpuflags_sse2 (1<<5) | cpuflags_sse
709 %assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
710 %assign cpuflags_sse3 (1<<7) | cpuflags_sse2
711 %assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
712 %assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
713 %assign cpuflags_sse42 (1<<10)| cpuflags_sse4
714 %assign cpuflags_avx (1<<11)| cpuflags_sse42
715 %assign cpuflags_xop (1<<12)| cpuflags_avx
716 %assign cpuflags_fma4 (1<<13)| cpuflags_avx
717 %assign cpuflags_avx2 (1<<14)| cpuflags_avx
718 %assign cpuflags_fma3 (1<<15)| cpuflags_avx
720 %assign cpuflags_cache32 (1<<16)
721 %assign cpuflags_cache64 (1<<17)
722 %assign cpuflags_slowctz (1<<18)
723 %assign cpuflags_lzcnt (1<<19)
724 %assign cpuflags_misalign (1<<20)
725 %assign cpuflags_aligned (1<<21) ; not a cpu feature, but a function variant
726 %assign cpuflags_atom (1<<22)
727 %assign cpuflags_bmi1 (1<<23)
728 %assign cpuflags_bmi2 (1<<24)|cpuflags_bmi1
729 %assign cpuflags_tbm (1<<25)|cpuflags_bmi1
731 %define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
732 %define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
734 ; Takes up to 2 cpuflags from the above list.
735 ; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
736 ; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
737 %macro INIT_CPUFLAGS 0-2
741 %assign cpuflags cpuflags_%1
743 %xdefine cpuname %1_%2
744 %assign cpuflags cpuflags | cpuflags_%2
746 %xdefine SUFFIX _ %+ cpuname
748 %assign avx_enabled 1
750 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
753 %define movnta movntps
760 %if ARCH_X86_64 == 0 && notcpuflag(sse2)
781 %assign avx_enabled 0
782 %define RESET_MM_PERMUTATION INIT_MMX %1
788 %define movnta movntq
791 CAT_XDEFINE m, %%i, mm %+ %%i
792 CAT_XDEFINE nmm, %%i, %%i
804 %assign avx_enabled 0
805 %define RESET_MM_PERMUTATION INIT_XMM %1
809 %define num_mmregs 16
814 %define movnta movntdq
817 CAT_XDEFINE m, %%i, xmm %+ %%i
818 CAT_XDEFINE nxmm, %%i, %%i
825 %assign avx_enabled 1
826 %define RESET_MM_PERMUTATION INIT_YMM %1
830 %define num_mmregs 16
835 %define movnta movntdq
838 CAT_XDEFINE m, %%i, ymm %+ %%i
839 CAT_XDEFINE nymm, %%i, %%i
847 ; I often want to use macros that permute their arguments. e.g. there's no
848 ; efficient way to implement butterfly or transpose or dct without swapping some
851 ; I would like to not have to manually keep track of the permutations:
852 ; If I insert a permutation in the middle of a function, it should automatically
853 ; change everything that follows. For more complex macros I may also have multiple
854 ; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
856 ; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
857 ; permutes its arguments. It's equivalent to exchanging the contents of the
858 ; registers, except that this way you exchange the register names instead, so it
859 ; doesn't cost any cycles.
861 %macro PERMUTE 2-* ; takes a list of pairs to swap
876 %macro SWAP 2-* ; swaps a single chain (sometimes more concise than pairs)
882 CAT_XDEFINE n, m%1, %1
883 CAT_XDEFINE n, m%2, %2
885 ; If we were called as "SWAP m0,m1" rather than "SWAP 0,1" infer the original numbers here.
886 ; Be careful using this mode in nested macros though, as in some cases there may be
887 ; other copies of m# that have already been dereferenced and don't get updated correctly.
888 %xdefine %%n1 n %+ %1
889 %xdefine %%n2 n %+ %2
890 %xdefine tmp m %+ %%n1
891 CAT_XDEFINE m, %%n1, m %+ %%n2
892 CAT_XDEFINE m, %%n2, tmp
893 CAT_XDEFINE n, m %+ %%n1, %%n1
894 CAT_XDEFINE n, m %+ %%n2, %%n2
901 ; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
902 ; calls to that function will automatically load the permutation, so values can
903 ; be returned in mmregs.
904 %macro SAVE_MM_PERMUTATION 0-1
908 %xdefine %%f current_function %+ _m
912 CAT_XDEFINE %%f, %%i, m %+ %%i
917 %macro LOAD_MM_PERMUTATION 1 ; name to load from
921 CAT_XDEFINE m, %%i, %1_m %+ %%i
922 CAT_XDEFINE n, m %+ %%i, %%i
928 ; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
930 call_internal %1, %1 %+ SUFFIX
932 %macro call_internal 2
940 LOAD_MM_PERMUTATION %%i
943 ; Substitutions that reduce instruction size but are functionally equivalent
968 ;=============================================================================
969 ; AVX abstraction layer
970 ;=============================================================================
975 CAT_XDEFINE sizeofmm, i, 8
977 CAT_XDEFINE sizeofxmm, i, 16
978 CAT_XDEFINE sizeofymm, i, 32
983 %macro CHECK_AVX_INSTR_EMU 3-*
988 %error non-avx emulation of ``%%opcode'' is not supported
995 ;%2 == 1 if float, 0 if int
996 ;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
997 ;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
999 %macro RUN_AVX_INSTR 5-8+
1001 %assign %%sizeofreg sizeof%6
1003 %assign %%sizeofreg sizeof%5
1005 %assign %%sizeofreg mmsize
1007 %assign %%emulate_avx 0
1008 %if avx_enabled && %%sizeofreg >= 16
1009 %xdefine %%instr v%1
1013 %assign %%emulate_avx 1
1022 CHECK_AVX_INSTR_EMU {%1 %5, %6, %7, %8}, %5, %7, %8
1024 CHECK_AVX_INSTR_EMU {%1 %5, %6, %7}, %5, %7
1028 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1029 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1030 ; So, if the instruction is commutative with a memory arg, swap them.
1035 %if %%sizeofreg == 8
1049 %%instr %5, %6, %7, %8
1060 ;%2 == 1 if float, 0 if int
1061 ;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1062 ;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1063 %macro AVX_INSTR 1-4 0, 1, 0
1064 %macro %1 1-9 fnord, fnord, fnord, fnord, %1, %2, %3, %4
1066 RUN_AVX_INSTR %6, %7, %8, %9, %1
1068 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2
1070 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3
1072 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4
1074 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4, %5
1079 ; Instructions with both VEX and non-VEX encodings
1080 ; Non-destructive instructions are written without parameters
1081 AVX_INSTR addpd, 1, 0, 1
1082 AVX_INSTR addps, 1, 0, 1
1083 AVX_INSTR addsd, 1, 0, 1
1084 AVX_INSTR addss, 1, 0, 1
1085 AVX_INSTR addsubpd, 1, 0, 0
1086 AVX_INSTR addsubps, 1, 0, 0
1087 AVX_INSTR aesdec, 0, 0, 0
1088 AVX_INSTR aesdeclast, 0, 0, 0
1089 AVX_INSTR aesenc, 0, 0, 0
1090 AVX_INSTR aesenclast, 0, 0, 0
1092 AVX_INSTR aeskeygenassist
1093 AVX_INSTR andnpd, 1, 0, 0
1094 AVX_INSTR andnps, 1, 0, 0
1095 AVX_INSTR andpd, 1, 0, 1
1096 AVX_INSTR andps, 1, 0, 1
1097 AVX_INSTR blendpd, 1, 0, 0
1098 AVX_INSTR blendps, 1, 0, 0
1099 AVX_INSTR blendvpd, 1, 0, 0
1100 AVX_INSTR blendvps, 1, 0, 0
1101 AVX_INSTR cmppd, 1, 0, 0
1102 AVX_INSTR cmpps, 1, 0, 0
1103 AVX_INSTR cmpsd, 1, 0, 0
1104 AVX_INSTR cmpss, 1, 0, 0
1123 AVX_INSTR divpd, 1, 0, 0
1124 AVX_INSTR divps, 1, 0, 0
1125 AVX_INSTR divsd, 1, 0, 0
1126 AVX_INSTR divss, 1, 0, 0
1127 AVX_INSTR dppd, 1, 1, 0
1128 AVX_INSTR dpps, 1, 1, 0
1130 AVX_INSTR haddpd, 1, 0, 0
1131 AVX_INSTR haddps, 1, 0, 0
1132 AVX_INSTR hsubpd, 1, 0, 0
1133 AVX_INSTR hsubps, 1, 0, 0
1134 AVX_INSTR insertps, 1, 1, 0
1137 AVX_INSTR maskmovdqu
1138 AVX_INSTR maxpd, 1, 0, 1
1139 AVX_INSTR maxps, 1, 0, 1
1140 AVX_INSTR maxsd, 1, 0, 1
1141 AVX_INSTR maxss, 1, 0, 1
1142 AVX_INSTR minpd, 1, 0, 1
1143 AVX_INSTR minps, 1, 0, 1
1144 AVX_INSTR minsd, 1, 0, 1
1145 AVX_INSTR minss, 1, 0, 1
1152 AVX_INSTR movhlps, 1, 0, 0
1153 AVX_INSTR movhpd, 1, 0, 0
1154 AVX_INSTR movhps, 1, 0, 0
1155 AVX_INSTR movlhps, 1, 0, 0
1156 AVX_INSTR movlpd, 1, 0, 0
1157 AVX_INSTR movlps, 1, 0, 0
1165 AVX_INSTR movsd, 1, 0, 0
1168 AVX_INSTR movss, 1, 0, 0
1171 AVX_INSTR mpsadbw, 0, 1, 0
1172 AVX_INSTR mulpd, 1, 0, 1
1173 AVX_INSTR mulps, 1, 0, 1
1174 AVX_INSTR mulsd, 1, 0, 1
1175 AVX_INSTR mulss, 1, 0, 1
1176 AVX_INSTR orpd, 1, 0, 1
1177 AVX_INSTR orps, 1, 0, 1
1181 AVX_INSTR packsswb, 0, 0, 0
1182 AVX_INSTR packssdw, 0, 0, 0
1183 AVX_INSTR packuswb, 0, 0, 0
1184 AVX_INSTR packusdw, 0, 0, 0
1185 AVX_INSTR paddb, 0, 0, 1
1186 AVX_INSTR paddw, 0, 0, 1
1187 AVX_INSTR paddd, 0, 0, 1
1188 AVX_INSTR paddq, 0, 0, 1
1189 AVX_INSTR paddsb, 0, 0, 1
1190 AVX_INSTR paddsw, 0, 0, 1
1191 AVX_INSTR paddusb, 0, 0, 1
1192 AVX_INSTR paddusw, 0, 0, 1
1193 AVX_INSTR palignr, 0, 1, 0
1194 AVX_INSTR pand, 0, 0, 1
1195 AVX_INSTR pandn, 0, 0, 0
1196 AVX_INSTR pavgb, 0, 0, 1
1197 AVX_INSTR pavgw, 0, 0, 1
1198 AVX_INSTR pblendvb, 0, 0, 0
1199 AVX_INSTR pblendw, 0, 1, 0
1200 AVX_INSTR pclmulqdq, 0, 1, 0
1205 AVX_INSTR pcmpeqb, 0, 0, 1
1206 AVX_INSTR pcmpeqw, 0, 0, 1
1207 AVX_INSTR pcmpeqd, 0, 0, 1
1208 AVX_INSTR pcmpeqq, 0, 0, 1
1209 AVX_INSTR pcmpgtb, 0, 0, 0
1210 AVX_INSTR pcmpgtw, 0, 0, 0
1211 AVX_INSTR pcmpgtd, 0, 0, 0
1212 AVX_INSTR pcmpgtq, 0, 0, 0
1217 AVX_INSTR phaddw, 0, 0, 0
1218 AVX_INSTR phaddd, 0, 0, 0
1219 AVX_INSTR phaddsw, 0, 0, 0
1220 AVX_INSTR phminposuw
1221 AVX_INSTR phsubw, 0, 0, 0
1222 AVX_INSTR phsubd, 0, 0, 0
1223 AVX_INSTR phsubsw, 0, 0, 0
1224 AVX_INSTR pinsrb, 0, 1, 0
1225 AVX_INSTR pinsrd, 0, 1, 0
1226 AVX_INSTR pinsrq, 0, 1, 0
1227 AVX_INSTR pinsrw, 0, 1, 0
1228 AVX_INSTR pmaddwd, 0, 0, 1
1229 AVX_INSTR pmaddubsw, 0, 0, 0
1230 AVX_INSTR pmaxsb, 0, 0, 1
1231 AVX_INSTR pmaxsw, 0, 0, 1
1232 AVX_INSTR pmaxsd, 0, 0, 1
1233 AVX_INSTR pmaxub, 0, 0, 1
1234 AVX_INSTR pmaxuw, 0, 0, 1
1235 AVX_INSTR pmaxud, 0, 0, 1
1236 AVX_INSTR pminsb, 0, 0, 1
1237 AVX_INSTR pminsw, 0, 0, 1
1238 AVX_INSTR pminsd, 0, 0, 1
1239 AVX_INSTR pminub, 0, 0, 1
1240 AVX_INSTR pminuw, 0, 0, 1
1241 AVX_INSTR pminud, 0, 0, 1
1255 AVX_INSTR pmuldq, 0, 0, 1
1256 AVX_INSTR pmulhrsw, 0, 0, 1
1257 AVX_INSTR pmulhuw, 0, 0, 1
1258 AVX_INSTR pmulhw, 0, 0, 1
1259 AVX_INSTR pmullw, 0, 0, 1
1260 AVX_INSTR pmulld, 0, 0, 1
1261 AVX_INSTR pmuludq, 0, 0, 1
1262 AVX_INSTR por, 0, 0, 1
1263 AVX_INSTR psadbw, 0, 0, 1
1264 AVX_INSTR pshufb, 0, 0, 0
1268 AVX_INSTR psignb, 0, 0, 0
1269 AVX_INSTR psignw, 0, 0, 0
1270 AVX_INSTR psignd, 0, 0, 0
1271 AVX_INSTR psllw, 0, 0, 0
1272 AVX_INSTR pslld, 0, 0, 0
1273 AVX_INSTR psllq, 0, 0, 0
1274 AVX_INSTR pslldq, 0, 0, 0
1275 AVX_INSTR psraw, 0, 0, 0
1276 AVX_INSTR psrad, 0, 0, 0
1277 AVX_INSTR psrlw, 0, 0, 0
1278 AVX_INSTR psrld, 0, 0, 0
1279 AVX_INSTR psrlq, 0, 0, 0
1280 AVX_INSTR psrldq, 0, 0, 0
1281 AVX_INSTR psubb, 0, 0, 0
1282 AVX_INSTR psubw, 0, 0, 0
1283 AVX_INSTR psubd, 0, 0, 0
1284 AVX_INSTR psubq, 0, 0, 0
1285 AVX_INSTR psubsb, 0, 0, 0
1286 AVX_INSTR psubsw, 0, 0, 0
1287 AVX_INSTR psubusb, 0, 0, 0
1288 AVX_INSTR psubusw, 0, 0, 0
1290 AVX_INSTR punpckhbw, 0, 0, 0
1291 AVX_INSTR punpckhwd, 0, 0, 0
1292 AVX_INSTR punpckhdq, 0, 0, 0
1293 AVX_INSTR punpckhqdq, 0, 0, 0
1294 AVX_INSTR punpcklbw, 0, 0, 0
1295 AVX_INSTR punpcklwd, 0, 0, 0
1296 AVX_INSTR punpckldq, 0, 0, 0
1297 AVX_INSTR punpcklqdq, 0, 0, 0
1298 AVX_INSTR pxor, 0, 0, 1
1299 AVX_INSTR rcpps, 1, 0, 0
1300 AVX_INSTR rcpss, 1, 0, 0
1305 AVX_INSTR rsqrtps, 1, 0, 0
1306 AVX_INSTR rsqrtss, 1, 0, 0
1307 AVX_INSTR shufpd, 1, 1, 0
1308 AVX_INSTR shufps, 1, 1, 0
1309 AVX_INSTR sqrtpd, 1, 0, 0
1310 AVX_INSTR sqrtps, 1, 0, 0
1311 AVX_INSTR sqrtsd, 1, 0, 0
1312 AVX_INSTR sqrtss, 1, 0, 0
1314 AVX_INSTR subpd, 1, 0, 0
1315 AVX_INSTR subps, 1, 0, 0
1316 AVX_INSTR subsd, 1, 0, 0
1317 AVX_INSTR subss, 1, 0, 0
1320 AVX_INSTR unpckhpd, 1, 0, 0
1321 AVX_INSTR unpckhps, 1, 0, 0
1322 AVX_INSTR unpcklpd, 1, 0, 0
1323 AVX_INSTR unpcklps, 1, 0, 0
1324 AVX_INSTR xorpd, 1, 0, 1
1325 AVX_INSTR xorps, 1, 0, 1
1327 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1328 AVX_INSTR pfadd, 1, 0, 1
1329 AVX_INSTR pfsub, 1, 0, 0
1330 AVX_INSTR pfmul, 1, 0, 1
1332 ; base-4 constants for shuffles
1335 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1337 CAT_XDEFINE q000, j, i
1339 CAT_XDEFINE q00, j, i
1341 CAT_XDEFINE q0, j, i
1351 %macro %1 4-7 %1, %2, %3
1361 FMA_INSTR pmacsdd, pmulld, paddd
1362 FMA_INSTR pmacsww, pmullw, paddw
1363 FMA_INSTR pmadcswd, pmaddwd, paddd
1365 ; convert FMA4 to FMA3 if possible
1367 %macro %1 4-8 %1, %2, %3, %4
1371 v%6 %1, %4, %3 ; %1 = %1 * %3 + %4
1373 v%7 %1, %2, %4 ; %1 = %2 * %1 + %4
1375 v%8 %1, %2, %3 ; %1 = %2 * %3 + %1
1377 %error fma3 emulation of ``%5 %1, %2, %3, %4'' is not supported
1382 FMA4_INSTR fmaddpd, fmadd132pd, fmadd213pd, fmadd231pd
1383 FMA4_INSTR fmaddps, fmadd132ps, fmadd213ps, fmadd231ps
1384 FMA4_INSTR fmaddsd, fmadd132sd, fmadd213sd, fmadd231sd
1385 FMA4_INSTR fmaddss, fmadd132ss, fmadd213ss, fmadd231ss
1387 FMA4_INSTR fmaddsubpd, fmaddsub132pd, fmaddsub213pd, fmaddsub231pd
1388 FMA4_INSTR fmaddsubps, fmaddsub132ps, fmaddsub213ps, fmaddsub231ps
1389 FMA4_INSTR fmsubaddpd, fmsubadd132pd, fmsubadd213pd, fmsubadd231pd
1390 FMA4_INSTR fmsubaddps, fmsubadd132ps, fmsubadd213ps, fmsubadd231ps
1392 FMA4_INSTR fmsubpd, fmsub132pd, fmsub213pd, fmsub231pd
1393 FMA4_INSTR fmsubps, fmsub132ps, fmsub213ps, fmsub231ps
1394 FMA4_INSTR fmsubsd, fmsub132sd, fmsub213sd, fmsub231sd
1395 FMA4_INSTR fmsubss, fmsub132ss, fmsub213ss, fmsub231ss
1397 FMA4_INSTR fnmaddpd, fnmadd132pd, fnmadd213pd, fnmadd231pd
1398 FMA4_INSTR fnmaddps, fnmadd132ps, fnmadd213ps, fnmadd231ps
1399 FMA4_INSTR fnmaddsd, fnmadd132sd, fnmadd213sd, fnmadd231sd
1400 FMA4_INSTR fnmaddss, fnmadd132ss, fnmadd213ss, fnmadd231ss
1402 FMA4_INSTR fnmsubpd, fnmsub132pd, fnmsub213pd, fnmsub231pd
1403 FMA4_INSTR fnmsubps, fnmsub132ps, fnmsub213ps, fnmsub231ps
1404 FMA4_INSTR fnmsubsd, fnmsub132sd, fnmsub213sd, fnmsub231sd
1405 FMA4_INSTR fnmsubss, fnmsub132ss, fnmsub213ss, fnmsub231ss