2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
25 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
26 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
27 #define BCM2708_PERI_BASE 0x3F000000 // pi3
28 #define BCM2708_PERI_SIZE 0x01000000
29 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
30 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
31 #define GPIO_ADDR 0x200000 /* GPIO controller */
32 #define GPCLK_ADDR 0x101000
33 #define CLK_PASSWD 0x5a000000
34 #define CLK_GP0_CTL 0x070
35 #define CLK_GP0_DIV 0x074
41 #define STATUSREGADDR \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_CLR = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_SET = 1 << SA0; \
51 GPIO_CLR = 1 << SA1; \
54 GPIO_CLR = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 GPIO_SET = 1 << SA0; \
59 GPIO_SET = 1 << SA1; \
62 #define PAGE_SIZE (4 * 1024)
63 #define BLOCK_SIZE (4 * 1024)
65 #define GPIOSET(no, ishigh) \
70 reset |= (1 << (no)); \
73 #define FASTBASE 0x08000000
74 #define FASTSIZE (256*1024*1024)
76 #define GAYLEBASE 0xD80000
77 #define GAYLESIZE (448*1024)
79 #define KICKBASE 0xF80000
80 #define KICKSIZE (512*1024)
84 int gayle_emulation_enabled = 1;
89 volatile unsigned int *gpio;
90 volatile unsigned int *gpclk;
91 volatile unsigned int gpfsel0;
92 volatile unsigned int gpfsel1;
93 volatile unsigned int gpfsel2;
94 volatile unsigned int gpfsel0_o;
95 volatile unsigned int gpfsel1_o;
96 volatile unsigned int gpfsel2_o;
98 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
100 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
101 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
102 #define SET_GPIO_ALT(g, a) \
103 *(gpio + (((g) / 10))) |= \
104 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
107 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
109 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
111 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
113 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
114 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
118 uint32_t read8(uint32_t address);
119 void write8(uint32_t address, uint32_t data);
121 uint32_t read16(uint32_t address);
122 void write16(uint32_t address, uint32_t data);
124 void write32(uint32_t address, uint32_t data);
125 uint32_t read32(uint32_t address);
127 uint16_t read_reg(void);
128 void write_reg(unsigned int value);
130 volatile uint16_t srdata;
131 volatile uint32_t srdata2;
132 volatile uint32_t srdata2_old;
134 unsigned char g_kick[KICKSIZE];
135 unsigned char g_ram[FASTSIZE]; /* RAM */
136 unsigned char toggle;
137 static volatile unsigned char ovl;
138 static volatile unsigned char maprom;
140 void sigint_handler(int sig_num) {
141 printf("\n Exit Ctrl+C %d\n", sig_num);
145 void *iplThread(void *args) {
146 printf("IPL thread running/n");
150 if (GET_GPIO(1) == 0){
152 m68k_end_timeslice();
153 //printf("thread!/n");
162 int main(int argc, char *argv[]) {
164 const struct sched_param priority = {99};
166 // Some command line switch stuffles
167 for (g = 1; g < argc; g++) {
168 if (strcmp(argv[g], "--disable-gayle") == 0) {
169 gayle_emulation_enabled = 0;
173 sched_setscheduler(0, SCHED_FIFO, &priority);
174 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
178 signal(SIGINT, sigint_handler);
181 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
183 printf("Enable 200MHz GPCLK0 on GPIO4\n");
185 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
187 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
190 *(gpclk + (CLK_GP0_DIV / 4)) =
191 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
193 *(gpclk + (CLK_GP0_CTL / 4)) =
194 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
196 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
200 SET_GPIO_ALT(4, 0); // gpclk0
210 // set gpio0 (aux0) and gpio1 (aux1) to input
214 // Set GPIO pins 6,7 and 8-23 to output
215 for (g = 6; g <= 23; g++) {
219 printf("Precalculate GPIO8-23 as Output\n");
220 gpfsel0_o = *(gpio); // store gpio ddr
221 printf("gpfsel0: %#x\n", gpfsel0_o);
222 gpfsel1_o = *(gpio + 1); // store gpio ddr
223 printf("gpfsel1: %#x\n", gpfsel1_o);
224 gpfsel2_o = *(gpio + 2); // store gpio ddr
225 printf("gpfsel2: %#x\n", gpfsel2_o);
227 // Set GPIO pins 8-23 to input
228 for (g = 8; g <= 23; g++) {
231 printf("Precalculate GPIO8-23 as Input\n");
232 gpfsel0 = *(gpio); // store gpio ddr
233 printf("gpfsel0: %#x\n", gpfsel0);
234 gpfsel1 = *(gpio + 1); // store gpio ddr
235 printf("gpfsel1: %#x\n", gpfsel1);
236 gpfsel2 = *(gpio + 2); // store gpio ddr
237 printf("gpfsel2: %#x\n", gpfsel2);
246 // reset cpld statemachine first
254 // load kick.rom if present
257 fd = open("kick.rom", O_RDONLY);
259 printf("Failed loading kick.rom, using motherboard kickstart\n");
262 int size = (int)lseek(fd, 0, SEEK_END);
263 if (size == 0x40000) {
264 lseek(fd, 0, SEEK_SET);
265 read(fd, &g_kick, size);
266 lseek(fd, 0, SEEK_SET);
267 read(fd, &g_kick[0x40000], size);
269 lseek(fd, 0, SEEK_SET);
270 read(fd, &g_kick, size);
272 printf("Loaded kick.rom with size %d kib\n", size / 1024);
275 // reset amiga and statemachine
278 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
279 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
284 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
288 m68k_set_reg(M68K_REG_PC, 0xF80002);
290 m68k_set_reg(M68K_REG_PC, 0x0);
296 err = pthread_create(&id, NULL, &iplThread, NULL);
298 printf("\ncan't create IPL thread :[%s]", strerror(err));
300 printf("\n IPL Thread created successfully\n");
310 m68k_set_irq((srdata >> 13) & 0xff);
318 if (GET_GPIO(1) == 0){
320 m68k_set_irq((srdata >> 13) & 0xff);
322 if (CheckIrq() == 1){
323 write16(0xdff09c, 0x8008);
334 void cpu_pulse_reset(void) {
336 // printf("Status Reg%x\n",read_reg());
339 // printf("Status Reg%x\n",read_reg());
342 int cpu_irq_ack(int level) {
343 printf("cpu irq ack\n");
347 unsigned int m68k_read_memory_8(unsigned int address) {
348 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
349 return g_ram[address - FASTBASE];
353 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
354 return g_kick[address - KICKBASE];
358 if (gayle_emulation_enabled) {
359 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
360 return readGayleB(address);
365 // if (address < 0xffffff) {
366 return read8((uint32_t)address);
372 unsigned int m68k_read_memory_16(unsigned int address) {
373 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
374 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
378 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
379 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
383 if (gayle_emulation_enabled) {
384 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
385 return readGayle(address);
389 // if (address < 0xffffff) {
391 return (unsigned int)read16((uint32_t)address);
397 unsigned int m68k_read_memory_32(unsigned int address) {
398 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
399 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
403 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
404 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
408 if (gayle_emulation_enabled) {
409 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
410 return readGayleL(address);
414 // if (address < 0xffffff) {
416 uint16_t a = read16(address);
417 uint16_t b = read16(address + 2);
418 return (a << 16) | b;
424 void m68k_write_memory_8(unsigned int address, unsigned int value) {
425 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
426 g_ram[address - FASTBASE] = value;
430 if (gayle_emulation_enabled) {
431 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
432 writeGayleB(address, value);
437 if (address == 0xbfe001) {
438 ovl = (value & (1 << 0));
439 printf("OVL:%x\n", ovl);
442 // if (address < 0xffffff) {
444 write8((uint32_t)address, value);
451 void m68k_write_memory_16(unsigned int address, unsigned int value) {
452 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
453 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
457 if (gayle_emulation_enabled) {
458 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
459 writeGayle(address, value);
464 // if (address < 0xffffff) {
466 write16((uint32_t)address, value);
472 void m68k_write_memory_32(unsigned int address, unsigned int value) {
473 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
474 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
478 if (gayle_emulation_enabled) {
479 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
480 writeGayleL(address, value);
484 // if (address < 0xffffff) {
486 write16(address, value >> 16);
487 write16(address + 2, value);
494 void write16(uint32_t address, uint32_t data) {
495 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
496 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
497 uint32_t addr_l_s = (address >> 16) << 8;
498 uint32_t addr_l_r = (~address >> 16) << 8;
499 uint32_t data_s = (data & 0x0000ffff) << 8;
500 uint32_t data_r = (~data & 0x0000ffff) << 8;
502 // asm volatile ("dmb" ::: "memory");
505 *(gpio + 1) = gpfsel1_o;
506 *(gpio + 2) = gpfsel2_o;
508 *(gpio + 7) = addr_h_s;
509 *(gpio + 10) = addr_h_r;
513 *(gpio + 7) = addr_l_s;
514 *(gpio + 10) = addr_l_r;
519 *(gpio + 7) = data_s;
520 *(gpio + 10) = data_r;
525 *(gpio + 1) = gpfsel1;
526 *(gpio + 2) = gpfsel2;
527 while ((GET_GPIO(0)))
529 // asm volatile ("dmb" ::: "memory");
532 void write8(uint32_t address, uint32_t data) {
533 if ((address & 1) == 0)
534 data = data + (data << 8); // EVEN, A0=0,UDS
536 data = data & 0xff; // ODD , A0=1,LDS
537 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
538 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
539 uint32_t addr_l_s = (address >> 16) << 8;
540 uint32_t addr_l_r = (~address >> 16) << 8;
541 uint32_t data_s = (data & 0x0000ffff) << 8;
542 uint32_t data_r = (~data & 0x0000ffff) << 8;
544 // asm volatile ("dmb" ::: "memory");
547 *(gpio + 1) = gpfsel1_o;
548 *(gpio + 2) = gpfsel2_o;
550 *(gpio + 7) = addr_h_s;
551 *(gpio + 10) = addr_h_r;
555 *(gpio + 7) = addr_l_s;
556 *(gpio + 10) = addr_l_r;
561 *(gpio + 7) = data_s;
562 *(gpio + 10) = data_r;
567 *(gpio + 1) = gpfsel1;
568 *(gpio + 2) = gpfsel2;
569 while ((GET_GPIO(0)))
571 // asm volatile ("dmb" ::: "memory");
574 uint32_t read16(uint32_t address) {
576 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
577 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
578 uint32_t addr_l_s = (address >> 16) << 8;
579 uint32_t addr_l_r = (~address >> 16) << 8;
581 // asm volatile ("dmb" ::: "memory");
584 *(gpio + 1) = gpfsel1_o;
585 *(gpio + 2) = gpfsel2_o;
587 *(gpio + 7) = addr_h_s;
588 *(gpio + 10) = addr_h_r;
592 *(gpio + 7) = addr_l_s;
593 *(gpio + 10) = addr_l_r;
599 *(gpio + 1) = gpfsel1;
600 *(gpio + 2) = gpfsel2;
602 while (!(GET_GPIO(0)))
607 // asm volatile ("dmb" ::: "memory");
608 return (val >> 8) & 0xffff;
611 uint32_t read8(uint32_t address) {
613 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
614 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
615 uint32_t addr_l_s = (address >> 16) << 8;
616 uint32_t addr_l_r = (~address >> 16) << 8;
618 // asm volatile ("dmb" ::: "memory");
621 *(gpio + 1) = gpfsel1_o;
622 *(gpio + 2) = gpfsel2_o;
624 *(gpio + 7) = addr_h_s;
625 *(gpio + 10) = addr_h_r;
629 *(gpio + 7) = addr_l_s;
630 *(gpio + 10) = addr_l_r;
636 *(gpio + 1) = gpfsel1;
637 *(gpio + 2) = gpfsel2;
640 while (!(GET_GPIO(0)))
645 // asm volatile ("dmb" ::: "memory");
647 val = (val >> 8) & 0xffff;
648 if ((address & 1) == 0)
649 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
651 return val & 0xff; // ODD , A0=1,LDS
654 /******************************************************/
656 void write_reg(unsigned int value) {
659 *(gpio + 1) = gpfsel1_o;
660 *(gpio + 2) = gpfsel2_o;
661 *(gpio + 7) = (value & 0xffff) << 8;
662 *(gpio + 10) = (~value & 0xffff) << 8;
664 GPIO_CLR = 1 << 7; // delay
669 *(gpio + 1) = gpfsel1;
670 *(gpio + 2) = gpfsel2;
673 uint16_t read_reg(void) {
678 *(gpio + 1) = gpfsel1;
679 *(gpio + 2) = gpfsel2;
681 GPIO_CLR = 1 << 6; // delay
686 return (uint16_t)(val >> 8);
690 // Set up a memory regions to access GPIO
694 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
695 printf("can't open /dev/mem \n");
701 NULL, // Any adddress in our space will do
702 BCM2708_PERI_SIZE, // Map length
703 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
704 MAP_SHARED, // Shared with other processes
705 mem_fd, // File to map
706 BCM2708_PERI_BASE // Offset to GPIO peripheral
709 close(mem_fd); // No need to keep mem_fd open after mmap
711 if (gpio_map == MAP_FAILED) {
712 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
716 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
717 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;