2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
22 #include "a314/a314.h"
27 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
28 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
29 #define BCM2708_PERI_BASE 0x3F000000 // pi3
30 #define BCM2708_PERI_SIZE 0x01000000
31 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
32 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
33 #define GPIO_ADDR 0x200000 /* GPIO controller */
34 #define GPCLK_ADDR 0x101000
35 #define CLK_PASSWD 0x5a000000
36 #define CLK_GP0_CTL 0x070
37 #define CLK_GP0_DIV 0x074
43 #define STATUSREGADDR \
44 GPIO_CLR = 1 << SA0; \
45 GPIO_CLR = 1 << SA1; \
48 GPIO_CLR = 1 << SA0; \
49 GPIO_CLR = 1 << SA1; \
52 GPIO_SET = 1 << SA0; \
53 GPIO_CLR = 1 << SA1; \
56 GPIO_CLR = 1 << SA0; \
57 GPIO_SET = 1 << SA1; \
60 GPIO_SET = 1 << SA0; \
61 GPIO_SET = 1 << SA1; \
64 #define PAGE_SIZE (4 * 1024)
65 #define BLOCK_SIZE (4 * 1024)
67 #define GPIOSET(no, ishigh) \
72 reset |= (1 << (no)); \
75 int fast_base_configured;
76 unsigned int fast_base;
77 #define FAST_SIZE (8 * 1024 * 1024)
79 #define GAYLEBASE 0xD80000
80 #define GAYLESIZE (448 * 1024)
82 #define KICKBASE 0xF80000
83 #define KICKSIZE (512 * 1024)
85 #define AC_BASE 0xE80000
86 #define AC_SIZE (64 * 1024)
88 #define AC_PIC_COUNT 1
89 int ac_current_pic = 0;
94 int gayle_emulation_enabled = 1;
99 volatile unsigned int *gpio;
100 volatile unsigned int *gpclk;
101 volatile unsigned int gpfsel0;
102 volatile unsigned int gpfsel1;
103 volatile unsigned int gpfsel2;
104 volatile unsigned int gpfsel0_o;
105 volatile unsigned int gpfsel1_o;
106 volatile unsigned int gpfsel2_o;
108 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
110 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
111 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
112 #define SET_GPIO_ALT(g, a) \
113 *(gpio + (((g) / 10))) |= \
114 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
117 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
119 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
121 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
123 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
124 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
128 uint32_t read8(uint32_t address);
129 void write8(uint32_t address, uint32_t data);
131 uint32_t read16(uint32_t address);
132 void write16(uint32_t address, uint32_t data);
134 void write32(uint32_t address, uint32_t data);
135 uint32_t read32(uint32_t address);
137 uint16_t read_reg(void);
138 void write_reg(unsigned int value);
140 volatile uint16_t srdata;
141 volatile uint32_t srdata2;
142 volatile uint32_t srdata2_old;
144 unsigned char g_kick[KICKSIZE];
145 unsigned char fast_ram_array[FAST_SIZE]; /* RAM */
146 unsigned char toggle;
147 static volatile unsigned char ovl;
148 static volatile unsigned char maprom;
150 void sigint_handler(int sig_num) {
151 printf("\n Exit Ctrl+C %d\n", sig_num);
155 void *iplThread(void *args) {
156 printf("IPL thread running/n");
159 if (GET_GPIO(1) == 0) {
161 m68k_end_timeslice();
162 //printf("thread!/n");
170 int main(int argc, char *argv[]) {
172 const struct sched_param priority = {99};
174 // Some command line switch stuffles
175 for (g = 1; g < argc; g++) {
176 if (strcmp(argv[g], "--disable-gayle") == 0) {
177 gayle_emulation_enabled = 0;
182 int err = a314_init();
184 printf("Unable to initialize A314 emulation\n");
189 sched_setscheduler(0, SCHED_FIFO, &priority);
190 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
194 signal(SIGINT, sigint_handler);
197 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
199 printf("Enable 200MHz GPCLK0 on GPIO4\n");
201 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
203 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
206 *(gpclk + (CLK_GP0_DIV / 4)) =
207 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
209 *(gpclk + (CLK_GP0_CTL / 4)) =
210 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
212 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
216 SET_GPIO_ALT(4, 0); // gpclk0
226 // set gpio0 (aux0) and gpio1 (aux1) to input
230 // Set GPIO pins 6,7 and 8-23 to output
231 for (g = 6; g <= 23; g++) {
235 printf("Precalculate GPIO8-23 as Output\n");
236 gpfsel0_o = *(gpio); // store gpio ddr
237 printf("gpfsel0: %#x\n", gpfsel0_o);
238 gpfsel1_o = *(gpio + 1); // store gpio ddr
239 printf("gpfsel1: %#x\n", gpfsel1_o);
240 gpfsel2_o = *(gpio + 2); // store gpio ddr
241 printf("gpfsel2: %#x\n", gpfsel2_o);
243 // Set GPIO pins 8-23 to input
244 for (g = 8; g <= 23; g++) {
247 printf("Precalculate GPIO8-23 as Input\n");
248 gpfsel0 = *(gpio); // store gpio ddr
249 printf("gpfsel0: %#x\n", gpfsel0);
250 gpfsel1 = *(gpio + 1); // store gpio ddr
251 printf("gpfsel1: %#x\n", gpfsel1);
252 gpfsel2 = *(gpio + 2); // store gpio ddr
253 printf("gpfsel2: %#x\n", gpfsel2);
262 // reset cpld statemachine first
270 // load kick.rom if present
273 fd = open("kick.rom", O_RDONLY);
275 printf("Failed loading kick.rom, using motherboard kickstart\n");
278 int size = (int)lseek(fd, 0, SEEK_END);
279 if (size == 0x40000) {
280 lseek(fd, 0, SEEK_SET);
281 read(fd, &g_kick, size);
282 lseek(fd, 0, SEEK_SET);
283 read(fd, &g_kick[0x40000], size);
285 lseek(fd, 0, SEEK_SET);
286 read(fd, &g_kick, size);
288 printf("Loaded kick.rom with size %d kib\n", size / 1024);
291 // reset amiga and statemachine
294 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
295 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
300 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
304 m68k_set_reg(M68K_REG_PC, 0xF80002);
306 m68k_set_reg(M68K_REG_PC, 0x0);
312 err = pthread_create(&id, NULL, &iplThread, NULL);
314 printf("\ncan't create IPL thread :[%s]", strerror(err));
316 printf("\n IPL Thread created successfully\n");
325 m68k_set_irq((srdata >> 13) & 0xff);
333 a314_process_events();
336 if (GET_GPIO(1) == 0) {
338 m68k_set_irq((srdata >> 13) & 0xff);
340 if (CheckIrq() == 1) {
341 write16(0xdff09c, 0x8008);
351 void cpu_pulse_reset(void) {
353 // printf("Status Reg%x\n",read_reg());
356 // printf("Status Reg%x\n",read_reg());
359 int cpu_irq_ack(int level) {
360 printf("cpu irq ack\n");
364 static unsigned char ac_fast_ram_rom[] = {
365 0xe, 0x0, // 00/02, link into memory free list, 8 MB
366 0x6, 0x9, // 04/06, product id
367 0x8, 0x0, // 08/0a, preference to 8 MB space
368 0x0, 0x0, // 0c/0e, reserved
369 0x0, 0x7, 0xd, 0xb, // 10/12/14/16, mfg id
370 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x2, 0x0 // 18/.../26, serial
373 static unsigned int ac_fast_ram_read_memory_8(unsigned int address) {
374 unsigned char val = 0;
375 if ((address & 1) == 0 && (address / 2) < sizeof(ac_fast_ram_rom))
376 val = ac_fast_ram_rom[address / 2];
378 if (address != 0 && address != 2 && address != 40 && address != 42)
380 return (unsigned int)val;
383 static void ac_fast_ram_write_memory_8(unsigned int address, unsigned int value) {
386 if (address == 0x4a) { // base[19:16]
387 fast_base = (value & 0xf0) << (16 - 4);
388 } else if (address == 0x48) { // base[23:20]
389 fast_base &= 0xff0fffff;
390 fast_base |= (value & 0xf0) << (20 - 4);
391 fast_base_configured = 1;
393 } else if (address == 0x4c) { // shut up
399 if (ac_current_pic == AC_PIC_COUNT)
404 static unsigned int autoconfig_read_memory_8(unsigned int address) {
405 if (ac_current_pic == 0) {
406 return ac_fast_ram_read_memory_8(address);
410 static void autoconfig_write_memory_8(unsigned int address, unsigned int value) {
411 if (ac_current_pic == 0) {
412 return ac_fast_ram_write_memory_8(address, value);
416 unsigned int m68k_read_memory_8(unsigned int address) {
417 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
418 return fast_ram_array[address - fast_base];
421 if (!ac_done && address >= AC_BASE && address < AC_BASE + AC_SIZE) {
422 return autoconfig_read_memory_8(address - AC_BASE);
426 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
427 return g_kick[address - KICKBASE];
431 if (gayle_emulation_enabled) {
432 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
433 return readGayleB(address);
438 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
439 return a314_read_memory_8(address - A314_COM_AREA_BASE);
444 // if (address < 0xffffff) {
445 return read8((uint32_t)address);
451 unsigned int m68k_read_memory_16(unsigned int address) {
452 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
453 return be16toh(*(uint16_t *)&fast_ram_array[address - fast_base]);
457 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
458 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
462 if (gayle_emulation_enabled) {
463 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
464 return readGayle(address);
469 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
470 return a314_read_memory_16(address - A314_COM_AREA_BASE);
474 // if (address < 0xffffff) {
476 return (unsigned int)read16((uint32_t)address);
482 unsigned int m68k_read_memory_32(unsigned int address) {
483 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
484 return be32toh(*(uint32_t *)&fast_ram_array[address - fast_base]);
488 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
489 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
493 if (gayle_emulation_enabled) {
494 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
495 return readGayleL(address);
500 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
501 return a314_read_memory_32(address - A314_COM_AREA_BASE);
505 // if (address < 0xffffff) {
507 uint16_t a = read16(address);
508 uint16_t b = read16(address + 2);
509 return (a << 16) | b;
515 void m68k_write_memory_8(unsigned int address, unsigned int value) {
516 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
517 fast_ram_array[address - fast_base] = value;
521 if (!ac_done && address >= AC_BASE && address < AC_BASE + AC_SIZE) {
522 return autoconfig_write_memory_8(address - AC_BASE, value);
525 if (gayle_emulation_enabled) {
526 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
527 writeGayleB(address, value);
533 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
534 a314_write_memory_8(address - A314_COM_AREA_BASE, value);
540 if (address == 0xbfe001) {
541 ovl = (value & (1 << 0));
542 printf("OVL:%x\n", ovl);
545 // if (address < 0xffffff) {
547 write8((uint32_t)address, value);
554 void m68k_write_memory_16(unsigned int address, unsigned int value) {
555 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
556 *(uint16_t *)&fast_ram_array[address - fast_base] = htobe16(value);
560 if (gayle_emulation_enabled) {
561 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
562 writeGayle(address, value);
568 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
569 a314_write_memory_16(address - A314_COM_AREA_BASE, value);
574 // if (address < 0xffffff) {
576 write16((uint32_t)address, value);
582 void m68k_write_memory_32(unsigned int address, unsigned int value) {
583 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
584 *(uint32_t *)&fast_ram_array[address - fast_base] = htobe32(value);
588 if (gayle_emulation_enabled) {
589 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
590 writeGayleL(address, value);
595 if (address >= A314_COM_AREA_BASE && address < A314_COM_AREA_BASE + A314_COM_AREA_SIZE) {
596 a314_write_memory_32(address - A314_COM_AREA_BASE, value);
601 // if (address < 0xffffff) {
603 write16(address, value >> 16);
604 write16(address + 2, value);
611 void write16(uint32_t address, uint32_t data) {
612 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
613 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
614 uint32_t addr_l_s = (address >> 16) << 8;
615 uint32_t addr_l_r = (~address >> 16) << 8;
616 uint32_t data_s = (data & 0x0000ffff) << 8;
617 uint32_t data_r = (~data & 0x0000ffff) << 8;
619 // asm volatile ("dmb" ::: "memory");
622 *(gpio + 1) = gpfsel1_o;
623 *(gpio + 2) = gpfsel2_o;
625 *(gpio + 7) = addr_h_s;
626 *(gpio + 10) = addr_h_r;
630 *(gpio + 7) = addr_l_s;
631 *(gpio + 10) = addr_l_r;
636 *(gpio + 7) = data_s;
637 *(gpio + 10) = data_r;
642 *(gpio + 1) = gpfsel1;
643 *(gpio + 2) = gpfsel2;
644 while ((GET_GPIO(0)))
646 // asm volatile ("dmb" ::: "memory");
649 void write8(uint32_t address, uint32_t data) {
650 if ((address & 1) == 0)
651 data = data + (data << 8); // EVEN, A0=0,UDS
653 data = data & 0xff; // ODD , A0=1,LDS
654 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
655 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
656 uint32_t addr_l_s = (address >> 16) << 8;
657 uint32_t addr_l_r = (~address >> 16) << 8;
658 uint32_t data_s = (data & 0x0000ffff) << 8;
659 uint32_t data_r = (~data & 0x0000ffff) << 8;
661 // asm volatile ("dmb" ::: "memory");
664 *(gpio + 1) = gpfsel1_o;
665 *(gpio + 2) = gpfsel2_o;
667 *(gpio + 7) = addr_h_s;
668 *(gpio + 10) = addr_h_r;
672 *(gpio + 7) = addr_l_s;
673 *(gpio + 10) = addr_l_r;
678 *(gpio + 7) = data_s;
679 *(gpio + 10) = data_r;
684 *(gpio + 1) = gpfsel1;
685 *(gpio + 2) = gpfsel2;
686 while ((GET_GPIO(0)))
688 // asm volatile ("dmb" ::: "memory");
691 uint32_t read16(uint32_t address) {
693 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
694 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
695 uint32_t addr_l_s = (address >> 16) << 8;
696 uint32_t addr_l_r = (~address >> 16) << 8;
698 // asm volatile ("dmb" ::: "memory");
701 *(gpio + 1) = gpfsel1_o;
702 *(gpio + 2) = gpfsel2_o;
704 *(gpio + 7) = addr_h_s;
705 *(gpio + 10) = addr_h_r;
709 *(gpio + 7) = addr_l_s;
710 *(gpio + 10) = addr_l_r;
716 *(gpio + 1) = gpfsel1;
717 *(gpio + 2) = gpfsel2;
719 while (!(GET_GPIO(0)))
724 // asm volatile ("dmb" ::: "memory");
725 return (val >> 8) & 0xffff;
728 uint32_t read8(uint32_t address) {
730 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
731 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
732 uint32_t addr_l_s = (address >> 16) << 8;
733 uint32_t addr_l_r = (~address >> 16) << 8;
735 // asm volatile ("dmb" ::: "memory");
738 *(gpio + 1) = gpfsel1_o;
739 *(gpio + 2) = gpfsel2_o;
741 *(gpio + 7) = addr_h_s;
742 *(gpio + 10) = addr_h_r;
746 *(gpio + 7) = addr_l_s;
747 *(gpio + 10) = addr_l_r;
753 *(gpio + 1) = gpfsel1;
754 *(gpio + 2) = gpfsel2;
757 while (!(GET_GPIO(0)))
762 // asm volatile ("dmb" ::: "memory");
764 val = (val >> 8) & 0xffff;
765 if ((address & 1) == 0)
766 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
768 return val & 0xff; // ODD , A0=1,LDS
771 /******************************************************/
773 void write_reg(unsigned int value) {
776 *(gpio + 1) = gpfsel1_o;
777 *(gpio + 2) = gpfsel2_o;
778 *(gpio + 7) = (value & 0xffff) << 8;
779 *(gpio + 10) = (~value & 0xffff) << 8;
781 GPIO_CLR = 1 << 7; // delay
786 *(gpio + 1) = gpfsel1;
787 *(gpio + 2) = gpfsel2;
790 uint16_t read_reg(void) {
795 *(gpio + 1) = gpfsel1;
796 *(gpio + 2) = gpfsel2;
798 GPIO_CLR = 1 << 6; // delay
803 return (uint16_t)(val >> 8);
807 // Set up a memory regions to access GPIO
811 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
812 printf("can't open /dev/mem \n");
818 NULL, // Any adddress in our space will do
819 BCM2708_PERI_SIZE, // Map length
820 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
821 MAP_SHARED, // Shared with other processes
822 mem_fd, // File to map
823 BCM2708_PERI_BASE // Offset to GPIO peripheral
826 close(mem_fd); // No need to keep mem_fd open after mmap
828 if (gpio_map == MAP_FAILED) {
829 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
833 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
834 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;