2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
26 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
27 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
28 #define BCM2708_PERI_BASE 0x3F000000 // pi3
29 #define BCM2708_PERI_SIZE 0x01000000
30 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
31 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
32 #define GPIO_ADDR 0x200000 /* GPIO controller */
33 #define GPCLK_ADDR 0x101000
34 #define CLK_PASSWD 0x5a000000
35 #define CLK_GP0_CTL 0x070
36 #define CLK_GP0_DIV 0x074
42 #define STATUSREGADDR \
43 GPIO_CLR = 1 << SA0; \
44 GPIO_CLR = 1 << SA1; \
47 GPIO_CLR = 1 << SA0; \
48 GPIO_CLR = 1 << SA1; \
51 GPIO_SET = 1 << SA0; \
52 GPIO_CLR = 1 << SA1; \
55 GPIO_CLR = 1 << SA0; \
56 GPIO_SET = 1 << SA1; \
59 GPIO_SET = 1 << SA0; \
60 GPIO_SET = 1 << SA1; \
63 #define PAGE_SIZE (4 * 1024)
64 #define BLOCK_SIZE (4 * 1024)
66 #define GPIOSET(no, ishigh) \
71 reset |= (1 << (no)); \
74 int fast_base_configured;
75 unsigned int fast_base;
76 #define FAST_SIZE (8 * 1024 * 1024)
78 #define GAYLEBASE 0xD80000
79 #define GAYLESIZE (448 * 1024)
81 #define KICKBASE 0xF80000
82 #define KICKSIZE (512 * 1024)
84 #define AC_BASE 0xE80000
85 #define AC_SIZE (64 * 1024)
87 #define AC_PIC_COUNT 1
88 int ac_current_pic = 0;
93 int gayle_emulation_enabled = 1;
98 volatile unsigned int *gpio;
99 volatile unsigned int *gpclk;
100 volatile unsigned int gpfsel0;
101 volatile unsigned int gpfsel1;
102 volatile unsigned int gpfsel2;
103 volatile unsigned int gpfsel0_o;
104 volatile unsigned int gpfsel1_o;
105 volatile unsigned int gpfsel2_o;
107 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
109 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
110 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
111 #define SET_GPIO_ALT(g, a) \
112 *(gpio + (((g) / 10))) |= \
113 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
116 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
118 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
120 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
122 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
123 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
127 uint32_t read8(uint32_t address);
128 void write8(uint32_t address, uint32_t data);
130 uint32_t read16(uint32_t address);
131 void write16(uint32_t address, uint32_t data);
133 void write32(uint32_t address, uint32_t data);
134 uint32_t read32(uint32_t address);
136 uint16_t read_reg(void);
137 void write_reg(unsigned int value);
139 volatile uint16_t srdata;
140 volatile uint32_t srdata2;
141 volatile uint32_t srdata2_old;
143 unsigned char g_kick[KICKSIZE];
144 unsigned char fast_ram_array[FAST_SIZE]; /* RAM */
145 unsigned char toggle;
146 static volatile unsigned char ovl;
147 static volatile unsigned char maprom;
149 void sigint_handler(int sig_num) {
150 printf("\n Exit Ctrl+C %d\n", sig_num);
154 void *iplThread(void *args) {
155 printf("IPL thread running/n");
158 if (GET_GPIO(1) == 0) {
160 m68k_end_timeslice();
161 //printf("thread!/n");
169 int main(int argc, char *argv[]) {
171 const struct sched_param priority = {99};
173 // Some command line switch stuffles
174 for (g = 1; g < argc; g++) {
175 if (strcmp(argv[g], "--disable-gayle") == 0) {
176 gayle_emulation_enabled = 0;
180 sched_setscheduler(0, SCHED_FIFO, &priority);
181 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
185 signal(SIGINT, sigint_handler);
188 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
190 printf("Enable 200MHz GPCLK0 on GPIO4\n");
192 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
194 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
197 *(gpclk + (CLK_GP0_DIV / 4)) =
198 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
200 *(gpclk + (CLK_GP0_CTL / 4)) =
201 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
203 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
207 SET_GPIO_ALT(4, 0); // gpclk0
217 // set gpio0 (aux0) and gpio1 (aux1) to input
221 // Set GPIO pins 6,7 and 8-23 to output
222 for (g = 6; g <= 23; g++) {
226 printf("Precalculate GPIO8-23 as Output\n");
227 gpfsel0_o = *(gpio); // store gpio ddr
228 printf("gpfsel0: %#x\n", gpfsel0_o);
229 gpfsel1_o = *(gpio + 1); // store gpio ddr
230 printf("gpfsel1: %#x\n", gpfsel1_o);
231 gpfsel2_o = *(gpio + 2); // store gpio ddr
232 printf("gpfsel2: %#x\n", gpfsel2_o);
234 // Set GPIO pins 8-23 to input
235 for (g = 8; g <= 23; g++) {
238 printf("Precalculate GPIO8-23 as Input\n");
239 gpfsel0 = *(gpio); // store gpio ddr
240 printf("gpfsel0: %#x\n", gpfsel0);
241 gpfsel1 = *(gpio + 1); // store gpio ddr
242 printf("gpfsel1: %#x\n", gpfsel1);
243 gpfsel2 = *(gpio + 2); // store gpio ddr
244 printf("gpfsel2: %#x\n", gpfsel2);
253 // reset cpld statemachine first
261 // load kick.rom if present
264 fd = open("kick.rom", O_RDONLY);
266 printf("Failed loading kick.rom, using motherboard kickstart\n");
269 int size = (int)lseek(fd, 0, SEEK_END);
270 if (size == 0x40000) {
271 lseek(fd, 0, SEEK_SET);
272 read(fd, &g_kick, size);
273 lseek(fd, 0, SEEK_SET);
274 read(fd, &g_kick[0x40000], size);
276 lseek(fd, 0, SEEK_SET);
277 read(fd, &g_kick, size);
279 printf("Loaded kick.rom with size %d kib\n", size / 1024);
282 // reset amiga and statemachine
285 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
286 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
291 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
295 m68k_set_reg(M68K_REG_PC, 0xF80002);
297 m68k_set_reg(M68K_REG_PC, 0x0);
303 err = pthread_create(&id, NULL, &iplThread, NULL);
305 printf("\ncan't create IPL thread :[%s]", strerror(err));
307 printf("\n IPL Thread created successfully\n");
316 m68k_set_irq((srdata >> 13) & 0xff);
323 if (GET_GPIO(1) == 0) {
325 m68k_set_irq((srdata >> 13) & 0xff);
327 if (CheckIrq() == 1) {
328 write16(0xdff09c, 0x8008);
338 void cpu_pulse_reset(void) {
340 // printf("Status Reg%x\n",read_reg());
343 // printf("Status Reg%x\n",read_reg());
346 int cpu_irq_ack(int level) {
347 printf("cpu irq ack\n");
351 static unsigned char ac_fast_ram_rom[] = {
352 0xe, 0x0, // 00/02, link into memory free list, 8 MB
353 0x6, 0x9, // 04/06, product id
354 0x8, 0x0, // 08/0a, preference to 8 MB space
355 0x0, 0x0, // 0c/0e, reserved
356 0x0, 0x7, 0xd, 0xb, // 10/12/14/16, mfg id
357 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x2, 0x0 // 18/.../26, serial
360 static unsigned int ac_fast_ram_read_memory_8(unsigned int address) {
361 unsigned char val = 0;
362 if ((address & 1) == 0 && (address / 2) < sizeof(ac_fast_ram_rom))
363 val = ac_fast_ram_rom[address / 2];
365 if (address != 0 && address != 2 && address != 40 && address != 42)
367 return (unsigned int)val;
370 static void ac_fast_ram_write_memory_8(unsigned int address, unsigned int value) {
373 if (address == 0x4a) { // base[19:16]
374 fast_base = (value & 0xf0) << (16 - 4);
375 } else if (address == 0x48) { // base[23:20]
376 fast_base &= 0xff0fffff;
377 fast_base |= (value & 0xf0) << (20 - 4);
378 fast_base_configured = 1;
380 } else if (address == 0x4c) { // shut up
386 if (ac_current_pic == AC_PIC_COUNT)
391 static unsigned int autoconfig_read_memory_8(unsigned int address) {
392 if (ac_current_pic == 0) {
393 return ac_fast_ram_read_memory_8(address);
397 static void autoconfig_write_memory_8(unsigned int address, unsigned int value) {
398 if (ac_current_pic == 0) {
399 return ac_fast_ram_write_memory_8(address, value);
403 unsigned int m68k_read_memory_8(unsigned int address) {
404 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
405 return fast_ram_array[address - fast_base];
408 if (!ac_done && address >= AC_BASE && address < AC_BASE + AC_SIZE) {
409 return autoconfig_read_memory_8(address - AC_BASE);
413 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
414 return g_kick[address - KICKBASE];
418 if (gayle_emulation_enabled) {
419 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
420 return readGayleB(address);
425 // if (address < 0xffffff) {
426 return read8((uint32_t)address);
432 unsigned int m68k_read_memory_16(unsigned int address) {
433 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
434 return be16toh(*(uint16_t *)&fast_ram_array[address - fast_base]);
438 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
439 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
443 if (gayle_emulation_enabled) {
444 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
445 return readGayle(address);
449 // if (address < 0xffffff) {
451 return (unsigned int)read16((uint32_t)address);
457 unsigned int m68k_read_memory_32(unsigned int address) {
458 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
459 return be32toh(*(uint32_t *)&fast_ram_array[address - fast_base]);
463 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
464 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
468 if (gayle_emulation_enabled) {
469 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
470 return readGayleL(address);
474 // if (address < 0xffffff) {
476 uint16_t a = read16(address);
477 uint16_t b = read16(address + 2);
478 return (a << 16) | b;
484 void m68k_write_memory_8(unsigned int address, unsigned int value) {
485 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
486 fast_ram_array[address - fast_base] = value;
490 if (!ac_done && address >= AC_BASE && address < AC_BASE + AC_SIZE) {
491 return autoconfig_write_memory_8(address - AC_BASE, value);
494 if (gayle_emulation_enabled) {
495 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
496 writeGayleB(address, value);
501 if (address == 0xbfe001) {
502 ovl = (value & (1 << 0));
503 printf("OVL:%x\n", ovl);
506 // if (address < 0xffffff) {
508 write8((uint32_t)address, value);
515 void m68k_write_memory_16(unsigned int address, unsigned int value) {
516 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
517 *(uint16_t *)&fast_ram_array[address - fast_base] = htobe16(value);
521 if (gayle_emulation_enabled) {
522 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
523 writeGayle(address, value);
528 // if (address < 0xffffff) {
530 write16((uint32_t)address, value);
536 void m68k_write_memory_32(unsigned int address, unsigned int value) {
537 if (fast_base_configured && address >= fast_base && address < fast_base + FAST_SIZE) {
538 *(uint32_t *)&fast_ram_array[address - fast_base] = htobe32(value);
542 if (gayle_emulation_enabled) {
543 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
544 writeGayleL(address, value);
548 // if (address < 0xffffff) {
550 write16(address, value >> 16);
551 write16(address + 2, value);
558 void write16(uint32_t address, uint32_t data) {
559 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
560 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
561 uint32_t addr_l_s = (address >> 16) << 8;
562 uint32_t addr_l_r = (~address >> 16) << 8;
563 uint32_t data_s = (data & 0x0000ffff) << 8;
564 uint32_t data_r = (~data & 0x0000ffff) << 8;
566 // asm volatile ("dmb" ::: "memory");
569 *(gpio + 1) = gpfsel1_o;
570 *(gpio + 2) = gpfsel2_o;
572 *(gpio + 7) = addr_h_s;
573 *(gpio + 10) = addr_h_r;
577 *(gpio + 7) = addr_l_s;
578 *(gpio + 10) = addr_l_r;
583 *(gpio + 7) = data_s;
584 *(gpio + 10) = data_r;
589 *(gpio + 1) = gpfsel1;
590 *(gpio + 2) = gpfsel2;
591 while ((GET_GPIO(0)))
593 // asm volatile ("dmb" ::: "memory");
596 void write8(uint32_t address, uint32_t data) {
597 if ((address & 1) == 0)
598 data = data + (data << 8); // EVEN, A0=0,UDS
600 data = data & 0xff; // ODD , A0=1,LDS
601 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
602 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
603 uint32_t addr_l_s = (address >> 16) << 8;
604 uint32_t addr_l_r = (~address >> 16) << 8;
605 uint32_t data_s = (data & 0x0000ffff) << 8;
606 uint32_t data_r = (~data & 0x0000ffff) << 8;
608 // asm volatile ("dmb" ::: "memory");
611 *(gpio + 1) = gpfsel1_o;
612 *(gpio + 2) = gpfsel2_o;
614 *(gpio + 7) = addr_h_s;
615 *(gpio + 10) = addr_h_r;
619 *(gpio + 7) = addr_l_s;
620 *(gpio + 10) = addr_l_r;
625 *(gpio + 7) = data_s;
626 *(gpio + 10) = data_r;
631 *(gpio + 1) = gpfsel1;
632 *(gpio + 2) = gpfsel2;
633 while ((GET_GPIO(0)))
635 // asm volatile ("dmb" ::: "memory");
638 uint32_t read16(uint32_t address) {
640 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
641 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
642 uint32_t addr_l_s = (address >> 16) << 8;
643 uint32_t addr_l_r = (~address >> 16) << 8;
645 // asm volatile ("dmb" ::: "memory");
648 *(gpio + 1) = gpfsel1_o;
649 *(gpio + 2) = gpfsel2_o;
651 *(gpio + 7) = addr_h_s;
652 *(gpio + 10) = addr_h_r;
656 *(gpio + 7) = addr_l_s;
657 *(gpio + 10) = addr_l_r;
663 *(gpio + 1) = gpfsel1;
664 *(gpio + 2) = gpfsel2;
666 while (!(GET_GPIO(0)))
671 // asm volatile ("dmb" ::: "memory");
672 return (val >> 8) & 0xffff;
675 uint32_t read8(uint32_t address) {
677 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
678 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
679 uint32_t addr_l_s = (address >> 16) << 8;
680 uint32_t addr_l_r = (~address >> 16) << 8;
682 // asm volatile ("dmb" ::: "memory");
685 *(gpio + 1) = gpfsel1_o;
686 *(gpio + 2) = gpfsel2_o;
688 *(gpio + 7) = addr_h_s;
689 *(gpio + 10) = addr_h_r;
693 *(gpio + 7) = addr_l_s;
694 *(gpio + 10) = addr_l_r;
700 *(gpio + 1) = gpfsel1;
701 *(gpio + 2) = gpfsel2;
704 while (!(GET_GPIO(0)))
709 // asm volatile ("dmb" ::: "memory");
711 val = (val >> 8) & 0xffff;
712 if ((address & 1) == 0)
713 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
715 return val & 0xff; // ODD , A0=1,LDS
718 /******************************************************/
720 void write_reg(unsigned int value) {
723 *(gpio + 1) = gpfsel1_o;
724 *(gpio + 2) = gpfsel2_o;
725 *(gpio + 7) = (value & 0xffff) << 8;
726 *(gpio + 10) = (~value & 0xffff) << 8;
728 GPIO_CLR = 1 << 7; // delay
733 *(gpio + 1) = gpfsel1;
734 *(gpio + 2) = gpfsel2;
737 uint16_t read_reg(void) {
742 *(gpio + 1) = gpfsel1;
743 *(gpio + 2) = gpfsel2;
745 GPIO_CLR = 1 << 6; // delay
750 return (uint16_t)(val >> 8);
754 // Set up a memory regions to access GPIO
758 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
759 printf("can't open /dev/mem \n");
765 NULL, // Any adddress in our space will do
766 BCM2708_PERI_SIZE, // Map length
767 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
768 MAP_SHARED, // Shared with other processes
769 mem_fd, // File to map
770 BCM2708_PERI_BASE // Offset to GPIO peripheral
773 close(mem_fd); // No need to keep mem_fd open after mmap
775 if (gpio_map == MAP_FAILED) {
776 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
780 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
781 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;