20 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
21 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
22 #define BCM2708_PERI_BASE 0x3F000000 //pi3
23 #define BCM2708_PERI_SIZE 0x01000000
24 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
25 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
26 #define GPIO_ADDR 0x200000 /* GPIO controller */
27 #define GPCLK_ADDR 0x101000
28 #define CLK_PASSWD 0x5a000000
29 #define CLK_GP0_CTL 0x070
30 #define CLK_GP0_DIV 0x074
36 #define STATUSREGADDR GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_SET = 1<<SA2;
37 #define W16 GPIO_CLR = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
38 #define R16 GPIO_SET = 1<<SA0;GPIO_CLR = 1<<SA1;GPIO_CLR = 1<<SA2;
39 #define W8 GPIO_CLR = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
40 #define R8 GPIO_SET = 1<<SA0;GPIO_SET = 1<<SA1;GPIO_CLR = 1<<SA2;
42 #define PAGE_SIZE (4*1024)
43 #define BLOCK_SIZE (4*1024)
45 #define GPIOSET(no, ishigh) \
50 reset |= (1 << (no)); \
54 #define FASTBASE 0x07FFFFFF
55 #define FASTSIZE 0xFFFFFFF
56 #define GAYLEBASE 0xD80000 //D7FFFF
57 #define GAYLESIZE 0x6FFFF
59 #define KICKBASE 0xF80000
60 #define KICKSIZE 0x7FFFF
68 volatile unsigned int *gpio;
69 volatile unsigned int *gpclk;
70 volatile unsigned int gpfsel0;
71 volatile unsigned int gpfsel1;
72 volatile unsigned int gpfsel2;
73 volatile unsigned int gpfsel0_o;
74 volatile unsigned int gpfsel1_o;
75 volatile unsigned int gpfsel2_o;
77 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y)
78 #define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
79 #define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3))
80 #define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
82 #define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0
83 #define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0
85 #define GET_GPIO(g) (*(gpio+13)&(1<<g)) // 0 if LOW, (1<<g) if HIGH
87 #define GPIO_PULL *(gpio+37) // Pull up/pull down
88 #define GPIO_PULLCLK0 *(gpio+38) // Pull up/pull down clock
93 uint32_t read8(uint32_t address);
94 void write8(uint32_t address, uint32_t data);
96 uint32_t read16(uint32_t address);
97 void write16(uint32_t address, uint32_t data);
99 void write32(uint32_t address, uint32_t data);
100 uint32_t read32(uint32_t address);
102 uint16_t read_reg(void);
103 void write_reg(unsigned int value);
105 volatile uint16_t srdata;
106 volatile uint32_t srdata2;
107 volatile uint32_t srdata2_old;
110 unsigned char g_kick[524288];
111 unsigned char g_ram[FASTSIZE+1]; /* RAM */
112 unsigned char toggle;
113 static volatile unsigned char ovl;
114 static volatile unsigned char maprom;
117 /* Signal Handler for SIGINT */
118 void sigint_handler(int sig_num)
120 /* Reset handler to catch SIGINT next time.
121 Refer http://en.cppreference.com/w/c/program/signal */
122 printf("\n User provided signal handler for Ctrl+C \n");
124 /* Do a graceful cleanup of the program like: free memory/resources/etc and exit */
129 void* iplThread(void *args){
132 //srdata2_old = read_reg();
136 //printf("thread!/n");
137 if (GET_GPIO(1) == 0){
139 if (srdata != srdata2_old){
140 srdata2 = ((srdata >> 13)&0xff);
141 //printf("STATUS: %d\n", srdata2);
142 srdata2_old = srdata;
143 m68k_set_irq(srdata2);
150 srdata2 = ((srdata >> 13)&0xff);
151 srdata2_old = srdata;
152 m68k_set_irq(srdata2);
155 //printf("STATUS: 0\n");
169 const struct sched_param priority = {99};
171 sched_setscheduler(0, SCHED_RR , &priority);
172 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
177 signal(SIGINT, sigint_handler);
180 //Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending on pi model
181 printf("Enable GPCLK0 on GPIO4\n");
183 *(gpclk+ (CLK_GP0_CTL/4)) = CLK_PASSWD | (1 << 5);
185 while ( (*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7));
187 *(gpclk+(CLK_GP0_DIV/4)) = CLK_PASSWD | (6 << 12); //divider , 6=200MHz on pi3
189 *(gpclk+(CLK_GP0_CTL/4)) = CLK_PASSWD | 5 | (1 << 4); //pll? 6=plld, 5=pllc
191 while (((*(gpclk+(CLK_GP0_CTL/4))) & (1 << 7))== 0);
194 SET_GPIO_ALT(4,0); //gpclk0
204 //set gpio0 (aux0) and gpio1 (aux1) to input
208 // Set GPIO pins 6,7 and 8-23 to output
209 for (g=6; g<=23; g++)
214 printf ("Precalculate GPIO8-23 aus Output\n");
215 gpfsel0_o =*(gpio); //store gpio ddr
216 printf ("gpfsel0: %#x\n", gpfsel0_o);
217 gpfsel1_o =*(gpio+1); //store gpio ddr
218 printf ("gpfsel1: %#x\n", gpfsel1_o);
219 gpfsel2_o =*(gpio+2); //store gpio ddr
220 printf ("gpfsel2: %#x\n", gpfsel2_o);
222 // Set GPIO pins 8-23 to input
223 for (g=8; g<=23; g++)
227 printf ("Precalculate GPIO8-23 as Input\n");
228 gpfsel0 =*(gpio); //store gpio ddr
229 printf ("gpfsel0: %#x\n", gpfsel0);
230 gpfsel1 =*(gpio+1); //store gpio ddr
231 printf ("gpfsel1: %#x\n", gpfsel1);
232 gpfsel2 =*(gpio+2); //store gpio ddr
233 printf ("gpfsel2: %#x\n", gpfsel2);
242 //reset cpld statemachine first
253 fp = fopen("kick.rom", "rb");
256 printf("kick.rom cannot be opened\n");
258 printf("kick.rom found, using that instead of motherboard rom\n");
261 unsigned int reads = fread(&g_kick, sizeof(g_kick), 1, fp);
263 printf("failed loading kick.rom\n");
265 printf("loaded kick.rom\n");
274 fd = open("kick.rom",O_RDONLY);
276 printf("failed loading kick.rom, using motherboard kickstart\n");
279 int size = (int)lseek(fd, 0, SEEK_END);
281 lseek(fd, 0, SEEK_SET);
282 read(fd, &g_kick, size);
283 lseek(fd, 0, SEEK_SET);
284 read(fd, &g_kick[0x40000], size);
286 lseek(fd, 0, SEEK_SET);
287 read(fd, &g_kick, size);
289 printf("loaded kick.rom with size %d kib\n",size/1024);
296 m68k_write_memory_8(0xbfe201,0x0001); //AMIGA OVL
297 m68k_write_memory_8(0xbfe001,0x0001); //AMIGA OVL high (ROM@0x0)
303 m68k_set_cpu_type(M68K_CPU_TYPE_68030);
307 m68k_set_reg(M68K_REG_PC, 0xF80002);
309 m68k_set_reg(M68K_REG_PC, 0x0);
315 //err = pthread_create(&id, NULL, &iplThread, NULL);
317 printf("\ncan't create IPL thread :[%s]", strerror(err));
319 printf("\n IPL Thread created successfully\n");
326 if (GET_GPIO(1) == 0){
328 m68k_set_irq((srdata >> 13)&0xff);
339 void cpu_pulse_reset(void){
342 printf("Status Reg%x\n",read_reg());
345 printf("Status Reg%x\n",read_reg());
351 int cpu_irq_ack(int level)
353 printf("cpu irq ack\n");
359 unsigned int m68k_read_memory_8(unsigned int address){
362 if(address>FASTBASE && address<FASTBASE + FASTSIZE){
363 // if(address>FASTBASE){
364 return g_ram[address- FASTBASE];
368 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
369 return g_kick[address-KICKBASE];
373 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
374 return readGayleB(address);
377 if (address < 0xffffff){
378 return read8((uint32_t)address);
384 unsigned int m68k_read_memory_16(unsigned int address){
386 if(address>FASTBASE && address<FASTBASE + FASTSIZE){
387 // if(address>FASTBASE){
388 uint16_t value = *(uint16_t*)&g_ram[address- FASTBASE];
389 value = (value << 8) | (value >> 8);
394 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
395 uint16_t value = *(uint16_t*)&g_kick[address-KICKBASE];
396 value = (value << 8) | (value >> 8);
401 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
402 return readGayle(address);
405 if (address < 0xffffff){
406 return (unsigned int)read16((uint32_t)address);
412 unsigned int m68k_read_memory_32(unsigned int address){
414 if(address>FASTBASE && address<FASTBASE + FASTSIZE){
415 // if(address>FASTBASE){
416 uint32_t value = *(uint32_t*)&g_ram[address- FASTBASE];
417 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
418 return value << 16 | value >> 16;
422 if(address>KICKBASE && address<KICKBASE + KICKSIZE){
423 uint32_t value = *(uint32_t*)&g_kick[address-KICKBASE];
424 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
425 return value << 16 | value >> 16;
429 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
430 return readGayleL(address);
433 if (address < 0xffffff){
434 uint16_t a = read16(address);
435 uint16_t b = read16(address+2);
436 return (a << 16) | b;
442 void m68k_write_memory_8(unsigned int address, unsigned int value){
444 if(address>FASTBASE && address<FASTBASE + FASTSIZE){
445 // if(address>FASTBASE){
446 g_ram[address- FASTBASE] = value;
450 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
451 writeGayleB(address, value);
455 if (address == 0xbfe001){
456 ovl = (value & (1<<0));
457 printf("OVL:%x\n", ovl );
461 if (address < 0xffffff){
462 write8((uint32_t)address,value);
469 void m68k_write_memory_16(unsigned int address, unsigned int value){
470 // if (address==0xdff030) printf("%c", value);
472 if(address>FASTBASE && address<FASTBASE + FASTSIZE ){
473 // if(address>FASTBASE){
474 uint16_t* dest = (uint16_t*)&g_ram[address- FASTBASE];
475 value = (value << 8) | (value >> 8);
480 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
481 writeGayle(address,value);
485 if (address < 0xffffff){
486 write16((uint32_t)address,value);
492 void m68k_write_memory_32(unsigned int address, unsigned int value){
494 if(address>FASTBASE && address<FASTBASE + FASTSIZE ){
495 // if(address>FASTBASE){
496 uint32_t* dest = (uint32_t*)&g_ram[address- FASTBASE];
497 value = ((value << 8) & 0xFF00FF00 ) | ((value >> 8) & 0xFF00FF );
498 value = value << 16 | value >> 16;
503 if(address>GAYLEBASE && address<GAYLEBASE + GAYLESIZE){
504 writeGayleL(address, value);
507 if (address < 0xffffff){
508 write16(address , value >> 16);
509 write16(address+2 , value );
516 void write16(uint32_t address, uint32_t data)
518 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
519 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
520 uint32_t addr_l_s = (address >> 16) << 8;
521 uint32_t addr_l_r = (~address >> 16) << 8;
522 uint32_t data_s = (data & 0x0000ffff) << 8;
523 uint32_t data_r = (~data & 0x0000ffff) << 8;
525 // asm volatile ("dmb" ::: "memory");
528 *(gpio + 1) = gpfsel1_o;
529 *(gpio + 2) = gpfsel2_o;
531 *(gpio + 7) = addr_h_s;
532 *(gpio + 10) = addr_h_r;
533 // while ((GET_GPIO(0)));
537 *(gpio + 7) = addr_l_s;
538 *(gpio + 10) = addr_l_r;
543 *(gpio + 7) = data_s;
544 *(gpio + 10) = data_r;
549 *(gpio + 1) = gpfsel1;
550 *(gpio + 2) = gpfsel2;
551 while ((GET_GPIO(0)));
552 // asm volatile ("dmb" ::: "memory");
556 void write8(uint32_t address, uint32_t data)
559 if ((address & 1) == 0)
560 data = data + (data << 8); //EVEN, A0=0,UDS
561 else data = data & 0xff ; //ODD , A0=1,LDS
562 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
563 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
564 uint32_t addr_l_s = (address >> 16) << 8;
565 uint32_t addr_l_r = (~address >> 16) << 8;
566 uint32_t data_s = (data & 0x0000ffff) << 8;
567 uint32_t data_r = (~data & 0x0000ffff) << 8;
569 // asm volatile ("dmb" ::: "memory");
572 *(gpio + 1) = gpfsel1_o;
573 *(gpio + 2) = gpfsel2_o;
575 *(gpio + 7) = addr_h_s;
576 *(gpio + 10) = addr_h_r;
577 //while ((GET_GPIO(0)));
581 *(gpio + 7) = addr_l_s;
582 *(gpio + 10) = addr_l_r;
587 *(gpio + 7) = data_s;
588 *(gpio + 10) = data_r;
593 *(gpio + 1) = gpfsel1;
594 *(gpio + 2) = gpfsel2;
595 while ((GET_GPIO(0)));
596 // asm volatile ("dmb" ::: "memory");
597 // GPIO_SET = 1 << 7;
601 uint32_t read16(uint32_t address)
604 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
605 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
606 uint32_t addr_l_s = (address >> 16) << 8;
607 uint32_t addr_l_r = (~address >> 16) << 8;
609 // asm volatile ("dmb" ::: "memory");
613 *(gpio + 1) = gpfsel1_o;
614 *(gpio + 2) = gpfsel2_o;
616 *(gpio + 7) = addr_h_s;
617 *(gpio + 10) = addr_h_r;
618 // while ((GET_GPIO(0)));
622 *(gpio + 7) = addr_l_s;
623 *(gpio + 10) = addr_l_r;
629 *(gpio + 1) = gpfsel1;
630 *(gpio + 2) = gpfsel2;
632 while (!(GET_GPIO(0)));
634 // asm volatile ("nop" ::);
637 // asm volatile ("dmb" ::: "memory");
638 return (val >>8)&0xffff;
642 uint32_t read8(uint32_t address)
645 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
646 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
647 uint32_t addr_l_s = (address >> 16) << 8;
648 uint32_t addr_l_r = (~address >> 16) << 8;
650 // asm volatile ("dmb" ::: "memory");
653 *(gpio + 1) = gpfsel1_o;
654 *(gpio + 2) = gpfsel2_o;
656 *(gpio + 7) = addr_h_s;
657 *(gpio + 10) = addr_h_r;
658 // while ((GET_GPIO(0)));
662 *(gpio + 7) = addr_l_s;
663 *(gpio + 10) = addr_l_r;
669 *(gpio + 1) = gpfsel1;
670 *(gpio + 2) = gpfsel2;
673 while (!(GET_GPIO(0)));
675 // asm volatile ("nop" ::);
678 // asm volatile ("dmb" ::: "memory");
680 val = (val >>8)&0xffff;
681 if ((address & 1) == 0)
682 val = (val >> 8) & 0xff ; //EVEN, A0=0,UDS
684 val = val & 0xff ; //ODD , A0=1,LDS
690 /******************************************************/
692 void write_reg(unsigned int value)
696 *(gpio + 1) = gpfsel1_o;
697 *(gpio + 2) = gpfsel2_o;
698 *(gpio + 7) = (value & 0xffff) << 8;
699 *(gpio + 10) = (~value & 0xffff) << 8;
701 GPIO_CLR = 1 << 7; //delay
706 *(gpio + 1) = gpfsel1;
707 *(gpio + 2) = gpfsel2;
711 uint16_t read_reg(void)
717 *(gpio + 1) = gpfsel1;
718 *(gpio + 2) = gpfsel2;
720 GPIO_CLR = 1 << 6; //delay
725 return (uint16_t)(val >> 8);
730 // Set up a memory regions to access GPIO
735 if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
736 printf("can't open /dev/mem \n");
742 NULL, //Any adddress in our space will do
743 BCM2708_PERI_SIZE, //Map length
744 PROT_READ|PROT_WRITE,// Enable reading & writting to mapped memory
745 MAP_SHARED, //Shared with other processes
746 mem_fd, //File to map
747 BCM2708_PERI_BASE //Offset to GPIO peripheral
750 close(mem_fd); //No need to keep mem_fd open after mmap
752 if (gpio_map == MAP_FAILED) {
753 printf("gpio mmap error %d\n", (int)gpio_map);//errno also set!
757 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR/4;
758 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR/4;