2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
26 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
27 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
28 #define BCM2708_PERI_BASE 0x3F000000 // pi3
29 #define BCM2708_PERI_SIZE 0x01000000
30 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
31 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
32 #define GPIO_ADDR 0x200000 /* GPIO controller */
33 #define GPCLK_ADDR 0x101000
34 #define CLK_PASSWD 0x5a000000
35 #define CLK_GP0_CTL 0x070
36 #define CLK_GP0_DIV 0x074
42 #define STATUSREGADDR \
43 GPIO_CLR = 1 << SA0; \
44 GPIO_CLR = 1 << SA1; \
47 GPIO_CLR = 1 << SA0; \
48 GPIO_CLR = 1 << SA1; \
51 GPIO_SET = 1 << SA0; \
52 GPIO_CLR = 1 << SA1; \
55 GPIO_CLR = 1 << SA0; \
56 GPIO_SET = 1 << SA1; \
59 GPIO_SET = 1 << SA0; \
60 GPIO_SET = 1 << SA1; \
63 #define PAGE_SIZE (4 * 1024)
64 #define BLOCK_SIZE (4 * 1024)
66 #define GPIOSET(no, ishigh) \
71 reset |= (1 << (no)); \
74 #define FASTBASE 0x08000000
75 #define FASTSIZE (256 * 1024 * 1024)
77 #define GAYLEBASE 0xD80000
78 #define GAYLESIZE (448 * 1024)
80 #define KICKBASE 0xF80000
81 #define KICKSIZE (512 * 1024)
85 int gayle_emulation_enabled = 1;
90 volatile unsigned int *gpio;
91 volatile unsigned int *gpclk;
92 volatile unsigned int gpfsel0;
93 volatile unsigned int gpfsel1;
94 volatile unsigned int gpfsel2;
95 volatile unsigned int gpfsel0_o;
96 volatile unsigned int gpfsel1_o;
97 volatile unsigned int gpfsel2_o;
99 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
101 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
102 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
103 #define SET_GPIO_ALT(g, a) \
104 *(gpio + (((g) / 10))) |= \
105 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
108 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
110 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
112 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
114 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
115 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
119 uint32_t read8(uint32_t address);
120 void write8(uint32_t address, uint32_t data);
122 uint32_t read16(uint32_t address);
123 void write16(uint32_t address, uint32_t data);
125 void write32(uint32_t address, uint32_t data);
126 uint32_t read32(uint32_t address);
128 uint16_t read_reg(void);
129 void write_reg(unsigned int value);
131 volatile uint16_t srdata;
132 volatile uint32_t srdata2;
133 volatile uint32_t srdata2_old;
135 unsigned char g_kick[KICKSIZE];
136 unsigned char g_ram[FASTSIZE]; /* RAM */
137 unsigned char toggle;
138 static volatile unsigned char ovl;
139 static volatile unsigned char maprom;
141 void sigint_handler(int sig_num) {
142 printf("\n Exit Ctrl+C %d\n", sig_num);
146 void *iplThread(void *args) {
147 printf("IPL thread running/n");
150 if (GET_GPIO(1) == 0) {
152 m68k_end_timeslice();
153 //printf("thread!/n");
161 int main(int argc, char *argv[]) {
163 const struct sched_param priority = {99};
165 // Some command line switch stuffles
166 for (g = 1; g < argc; g++) {
167 if (strcmp(argv[g], "--disable-gayle") == 0) {
168 gayle_emulation_enabled = 0;
172 sched_setscheduler(0, SCHED_FIFO, &priority);
173 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
177 signal(SIGINT, sigint_handler);
180 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
182 printf("Enable 200MHz GPCLK0 on GPIO4\n");
184 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
186 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
189 *(gpclk + (CLK_GP0_DIV / 4)) =
190 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
192 *(gpclk + (CLK_GP0_CTL / 4)) =
193 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
195 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
199 SET_GPIO_ALT(4, 0); // gpclk0
209 // set gpio0 (aux0) and gpio1 (aux1) to input
213 // Set GPIO pins 6,7 and 8-23 to output
214 for (g = 6; g <= 23; g++) {
218 printf("Precalculate GPIO8-23 as Output\n");
219 gpfsel0_o = *(gpio); // store gpio ddr
220 printf("gpfsel0: %#x\n", gpfsel0_o);
221 gpfsel1_o = *(gpio + 1); // store gpio ddr
222 printf("gpfsel1: %#x\n", gpfsel1_o);
223 gpfsel2_o = *(gpio + 2); // store gpio ddr
224 printf("gpfsel2: %#x\n", gpfsel2_o);
226 // Set GPIO pins 8-23 to input
227 for (g = 8; g <= 23; g++) {
230 printf("Precalculate GPIO8-23 as Input\n");
231 gpfsel0 = *(gpio); // store gpio ddr
232 printf("gpfsel0: %#x\n", gpfsel0);
233 gpfsel1 = *(gpio + 1); // store gpio ddr
234 printf("gpfsel1: %#x\n", gpfsel1);
235 gpfsel2 = *(gpio + 2); // store gpio ddr
236 printf("gpfsel2: %#x\n", gpfsel2);
245 // reset cpld statemachine first
253 // load kick.rom if present
256 fd = open("kick.rom", O_RDONLY);
258 printf("Failed loading kick.rom, using motherboard kickstart\n");
261 int size = (int)lseek(fd, 0, SEEK_END);
262 if (size == 0x40000) {
263 lseek(fd, 0, SEEK_SET);
264 read(fd, &g_kick, size);
265 lseek(fd, 0, SEEK_SET);
266 read(fd, &g_kick[0x40000], size);
268 lseek(fd, 0, SEEK_SET);
269 read(fd, &g_kick, size);
271 printf("Loaded kick.rom with size %d kib\n", size / 1024);
274 // reset amiga and statemachine
277 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
278 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
283 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
287 m68k_set_reg(M68K_REG_PC, 0xF80002);
289 m68k_set_reg(M68K_REG_PC, 0x0);
295 err = pthread_create(&id, NULL, &iplThread, NULL);
297 printf("\ncan't create IPL thread :[%s]", strerror(err));
299 printf("\n IPL Thread created successfully\n");
308 m68k_set_irq((srdata >> 13) & 0xff);
315 if (GET_GPIO(1) == 0) {
317 m68k_set_irq((srdata >> 13) & 0xff);
319 if (CheckIrq() == 1) {
320 write16(0xdff09c, 0x8008);
330 void cpu_pulse_reset(void) {
332 // printf("Status Reg%x\n",read_reg());
335 // printf("Status Reg%x\n",read_reg());
338 int cpu_irq_ack(int level) {
339 printf("cpu irq ack\n");
343 unsigned int m68k_read_memory_8(unsigned int address) {
344 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
345 return g_ram[address - FASTBASE];
349 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
350 return g_kick[address - KICKBASE];
354 if (gayle_emulation_enabled) {
355 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
356 return readGayleB(address);
361 // if (address < 0xffffff) {
362 return read8((uint32_t)address);
368 unsigned int m68k_read_memory_16(unsigned int address) {
369 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
370 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
374 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
375 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
379 if (gayle_emulation_enabled) {
380 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
381 return readGayle(address);
385 // if (address < 0xffffff) {
387 return (unsigned int)read16((uint32_t)address);
393 unsigned int m68k_read_memory_32(unsigned int address) {
394 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
395 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
399 if (address >= KICKBASE && address < KICKBASE + KICKSIZE) {
400 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
404 if (gayle_emulation_enabled) {
405 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
406 return readGayleL(address);
410 // if (address < 0xffffff) {
412 uint16_t a = read16(address);
413 uint16_t b = read16(address + 2);
414 return (a << 16) | b;
420 void m68k_write_memory_8(unsigned int address, unsigned int value) {
421 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
422 g_ram[address - FASTBASE] = value;
426 if (gayle_emulation_enabled) {
427 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
428 writeGayleB(address, value);
433 if (address == 0xbfe001) {
434 ovl = (value & (1 << 0));
435 printf("OVL:%x\n", ovl);
438 // if (address < 0xffffff) {
440 write8((uint32_t)address, value);
447 void m68k_write_memory_16(unsigned int address, unsigned int value) {
448 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
449 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
453 if (gayle_emulation_enabled) {
454 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
455 writeGayle(address, value);
460 // if (address < 0xffffff) {
462 write16((uint32_t)address, value);
468 void m68k_write_memory_32(unsigned int address, unsigned int value) {
469 if (address >= FASTBASE && address < FASTBASE + FASTSIZE) {
470 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
474 if (gayle_emulation_enabled) {
475 if (address >= GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
476 writeGayleL(address, value);
480 // if (address < 0xffffff) {
482 write16(address, value >> 16);
483 write16(address + 2, value);
490 void write16(uint32_t address, uint32_t data) {
491 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
492 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
493 uint32_t addr_l_s = (address >> 16) << 8;
494 uint32_t addr_l_r = (~address >> 16) << 8;
495 uint32_t data_s = (data & 0x0000ffff) << 8;
496 uint32_t data_r = (~data & 0x0000ffff) << 8;
498 // asm volatile ("dmb" ::: "memory");
501 *(gpio + 1) = gpfsel1_o;
502 *(gpio + 2) = gpfsel2_o;
504 *(gpio + 7) = addr_h_s;
505 *(gpio + 10) = addr_h_r;
509 *(gpio + 7) = addr_l_s;
510 *(gpio + 10) = addr_l_r;
515 *(gpio + 7) = data_s;
516 *(gpio + 10) = data_r;
521 *(gpio + 1) = gpfsel1;
522 *(gpio + 2) = gpfsel2;
523 while ((GET_GPIO(0)))
525 // asm volatile ("dmb" ::: "memory");
528 void write8(uint32_t address, uint32_t data) {
529 if ((address & 1) == 0)
530 data = data + (data << 8); // EVEN, A0=0,UDS
532 data = data & 0xff; // ODD , A0=1,LDS
533 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
534 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
535 uint32_t addr_l_s = (address >> 16) << 8;
536 uint32_t addr_l_r = (~address >> 16) << 8;
537 uint32_t data_s = (data & 0x0000ffff) << 8;
538 uint32_t data_r = (~data & 0x0000ffff) << 8;
540 // asm volatile ("dmb" ::: "memory");
543 *(gpio + 1) = gpfsel1_o;
544 *(gpio + 2) = gpfsel2_o;
546 *(gpio + 7) = addr_h_s;
547 *(gpio + 10) = addr_h_r;
551 *(gpio + 7) = addr_l_s;
552 *(gpio + 10) = addr_l_r;
557 *(gpio + 7) = data_s;
558 *(gpio + 10) = data_r;
563 *(gpio + 1) = gpfsel1;
564 *(gpio + 2) = gpfsel2;
565 while ((GET_GPIO(0)))
567 // asm volatile ("dmb" ::: "memory");
570 uint32_t read16(uint32_t address) {
572 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
573 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
574 uint32_t addr_l_s = (address >> 16) << 8;
575 uint32_t addr_l_r = (~address >> 16) << 8;
577 // asm volatile ("dmb" ::: "memory");
580 *(gpio + 1) = gpfsel1_o;
581 *(gpio + 2) = gpfsel2_o;
583 *(gpio + 7) = addr_h_s;
584 *(gpio + 10) = addr_h_r;
588 *(gpio + 7) = addr_l_s;
589 *(gpio + 10) = addr_l_r;
595 *(gpio + 1) = gpfsel1;
596 *(gpio + 2) = gpfsel2;
598 while (!(GET_GPIO(0)))
603 // asm volatile ("dmb" ::: "memory");
604 return (val >> 8) & 0xffff;
607 uint32_t read8(uint32_t address) {
609 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
610 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
611 uint32_t addr_l_s = (address >> 16) << 8;
612 uint32_t addr_l_r = (~address >> 16) << 8;
614 // asm volatile ("dmb" ::: "memory");
617 *(gpio + 1) = gpfsel1_o;
618 *(gpio + 2) = gpfsel2_o;
620 *(gpio + 7) = addr_h_s;
621 *(gpio + 10) = addr_h_r;
625 *(gpio + 7) = addr_l_s;
626 *(gpio + 10) = addr_l_r;
632 *(gpio + 1) = gpfsel1;
633 *(gpio + 2) = gpfsel2;
636 while (!(GET_GPIO(0)))
641 // asm volatile ("dmb" ::: "memory");
643 val = (val >> 8) & 0xffff;
644 if ((address & 1) == 0)
645 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
647 return val & 0xff; // ODD , A0=1,LDS
650 /******************************************************/
652 void write_reg(unsigned int value) {
655 *(gpio + 1) = gpfsel1_o;
656 *(gpio + 2) = gpfsel2_o;
657 *(gpio + 7) = (value & 0xffff) << 8;
658 *(gpio + 10) = (~value & 0xffff) << 8;
660 GPIO_CLR = 1 << 7; // delay
665 *(gpio + 1) = gpfsel1;
666 *(gpio + 2) = gpfsel2;
669 uint16_t read_reg(void) {
674 *(gpio + 1) = gpfsel1;
675 *(gpio + 2) = gpfsel2;
677 GPIO_CLR = 1 << 6; // delay
682 return (uint16_t)(val >> 8);
686 // Set up a memory regions to access GPIO
690 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
691 printf("can't open /dev/mem \n");
697 NULL, // Any adddress in our space will do
698 BCM2708_PERI_SIZE, // Map length
699 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
700 MAP_SHARED, // Shared with other processes
701 mem_fd, // File to map
702 BCM2708_PERI_BASE // Offset to GPIO peripheral
705 close(mem_fd); // No need to keep mem_fd open after mmap
707 if (gpio_map == MAP_FAILED) {
708 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
712 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
713 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;