14 #include <sys/types.h>
21 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
22 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
23 #define BCM2708_PERI_BASE 0x3F000000 // pi3
24 #define BCM2708_PERI_SIZE 0x01000000
25 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
26 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
27 #define GPIO_ADDR 0x200000 /* GPIO controller */
28 #define GPCLK_ADDR 0x101000
29 #define CLK_PASSWD 0x5a000000
30 #define CLK_GP0_CTL 0x070
31 #define CLK_GP0_DIV 0x074
37 #define STATUSREGADDR \
38 GPIO_CLR = 1 << SA0; \
39 GPIO_CLR = 1 << SA1; \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_SET = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_CLR = 1 << SA0; \
51 GPIO_SET = 1 << SA1; \
54 GPIO_SET = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 #define PAGE_SIZE (4 * 1024)
59 #define BLOCK_SIZE (4 * 1024)
61 #define GPIOSET(no, ishigh) \
66 reset |= (1 << (no)); \
69 #define FASTBASE 0x07FFFFFF
70 #define FASTSIZE 0xFFFFFFF
71 #define GAYLEBASE 0xD80000 // D7FFFF
72 #define GAYLESIZE 0x6FFFF
74 #define KICKBASE 0xF80000
75 #define KICKSIZE 0x7FFFF
83 volatile unsigned int *gpio;
84 volatile unsigned int *gpclk;
85 volatile unsigned int gpfsel0;
86 volatile unsigned int gpfsel1;
87 volatile unsigned int gpfsel2;
88 volatile unsigned int gpfsel0_o;
89 volatile unsigned int gpfsel1_o;
90 volatile unsigned int gpfsel2_o;
92 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
94 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
95 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
96 #define SET_GPIO_ALT(g, a) \
97 *(gpio + (((g) / 10))) |= \
98 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
101 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
103 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
105 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
107 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
108 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
112 uint32_t read8(uint32_t address);
113 void write8(uint32_t address, uint32_t data);
115 uint32_t read16(uint32_t address);
116 void write16(uint32_t address, uint32_t data);
118 void write32(uint32_t address, uint32_t data);
119 uint32_t read32(uint32_t address);
121 uint16_t read_reg(void);
122 void write_reg(unsigned int value);
124 volatile uint16_t srdata;
125 volatile uint32_t srdata2;
126 volatile uint32_t srdata2_old;
128 unsigned char g_kick[524288];
129 unsigned char g_ram[FASTSIZE + 1]; /* RAM */
130 unsigned char toggle;
131 static volatile unsigned char ovl;
132 static volatile unsigned char maprom;
134 void sigint_handler(int sig_num) {
135 printf("\n Exit Ctrl+C %d\n", sig_num);
139 void *iplThread(void *args) {
149 const struct sched_param priority = {99};
151 sched_setscheduler(0, SCHED_FIFO, &priority);
152 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
156 signal(SIGINT, sigint_handler);
159 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
161 printf("Enable 200MHz GPCLK0 on GPIO4\n");
163 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
165 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
168 *(gpclk + (CLK_GP0_DIV / 4)) =
169 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
171 *(gpclk + (CLK_GP0_CTL / 4)) =
172 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
174 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
178 SET_GPIO_ALT(4, 0); // gpclk0
188 // set gpio0 (aux0) and gpio1 (aux1) to input
192 // Set GPIO pins 6,7 and 8-23 to output
193 for (g = 6; g <= 23; g++) {
197 printf("Precalculate GPIO8-23 as Output\n");
198 gpfsel0_o = *(gpio); // store gpio ddr
199 printf("gpfsel0: %#x\n", gpfsel0_o);
200 gpfsel1_o = *(gpio + 1); // store gpio ddr
201 printf("gpfsel1: %#x\n", gpfsel1_o);
202 gpfsel2_o = *(gpio + 2); // store gpio ddr
203 printf("gpfsel2: %#x\n", gpfsel2_o);
205 // Set GPIO pins 8-23 to input
206 for (g = 8; g <= 23; g++) {
209 printf("Precalculate GPIO8-23 as Input\n");
210 gpfsel0 = *(gpio); // store gpio ddr
211 printf("gpfsel0: %#x\n", gpfsel0);
212 gpfsel1 = *(gpio + 1); // store gpio ddr
213 printf("gpfsel1: %#x\n", gpfsel1);
214 gpfsel2 = *(gpio + 2); // store gpio ddr
215 printf("gpfsel2: %#x\n", gpfsel2);
224 // reset cpld statemachine first
232 // load kick.rom if present
235 fd = open("kick.rom", O_RDONLY);
237 printf("Failed loading kick.rom, using motherboard kickstart\n");
240 int size = (int)lseek(fd, 0, SEEK_END);
241 if (size == 0x40000) {
242 lseek(fd, 0, SEEK_SET);
243 read(fd, &g_kick, size);
244 lseek(fd, 0, SEEK_SET);
245 read(fd, &g_kick[0x40000], size);
247 lseek(fd, 0, SEEK_SET);
248 read(fd, &g_kick, size);
250 printf("Loaded kick.rom with size %d kib\n", size / 1024);
253 // reset amiga and statemachine
256 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
257 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
262 m68k_set_cpu_type(M68K_CPU_TYPE_68040);
266 m68k_set_reg(M68K_REG_PC, 0xF80002);
268 m68k_set_reg(M68K_REG_PC, 0x0);
274 //err = pthread_create(&id, NULL, &iplThread, NULL);
276 printf("\ncan't create IPL thread :[%s]", strerror(err));
278 printf("\n IPL Thread created successfully\n");
285 if (GET_GPIO(1) == 0){
287 m68k_set_irq((srdata >> 13) & 0xff);
289 // if (CheckIrq() == 1)
300 void cpu_pulse_reset(void) {
302 // printf("Status Reg%x\n",read_reg());
305 // printf("Status Reg%x\n",read_reg());
308 int cpu_irq_ack(int level) {
309 printf("cpu irq ack\n");
313 unsigned int m68k_read_memory_8(unsigned int address) {
314 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
315 return g_ram[address - FASTBASE];
319 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
320 return g_kick[address - KICKBASE];
324 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
325 return readGayleB(address);
328 if (address < 0xffffff) {
329 return read8((uint32_t)address);
335 unsigned int m68k_read_memory_16(unsigned int address) {
336 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
337 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
341 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
342 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
346 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
347 return readGayle(address);
350 if (address < 0xffffff) {
351 return (unsigned int)read16((uint32_t)address);
357 unsigned int m68k_read_memory_32(unsigned int address) {
358 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
359 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
363 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
364 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
368 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
369 return readGayleL(address);
372 if (address < 0xffffff) {
373 uint16_t a = read16(address);
374 uint16_t b = read16(address + 2);
375 return (a << 16) | b;
381 void m68k_write_memory_8(unsigned int address, unsigned int value) {
382 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
383 g_ram[address - FASTBASE] = value;
387 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
388 writeGayleB(address, value);
392 if (address == 0xbfe001) {
393 ovl = (value & (1 << 0));
394 printf("OVL:%x\n", ovl);
397 if (address < 0xffffff) {
398 write8((uint32_t)address, value);
405 void m68k_write_memory_16(unsigned int address, unsigned int value) {
406 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
407 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
411 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
412 writeGayle(address, value);
416 if (address < 0xffffff) {
417 write16((uint32_t)address, value);
423 void m68k_write_memory_32(unsigned int address, unsigned int value) {
424 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
425 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
429 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
430 writeGayleL(address, value);
433 if (address < 0xffffff) {
434 write16(address, value >> 16);
435 write16(address + 2, value);
442 void write16(uint32_t address, uint32_t data) {
443 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
444 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
445 uint32_t addr_l_s = (address >> 16) << 8;
446 uint32_t addr_l_r = (~address >> 16) << 8;
447 uint32_t data_s = (data & 0x0000ffff) << 8;
448 uint32_t data_r = (~data & 0x0000ffff) << 8;
450 // asm volatile ("dmb" ::: "memory");
453 *(gpio + 1) = gpfsel1_o;
454 *(gpio + 2) = gpfsel2_o;
456 *(gpio + 7) = addr_h_s;
457 *(gpio + 10) = addr_h_r;
461 *(gpio + 7) = addr_l_s;
462 *(gpio + 10) = addr_l_r;
467 *(gpio + 7) = data_s;
468 *(gpio + 10) = data_r;
473 *(gpio + 1) = gpfsel1;
474 *(gpio + 2) = gpfsel2;
475 while ((GET_GPIO(0)))
477 // asm volatile ("dmb" ::: "memory");
480 void write8(uint32_t address, uint32_t data) {
481 if ((address & 1) == 0)
482 data = data + (data << 8); // EVEN, A0=0,UDS
484 data = data & 0xff; // ODD , A0=1,LDS
485 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
486 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
487 uint32_t addr_l_s = (address >> 16) << 8;
488 uint32_t addr_l_r = (~address >> 16) << 8;
489 uint32_t data_s = (data & 0x0000ffff) << 8;
490 uint32_t data_r = (~data & 0x0000ffff) << 8;
492 // asm volatile ("dmb" ::: "memory");
495 *(gpio + 1) = gpfsel1_o;
496 *(gpio + 2) = gpfsel2_o;
498 *(gpio + 7) = addr_h_s;
499 *(gpio + 10) = addr_h_r;
503 *(gpio + 7) = addr_l_s;
504 *(gpio + 10) = addr_l_r;
509 *(gpio + 7) = data_s;
510 *(gpio + 10) = data_r;
515 *(gpio + 1) = gpfsel1;
516 *(gpio + 2) = gpfsel2;
517 while ((GET_GPIO(0)))
519 // asm volatile ("dmb" ::: "memory");
522 uint32_t read16(uint32_t address) {
524 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
525 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
526 uint32_t addr_l_s = (address >> 16) << 8;
527 uint32_t addr_l_r = (~address >> 16) << 8;
529 // asm volatile ("dmb" ::: "memory");
532 *(gpio + 1) = gpfsel1_o;
533 *(gpio + 2) = gpfsel2_o;
535 *(gpio + 7) = addr_h_s;
536 *(gpio + 10) = addr_h_r;
540 *(gpio + 7) = addr_l_s;
541 *(gpio + 10) = addr_l_r;
547 *(gpio + 1) = gpfsel1;
548 *(gpio + 2) = gpfsel2;
550 while (!(GET_GPIO(0)))
555 // asm volatile ("dmb" ::: "memory");
556 return (val >> 8) & 0xffff;
559 uint32_t read8(uint32_t address) {
561 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
562 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
563 uint32_t addr_l_s = (address >> 16) << 8;
564 uint32_t addr_l_r = (~address >> 16) << 8;
566 // asm volatile ("dmb" ::: "memory");
569 *(gpio + 1) = gpfsel1_o;
570 *(gpio + 2) = gpfsel2_o;
572 *(gpio + 7) = addr_h_s;
573 *(gpio + 10) = addr_h_r;
577 *(gpio + 7) = addr_l_s;
578 *(gpio + 10) = addr_l_r;
584 *(gpio + 1) = gpfsel1;
585 *(gpio + 2) = gpfsel2;
588 while (!(GET_GPIO(0)))
593 // asm volatile ("dmb" ::: "memory");
595 val = (val >> 8) & 0xffff;
596 if ((address & 1) == 0)
597 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
599 return val & 0xff; // ODD , A0=1,LDS
602 /******************************************************/
604 void write_reg(unsigned int value) {
607 *(gpio + 1) = gpfsel1_o;
608 *(gpio + 2) = gpfsel2_o;
609 *(gpio + 7) = (value & 0xffff) << 8;
610 *(gpio + 10) = (~value & 0xffff) << 8;
612 GPIO_CLR = 1 << 7; // delay
617 *(gpio + 1) = gpfsel1;
618 *(gpio + 2) = gpfsel2;
621 uint16_t read_reg(void) {
626 *(gpio + 1) = gpfsel1;
627 *(gpio + 2) = gpfsel2;
629 GPIO_CLR = 1 << 6; // delay
634 return (uint16_t)(val >> 8);
638 // Set up a memory regions to access GPIO
642 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
643 printf("can't open /dev/mem \n");
649 NULL, // Any adddress in our space will do
650 BCM2708_PERI_SIZE, // Map length
651 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
652 MAP_SHARED, // Shared with other processes
653 mem_fd, // File to map
654 BCM2708_PERI_BASE // Offset to GPIO peripheral
657 close(mem_fd); // No need to keep mem_fd open after mmap
659 if (gpio_map == MAP_FAILED) {
660 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
664 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
665 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;