2 Copyright 2020 Claude Schwartz
18 #include <sys/types.h>
25 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
26 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
27 #define BCM2708_PERI_BASE 0x3F000000 // pi3
28 #define BCM2708_PERI_SIZE 0x01000000
29 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
30 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
31 #define GPIO_ADDR 0x200000 /* GPIO controller */
32 #define GPCLK_ADDR 0x101000
33 #define CLK_PASSWD 0x5a000000
34 #define CLK_GP0_CTL 0x070
35 #define CLK_GP0_DIV 0x074
41 #define STATUSREGADDR \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_CLR = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_SET = 1 << SA0; \
51 GPIO_CLR = 1 << SA1; \
54 GPIO_CLR = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 GPIO_SET = 1 << SA0; \
59 GPIO_SET = 1 << SA1; \
62 #define PAGE_SIZE (4 * 1024)
63 #define BLOCK_SIZE (4 * 1024)
65 #define GPIOSET(no, ishigh) \
70 reset |= (1 << (no)); \
73 #define FASTBASE 0x07FFFFFF
74 #define FASTSIZE 0xFFFFFFF
75 #define GAYLEBASE 0xD80000 // D7FFFF
76 #define GAYLESIZE 0x6FFFF
78 #define KICKBASE 0xF80000
79 #define KICKSIZE 0x7FFFF
83 int gayle_emulation_enabled = 1;
88 volatile unsigned int *gpio;
89 volatile unsigned int *gpclk;
90 volatile unsigned int gpfsel0;
91 volatile unsigned int gpfsel1;
92 volatile unsigned int gpfsel2;
93 volatile unsigned int gpfsel0_o;
94 volatile unsigned int gpfsel1_o;
95 volatile unsigned int gpfsel2_o;
97 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
99 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
100 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
101 #define SET_GPIO_ALT(g, a) \
102 *(gpio + (((g) / 10))) |= \
103 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
106 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
108 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
110 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
112 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
113 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
117 uint32_t read8(uint32_t address);
118 void write8(uint32_t address, uint32_t data);
120 uint32_t read16(uint32_t address);
121 void write16(uint32_t address, uint32_t data);
123 void write32(uint32_t address, uint32_t data);
124 uint32_t read32(uint32_t address);
126 uint16_t read_reg(void);
127 void write_reg(unsigned int value);
129 volatile uint16_t srdata;
130 volatile uint32_t srdata2;
131 volatile uint32_t srdata2_old;
133 unsigned char g_kick[524288];
134 unsigned char g_ram[FASTSIZE + 1]; /* RAM */
135 unsigned char toggle;
136 static volatile unsigned char ovl;
137 static volatile unsigned char maprom;
139 void sigint_handler(int sig_num) {
140 printf("\n Exit Ctrl+C %d\n", sig_num);
144 void *iplThread(void *args) {
145 printf("IPL thread running/n");
149 if (GET_GPIO(1) == 0){
151 m68k_end_timeslice();
152 //printf("thread!/n");
161 int main(int argc, char *argv[]) {
163 const struct sched_param priority = {99};
165 // Some command line switch stuffles
166 for (g = 1; g < argc; g++) {
167 if (strcmp(argv[g], "--disable-gayle") == 0) {
168 gayle_emulation_enabled = 0;
172 sched_setscheduler(0, SCHED_FIFO, &priority);
173 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
177 signal(SIGINT, sigint_handler);
180 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
182 printf("Enable 200MHz GPCLK0 on GPIO4\n");
184 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
186 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
189 *(gpclk + (CLK_GP0_DIV / 4)) =
190 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
192 *(gpclk + (CLK_GP0_CTL / 4)) =
193 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
195 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
199 SET_GPIO_ALT(4, 0); // gpclk0
209 // set gpio0 (aux0) and gpio1 (aux1) to input
213 // Set GPIO pins 6,7 and 8-23 to output
214 for (g = 6; g <= 23; g++) {
218 printf("Precalculate GPIO8-23 as Output\n");
219 gpfsel0_o = *(gpio); // store gpio ddr
220 printf("gpfsel0: %#x\n", gpfsel0_o);
221 gpfsel1_o = *(gpio + 1); // store gpio ddr
222 printf("gpfsel1: %#x\n", gpfsel1_o);
223 gpfsel2_o = *(gpio + 2); // store gpio ddr
224 printf("gpfsel2: %#x\n", gpfsel2_o);
226 // Set GPIO pins 8-23 to input
227 for (g = 8; g <= 23; g++) {
230 printf("Precalculate GPIO8-23 as Input\n");
231 gpfsel0 = *(gpio); // store gpio ddr
232 printf("gpfsel0: %#x\n", gpfsel0);
233 gpfsel1 = *(gpio + 1); // store gpio ddr
234 printf("gpfsel1: %#x\n", gpfsel1);
235 gpfsel2 = *(gpio + 2); // store gpio ddr
236 printf("gpfsel2: %#x\n", gpfsel2);
245 // reset cpld statemachine first
253 // load kick.rom if present
256 fd = open("kick.rom", O_RDONLY);
258 printf("Failed loading kick.rom, using motherboard kickstart\n");
261 int size = (int)lseek(fd, 0, SEEK_END);
262 if (size == 0x40000) {
263 lseek(fd, 0, SEEK_SET);
264 read(fd, &g_kick, size);
265 lseek(fd, 0, SEEK_SET);
266 read(fd, &g_kick[0x40000], size);
268 lseek(fd, 0, SEEK_SET);
269 read(fd, &g_kick, size);
271 printf("Loaded kick.rom with size %d kib\n", size / 1024);
274 // reset amiga and statemachine
277 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
278 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
283 m68k_set_cpu_type(M68K_CPU_TYPE_68020);
287 m68k_set_reg(M68K_REG_PC, 0xF80002);
289 m68k_set_reg(M68K_REG_PC, 0x0);
295 err = pthread_create(&id, NULL, &iplThread, NULL);
297 printf("\ncan't create IPL thread :[%s]", strerror(err));
299 printf("\n IPL Thread created successfully\n");
309 m68k_set_irq((srdata >> 13) & 0xff);
317 if (GET_GPIO(1) == 0){
319 m68k_set_irq((srdata >> 13) & 0xff);
321 if (CheckIrq() == 1){
322 write16(0xdff09c, 0x8008);
333 void cpu_pulse_reset(void) {
335 // printf("Status Reg%x\n",read_reg());
338 // printf("Status Reg%x\n",read_reg());
341 int cpu_irq_ack(int level) {
342 printf("cpu irq ack\n");
346 unsigned int m68k_read_memory_8(unsigned int address) {
347 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
348 return g_ram[address - FASTBASE];
352 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
353 return g_kick[address - KICKBASE];
357 if (gayle_emulation_enabled) {
358 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
359 return readGayleB(address);
364 // if (address < 0xffffff) {
365 return read8((uint32_t)address);
371 unsigned int m68k_read_memory_16(unsigned int address) {
372 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
373 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
377 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
378 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
382 if (gayle_emulation_enabled) {
383 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
384 return readGayle(address);
388 // if (address < 0xffffff) {
390 return (unsigned int)read16((uint32_t)address);
396 unsigned int m68k_read_memory_32(unsigned int address) {
397 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
398 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
402 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
403 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
407 if (gayle_emulation_enabled) {
408 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
409 return readGayleL(address);
413 // if (address < 0xffffff) {
415 uint16_t a = read16(address);
416 uint16_t b = read16(address + 2);
417 return (a << 16) | b;
423 void m68k_write_memory_8(unsigned int address, unsigned int value) {
424 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
425 g_ram[address - FASTBASE] = value;
429 if (gayle_emulation_enabled) {
430 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
431 writeGayleB(address, value);
436 if (address == 0xbfe001) {
437 ovl = (value & (1 << 0));
438 printf("OVL:%x\n", ovl);
441 // if (address < 0xffffff) {
443 write8((uint32_t)address, value);
450 void m68k_write_memory_16(unsigned int address, unsigned int value) {
451 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
452 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
456 if (gayle_emulation_enabled) {
457 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
458 writeGayle(address, value);
463 // if (address < 0xffffff) {
465 write16((uint32_t)address, value);
471 void m68k_write_memory_32(unsigned int address, unsigned int value) {
472 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
473 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
477 if (gayle_emulation_enabled) {
478 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
479 writeGayleL(address, value);
483 // if (address < 0xffffff) {
485 write16(address, value >> 16);
486 write16(address + 2, value);
493 void write16(uint32_t address, uint32_t data) {
494 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
495 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
496 uint32_t addr_l_s = (address >> 16) << 8;
497 uint32_t addr_l_r = (~address >> 16) << 8;
498 uint32_t data_s = (data & 0x0000ffff) << 8;
499 uint32_t data_r = (~data & 0x0000ffff) << 8;
501 // asm volatile ("dmb" ::: "memory");
504 *(gpio + 1) = gpfsel1_o;
505 *(gpio + 2) = gpfsel2_o;
507 *(gpio + 7) = addr_h_s;
508 *(gpio + 10) = addr_h_r;
512 *(gpio + 7) = addr_l_s;
513 *(gpio + 10) = addr_l_r;
518 *(gpio + 7) = data_s;
519 *(gpio + 10) = data_r;
524 *(gpio + 1) = gpfsel1;
525 *(gpio + 2) = gpfsel2;
526 while ((GET_GPIO(0)))
528 // asm volatile ("dmb" ::: "memory");
531 void write8(uint32_t address, uint32_t data) {
532 if ((address & 1) == 0)
533 data = data + (data << 8); // EVEN, A0=0,UDS
535 data = data & 0xff; // ODD , A0=1,LDS
536 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
537 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
538 uint32_t addr_l_s = (address >> 16) << 8;
539 uint32_t addr_l_r = (~address >> 16) << 8;
540 uint32_t data_s = (data & 0x0000ffff) << 8;
541 uint32_t data_r = (~data & 0x0000ffff) << 8;
543 // asm volatile ("dmb" ::: "memory");
546 *(gpio + 1) = gpfsel1_o;
547 *(gpio + 2) = gpfsel2_o;
549 *(gpio + 7) = addr_h_s;
550 *(gpio + 10) = addr_h_r;
554 *(gpio + 7) = addr_l_s;
555 *(gpio + 10) = addr_l_r;
560 *(gpio + 7) = data_s;
561 *(gpio + 10) = data_r;
566 *(gpio + 1) = gpfsel1;
567 *(gpio + 2) = gpfsel2;
568 while ((GET_GPIO(0)))
570 // asm volatile ("dmb" ::: "memory");
573 uint32_t read16(uint32_t address) {
575 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
576 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
577 uint32_t addr_l_s = (address >> 16) << 8;
578 uint32_t addr_l_r = (~address >> 16) << 8;
580 // asm volatile ("dmb" ::: "memory");
583 *(gpio + 1) = gpfsel1_o;
584 *(gpio + 2) = gpfsel2_o;
586 *(gpio + 7) = addr_h_s;
587 *(gpio + 10) = addr_h_r;
591 *(gpio + 7) = addr_l_s;
592 *(gpio + 10) = addr_l_r;
598 *(gpio + 1) = gpfsel1;
599 *(gpio + 2) = gpfsel2;
601 while (!(GET_GPIO(0)))
606 // asm volatile ("dmb" ::: "memory");
607 return (val >> 8) & 0xffff;
610 uint32_t read8(uint32_t address) {
612 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
613 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
614 uint32_t addr_l_s = (address >> 16) << 8;
615 uint32_t addr_l_r = (~address >> 16) << 8;
617 // asm volatile ("dmb" ::: "memory");
620 *(gpio + 1) = gpfsel1_o;
621 *(gpio + 2) = gpfsel2_o;
623 *(gpio + 7) = addr_h_s;
624 *(gpio + 10) = addr_h_r;
628 *(gpio + 7) = addr_l_s;
629 *(gpio + 10) = addr_l_r;
635 *(gpio + 1) = gpfsel1;
636 *(gpio + 2) = gpfsel2;
639 while (!(GET_GPIO(0)))
644 // asm volatile ("dmb" ::: "memory");
646 val = (val >> 8) & 0xffff;
647 if ((address & 1) == 0)
648 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
650 return val & 0xff; // ODD , A0=1,LDS
653 /******************************************************/
655 void write_reg(unsigned int value) {
658 *(gpio + 1) = gpfsel1_o;
659 *(gpio + 2) = gpfsel2_o;
660 *(gpio + 7) = (value & 0xffff) << 8;
661 *(gpio + 10) = (~value & 0xffff) << 8;
663 GPIO_CLR = 1 << 7; // delay
668 *(gpio + 1) = gpfsel1;
669 *(gpio + 2) = gpfsel2;
672 uint16_t read_reg(void) {
677 *(gpio + 1) = gpfsel1;
678 *(gpio + 2) = gpfsel2;
680 GPIO_CLR = 1 << 6; // delay
685 return (uint16_t)(val >> 8);
689 // Set up a memory regions to access GPIO
693 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
694 printf("can't open /dev/mem \n");
700 NULL, // Any adddress in our space will do
701 BCM2708_PERI_SIZE, // Map length
702 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
703 MAP_SHARED, // Shared with other processes
704 mem_fd, // File to map
705 BCM2708_PERI_BASE // Offset to GPIO peripheral
708 close(mem_fd); // No need to keep mem_fd open after mmap
710 if (gpio_map == MAP_FAILED) {
711 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
715 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
716 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;