14 #include <sys/types.h>
21 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
22 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
23 #define BCM2708_PERI_BASE 0x3F000000 // pi3
24 #define BCM2708_PERI_SIZE 0x01000000
25 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
26 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
27 #define GPIO_ADDR 0x200000 /* GPIO controller */
28 #define GPCLK_ADDR 0x101000
29 #define CLK_PASSWD 0x5a000000
30 #define CLK_GP0_CTL 0x070
31 #define CLK_GP0_DIV 0x074
37 #define STATUSREGADDR \
38 GPIO_CLR = 1 << SA0; \
39 GPIO_CLR = 1 << SA1; \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_SET = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_CLR = 1 << SA0; \
51 GPIO_SET = 1 << SA1; \
54 GPIO_SET = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 #define PAGE_SIZE (4 * 1024)
59 #define BLOCK_SIZE (4 * 1024)
61 #define GPIOSET(no, ishigh) \
66 reset |= (1 << (no)); \
69 #define FASTBASE 0x07FFFFFF
70 #define FASTSIZE 0xFFFFFFF
71 #define GAYLEBASE 0xD80000 // D7FFFF
72 #define GAYLESIZE 0x6FFFF
74 #define KICKBASE 0xF80000
75 #define KICKSIZE 0x7FFFF
79 int gayle_emulation_enabled = 1;
84 volatile unsigned int *gpio;
85 volatile unsigned int *gpclk;
86 volatile unsigned int gpfsel0;
87 volatile unsigned int gpfsel1;
88 volatile unsigned int gpfsel2;
89 volatile unsigned int gpfsel0_o;
90 volatile unsigned int gpfsel1_o;
91 volatile unsigned int gpfsel2_o;
93 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
95 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
96 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
97 #define SET_GPIO_ALT(g, a) \
98 *(gpio + (((g) / 10))) |= \
99 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
102 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
104 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
106 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
108 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
109 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
113 uint32_t read8(uint32_t address);
114 void write8(uint32_t address, uint32_t data);
116 uint32_t read16(uint32_t address);
117 void write16(uint32_t address, uint32_t data);
119 void write32(uint32_t address, uint32_t data);
120 uint32_t read32(uint32_t address);
122 uint16_t read_reg(void);
123 void write_reg(unsigned int value);
125 volatile uint16_t srdata;
126 volatile uint32_t srdata2;
127 volatile uint32_t srdata2_old;
129 unsigned char g_kick[524288];
130 unsigned char g_ram[FASTSIZE + 1]; /* RAM */
131 unsigned char toggle;
132 static volatile unsigned char ovl;
133 static volatile unsigned char maprom;
135 void sigint_handler(int sig_num) {
136 printf("\n Exit Ctrl+C %d\n", sig_num);
140 void *iplThread(void *args) {
148 int main(int argc, char *argv[]) {
150 const struct sched_param priority = {99};
152 // Some command line switch stuffles
153 for (g = 1; g < argc; g++) {
154 if (strcmp(argv[g], "--disable-gayle") == 0) {
155 gayle_emulation_enabled = 0;
159 sched_setscheduler(0, SCHED_FIFO, &priority);
160 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
164 signal(SIGINT, sigint_handler);
167 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
169 printf("Enable 200MHz GPCLK0 on GPIO4\n");
171 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
173 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
176 *(gpclk + (CLK_GP0_DIV / 4)) =
177 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
179 *(gpclk + (CLK_GP0_CTL / 4)) =
180 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
182 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
186 SET_GPIO_ALT(4, 0); // gpclk0
196 // set gpio0 (aux0) and gpio1 (aux1) to input
200 // Set GPIO pins 6,7 and 8-23 to output
201 for (g = 6; g <= 23; g++) {
205 printf("Precalculate GPIO8-23 as Output\n");
206 gpfsel0_o = *(gpio); // store gpio ddr
207 printf("gpfsel0: %#x\n", gpfsel0_o);
208 gpfsel1_o = *(gpio + 1); // store gpio ddr
209 printf("gpfsel1: %#x\n", gpfsel1_o);
210 gpfsel2_o = *(gpio + 2); // store gpio ddr
211 printf("gpfsel2: %#x\n", gpfsel2_o);
213 // Set GPIO pins 8-23 to input
214 for (g = 8; g <= 23; g++) {
217 printf("Precalculate GPIO8-23 as Input\n");
218 gpfsel0 = *(gpio); // store gpio ddr
219 printf("gpfsel0: %#x\n", gpfsel0);
220 gpfsel1 = *(gpio + 1); // store gpio ddr
221 printf("gpfsel1: %#x\n", gpfsel1);
222 gpfsel2 = *(gpio + 2); // store gpio ddr
223 printf("gpfsel2: %#x\n", gpfsel2);
232 // reset cpld statemachine first
240 // load kick.rom if present
243 fd = open("kick.rom", O_RDONLY);
245 printf("Failed loading kick.rom, using motherboard kickstart\n");
248 int size = (int)lseek(fd, 0, SEEK_END);
249 if (size == 0x40000) {
250 lseek(fd, 0, SEEK_SET);
251 read(fd, &g_kick, size);
252 lseek(fd, 0, SEEK_SET);
253 read(fd, &g_kick[0x40000], size);
255 lseek(fd, 0, SEEK_SET);
256 read(fd, &g_kick, size);
258 printf("Loaded kick.rom with size %d kib\n", size / 1024);
261 // reset amiga and statemachine
264 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
265 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
270 m68k_set_cpu_type(M68K_CPU_TYPE_68030);
274 m68k_set_reg(M68K_REG_PC, 0xF80002);
276 m68k_set_reg(M68K_REG_PC, 0x0);
282 //err = pthread_create(&id, NULL, &iplThread, NULL);
284 printf("\ncan't create IPL thread :[%s]", strerror(err));
286 printf("\n IPL Thread created successfully\n");
292 if (GET_GPIO(1) == 0) {
294 m68k_set_irq((srdata >> 13) & 0xff);
303 void cpu_pulse_reset(void) {
305 // printf("Status Reg%x\n",read_reg());
308 // printf("Status Reg%x\n",read_reg());
311 int cpu_irq_ack(int level) {
312 printf("cpu irq ack\n");
316 unsigned int m68k_read_memory_8(unsigned int address) {
317 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
318 return g_ram[address - FASTBASE];
322 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
323 return g_kick[address - KICKBASE];
327 if (gayle_emulation_enabled) {
328 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
329 return readGayleB(address);
333 if (address < 0xffffff) {
334 return read8((uint32_t)address);
340 unsigned int m68k_read_memory_16(unsigned int address) {
341 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
342 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
346 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
347 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
351 if (gayle_emulation_enabled) {
352 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
353 return readGayle(address);
357 if (address < 0xffffff) {
358 return (unsigned int)read16((uint32_t)address);
364 unsigned int m68k_read_memory_32(unsigned int address) {
365 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
366 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
370 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
371 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
375 if (gayle_emulation_enabled) {
376 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
377 return readGayleL(address);
381 if (address < 0xffffff) {
382 uint16_t a = read16(address);
383 uint16_t b = read16(address + 2);
384 return (a << 16) | b;
390 void m68k_write_memory_8(unsigned int address, unsigned int value) {
391 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
392 g_ram[address - FASTBASE] = value;
396 if (gayle_emulation_enabled) {
397 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
398 writeGayleB(address, value);
403 if (address == 0xbfe001) {
404 ovl = (value & (1 << 0));
405 printf("OVL:%x\n", ovl);
408 if (address < 0xffffff) {
409 write8((uint32_t)address, value);
416 void m68k_write_memory_16(unsigned int address, unsigned int value) {
417 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
418 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
422 if (gayle_emulation_enabled) {
423 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
424 writeGayle(address, value);
429 if (address < 0xffffff) {
430 write16((uint32_t)address, value);
436 void m68k_write_memory_32(unsigned int address, unsigned int value) {
437 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
438 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
442 if (gayle_emulation_enabled) {
443 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
444 writeGayleL(address, value);
448 if (address < 0xffffff) {
449 write16(address, value >> 16);
450 write16(address + 2, value);
457 void write16(uint32_t address, uint32_t data) {
458 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
459 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
460 uint32_t addr_l_s = (address >> 16) << 8;
461 uint32_t addr_l_r = (~address >> 16) << 8;
462 uint32_t data_s = (data & 0x0000ffff) << 8;
463 uint32_t data_r = (~data & 0x0000ffff) << 8;
465 // asm volatile ("dmb" ::: "memory");
466 W16 *(gpio) = gpfsel0_o;
467 *(gpio + 1) = gpfsel1_o;
468 *(gpio + 2) = gpfsel2_o;
470 *(gpio + 7) = addr_h_s;
471 *(gpio + 10) = addr_h_r;
475 *(gpio + 7) = addr_l_s;
476 *(gpio + 10) = addr_l_r;
481 *(gpio + 7) = data_s;
482 *(gpio + 10) = data_r;
487 *(gpio + 1) = gpfsel1;
488 *(gpio + 2) = gpfsel2;
489 while ((GET_GPIO(0)))
491 // asm volatile ("dmb" ::: "memory");
494 void write8(uint32_t address, uint32_t data) {
495 if ((address & 1) == 0)
496 data = data + (data << 8); // EVEN, A0=0,UDS
498 data = data & 0xff; // ODD , A0=1,LDS
499 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
500 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
501 uint32_t addr_l_s = (address >> 16) << 8;
502 uint32_t addr_l_r = (~address >> 16) << 8;
503 uint32_t data_s = (data & 0x0000ffff) << 8;
504 uint32_t data_r = (~data & 0x0000ffff) << 8;
506 // asm volatile ("dmb" ::: "memory");
507 W8 *(gpio) = gpfsel0_o;
508 *(gpio + 1) = gpfsel1_o;
509 *(gpio + 2) = gpfsel2_o;
511 *(gpio + 7) = addr_h_s;
512 *(gpio + 10) = addr_h_r;
516 *(gpio + 7) = addr_l_s;
517 *(gpio + 10) = addr_l_r;
522 *(gpio + 7) = data_s;
523 *(gpio + 10) = data_r;
528 *(gpio + 1) = gpfsel1;
529 *(gpio + 2) = gpfsel2;
530 while ((GET_GPIO(0)))
532 // asm volatile ("dmb" ::: "memory");
535 uint32_t read16(uint32_t address) {
537 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
538 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
539 uint32_t addr_l_s = (address >> 16) << 8;
540 uint32_t addr_l_r = (~address >> 16) << 8;
542 // asm volatile ("dmb" ::: "memory");
546 *(gpio + 1) = gpfsel1_o;
547 *(gpio + 2) = gpfsel2_o;
549 *(gpio + 7) = addr_h_s;
550 *(gpio + 10) = addr_h_r;
554 *(gpio + 7) = addr_l_s;
555 *(gpio + 10) = addr_l_r;
561 *(gpio + 1) = gpfsel1;
562 *(gpio + 2) = gpfsel2;
564 while (!(GET_GPIO(0)))
569 // asm volatile ("dmb" ::: "memory");
570 return (val >> 8) & 0xffff;
573 uint32_t read8(uint32_t address) {
575 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
576 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
577 uint32_t addr_l_s = (address >> 16) << 8;
578 uint32_t addr_l_r = (~address >> 16) << 8;
580 // asm volatile ("dmb" ::: "memory");
581 R8 *(gpio) = gpfsel0_o;
582 *(gpio + 1) = gpfsel1_o;
583 *(gpio + 2) = gpfsel2_o;
585 *(gpio + 7) = addr_h_s;
586 *(gpio + 10) = addr_h_r;
590 *(gpio + 7) = addr_l_s;
591 *(gpio + 10) = addr_l_r;
597 *(gpio + 1) = gpfsel1;
598 *(gpio + 2) = gpfsel2;
601 while (!(GET_GPIO(0)))
606 // asm volatile ("dmb" ::: "memory");
608 val = (val >> 8) & 0xffff;
609 if ((address & 1) == 0)
610 val = (val >> 8) & 0xff; // EVEN, A0=0,UDS
612 val = val & 0xff; // ODD , A0=1,LDS
616 /******************************************************/
618 void write_reg(unsigned int value) {
621 *(gpio + 1) = gpfsel1_o;
622 *(gpio + 2) = gpfsel2_o;
623 *(gpio + 7) = (value & 0xffff) << 8;
624 *(gpio + 10) = (~value & 0xffff) << 8;
626 GPIO_CLR = 1 << 7; // delay
631 *(gpio + 1) = gpfsel1;
632 *(gpio + 2) = gpfsel2;
635 uint16_t read_reg(void) {
640 *(gpio + 1) = gpfsel1;
641 *(gpio + 2) = gpfsel2;
643 GPIO_CLR = 1 << 6; // delay
648 return (uint16_t)(val >> 8);
652 // Set up a memory regions to access GPIO
656 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
657 printf("can't open /dev/mem \n");
663 NULL, // Any adddress in our space will do
664 BCM2708_PERI_SIZE, // Map length
665 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
666 MAP_SHARED, // Shared with other processes
667 mem_fd, // File to map
668 BCM2708_PERI_BASE // Offset to GPIO peripheral
671 close(mem_fd); // No need to keep mem_fd open after mmap
673 if (gpio_map == MAP_FAILED) {
674 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
678 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
679 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;