14 #include <sys/types.h>
21 //#define BCM2708_PERI_BASE 0x20000000 //pi0-1
22 //#define BCM2708_PERI_BASE 0xFE000000 //pi4
23 #define BCM2708_PERI_BASE 0x3F000000 // pi3
24 #define BCM2708_PERI_SIZE 0x01000000
25 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */
26 #define GPCLK_BASE (BCM2708_PERI_BASE + 0x101000)
27 #define GPIO_ADDR 0x200000 /* GPIO controller */
28 #define GPCLK_ADDR 0x101000
29 #define CLK_PASSWD 0x5a000000
30 #define CLK_GP0_CTL 0x070
31 #define CLK_GP0_DIV 0x074
37 #define STATUSREGADDR \
38 GPIO_CLR = 1 << SA0; \
39 GPIO_CLR = 1 << SA1; \
42 GPIO_CLR = 1 << SA0; \
43 GPIO_CLR = 1 << SA1; \
46 GPIO_SET = 1 << SA0; \
47 GPIO_CLR = 1 << SA1; \
50 GPIO_CLR = 1 << SA0; \
51 GPIO_SET = 1 << SA1; \
54 GPIO_SET = 1 << SA0; \
55 GPIO_SET = 1 << SA1; \
58 #define PAGE_SIZE (4 * 1024)
59 #define BLOCK_SIZE (4 * 1024)
61 #define GPIOSET(no, ishigh) \
66 reset |= (1 << (no)); \
69 #define FASTBASE 0x07FFFFFF
70 #define FASTSIZE 0xFFFFFFF
71 #define GAYLEBASE 0xD80000 // D7FFFF
72 #define GAYLESIZE 0x6FFFF
74 #define KICKBASE 0xF80000
75 #define KICKSIZE 0x7FFFF
79 int gayle_emulation_enabled = 1;
84 volatile unsigned int *gpio;
85 volatile unsigned int *gpclk;
86 volatile unsigned int gpfsel0;
87 volatile unsigned int gpfsel1;
88 volatile unsigned int gpfsel2;
89 volatile unsigned int gpfsel0_o;
90 volatile unsigned int gpfsel1_o;
91 volatile unsigned int gpfsel2_o;
93 // GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or
95 #define INP_GPIO(g) *(gpio + ((g) / 10)) &= ~(7 << (((g) % 10) * 3))
96 #define OUT_GPIO(g) *(gpio + ((g) / 10)) |= (1 << (((g) % 10) * 3))
97 #define SET_GPIO_ALT(g, a) \
98 *(gpio + (((g) / 10))) |= \
99 (((a) <= 3 ? (a) + 4 : (a) == 4 ? 3 : 2) << (((g) % 10) * 3))
102 *(gpio + 7) // sets bits which are 1 ignores bits which are 0
104 *(gpio + 10) // clears bits which are 1 ignores bits which are 0
106 #define GET_GPIO(g) (*(gpio + 13) & (1 << g)) // 0 if LOW, (1<<g) if HIGH
108 #define GPIO_PULL *(gpio + 37) // Pull up/pull down
109 #define GPIO_PULLCLK0 *(gpio + 38) // Pull up/pull down clock
113 uint32_t read8(uint32_t address);
114 void write8(uint32_t address, uint32_t data);
116 uint32_t read16(uint32_t address);
117 void write16(uint32_t address, uint32_t data);
119 void write32(uint32_t address, uint32_t data);
120 uint32_t read32(uint32_t address);
122 uint16_t read_reg(void);
123 void write_reg(unsigned int value);
125 volatile uint16_t srdata;
126 volatile uint32_t srdata2;
127 volatile uint32_t srdata2_old;
129 unsigned char g_kick[524288];
130 unsigned char g_ram[FASTSIZE + 1]; /* RAM */
131 unsigned char toggle;
132 static volatile unsigned char ovl;
133 static volatile unsigned char maprom;
135 void sigint_handler(int sig_num) {
136 printf("\n Exit Ctrl+C %d\n", sig_num);
140 void *iplThread(void *args) {
148 int main(int argc, char *argv[]) {
150 const struct sched_param priority = {99};
152 // Some command line switch stuffles
153 for (g = 1; g < argc; g++) {
154 if (strcmp(argv[g], "--disable-gayle") == 0) {
155 gayle_emulation_enabled = 0;
159 sched_setscheduler(0, SCHED_FIFO, &priority);
160 mlockall(MCL_CURRENT); // lock in memory to keep us from paging out
164 signal(SIGINT, sigint_handler);
167 // Enable 200MHz CLK output on GPIO4, adjust divider and pll source depending
169 printf("Enable 200MHz GPCLK0 on GPIO4\n");
171 *(gpclk + (CLK_GP0_CTL / 4)) = CLK_PASSWD | (1 << 5);
173 while ((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7))
176 *(gpclk + (CLK_GP0_DIV / 4)) =
177 CLK_PASSWD | (6 << 12); // divider , 6=200MHz on pi3
179 *(gpclk + (CLK_GP0_CTL / 4)) =
180 CLK_PASSWD | 5 | (1 << 4); // pll? 6=plld, 5=pllc
182 while (((*(gpclk + (CLK_GP0_CTL / 4))) & (1 << 7)) == 0)
186 SET_GPIO_ALT(4, 0); // gpclk0
196 // set gpio0 (aux0) and gpio1 (aux1) to input
200 // Set GPIO pins 6,7 and 8-23 to output
201 for (g = 6; g <= 23; g++) {
205 printf("Precalculate GPIO8-23 as Output\n");
206 gpfsel0_o = *(gpio); // store gpio ddr
207 printf("gpfsel0: %#x\n", gpfsel0_o);
208 gpfsel1_o = *(gpio + 1); // store gpio ddr
209 printf("gpfsel1: %#x\n", gpfsel1_o);
210 gpfsel2_o = *(gpio + 2); // store gpio ddr
211 printf("gpfsel2: %#x\n", gpfsel2_o);
213 // Set GPIO pins 8-23 to input
214 for (g = 8; g <= 23; g++) {
217 printf("Precalculate GPIO8-23 as Input\n");
218 gpfsel0 = *(gpio); // store gpio ddr
219 printf("gpfsel0: %#x\n", gpfsel0);
220 gpfsel1 = *(gpio + 1); // store gpio ddr
221 printf("gpfsel1: %#x\n", gpfsel1);
222 gpfsel2 = *(gpio + 2); // store gpio ddr
223 printf("gpfsel2: %#x\n", gpfsel2);
232 // reset cpld statemachine first
240 // load kick.rom if present
243 fd = open("kick.rom", O_RDONLY);
245 printf("Failed loading kick.rom, using motherboard kickstart\n");
248 int size = (int)lseek(fd, 0, SEEK_END);
249 if (size == 0x40000) {
250 lseek(fd, 0, SEEK_SET);
251 read(fd, &g_kick, size);
252 lseek(fd, 0, SEEK_SET);
253 read(fd, &g_kick[0x40000], size);
255 lseek(fd, 0, SEEK_SET);
256 read(fd, &g_kick, size);
258 printf("Loaded kick.rom with size %d kib\n", size / 1024);
261 // reset amiga and statemachine
264 m68k_write_memory_8(0xbfe201, 0x0001); // AMIGA OVL
265 m68k_write_memory_8(0xbfe001, 0x0001); // AMIGA OVL high (ROM@0x0)
270 m68k_set_cpu_type(M68K_CPU_TYPE_68040);
274 m68k_set_reg(M68K_REG_PC, 0xF80002);
276 m68k_set_reg(M68K_REG_PC, 0x0);
282 //err = pthread_create(&id, NULL, &iplThread, NULL);
284 printf("\ncan't create IPL thread :[%s]", strerror(err));
286 printf("\n IPL Thread created successfully\n");
293 if (GET_GPIO(1) == 0){
295 m68k_set_irq((srdata >> 13) & 0xff);
297 // if (CheckIrq() == 1)
308 void cpu_pulse_reset(void) {
310 // printf("Status Reg%x\n",read_reg());
313 // printf("Status Reg%x\n",read_reg());
316 int cpu_irq_ack(int level) {
317 printf("cpu irq ack\n");
321 unsigned int m68k_read_memory_8(unsigned int address) {
322 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
323 return g_ram[address - FASTBASE];
327 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
328 return g_kick[address - KICKBASE];
332 if (gayle_emulation_enabled) {
333 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
334 return readGayleB(address);
338 if (address < 0xffffff) {
339 return read8((uint32_t)address);
345 unsigned int m68k_read_memory_16(unsigned int address) {
346 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
347 return be16toh(*(uint16_t *)&g_ram[address - FASTBASE]);
351 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
352 return be16toh(*(uint16_t *)&g_kick[address - KICKBASE]);
356 if (gayle_emulation_enabled) {
357 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
358 return readGayle(address);
362 if (address < 0xffffff) {
363 return (unsigned int)read16((uint32_t)address);
369 unsigned int m68k_read_memory_32(unsigned int address) {
370 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
371 return be32toh(*(uint32_t *)&g_ram[address - FASTBASE]);
375 if (address > KICKBASE && address < KICKBASE + KICKSIZE) {
376 return be32toh(*(uint32_t *)&g_kick[address - KICKBASE]);
380 if (gayle_emulation_enabled) {
381 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
382 return readGayleL(address);
386 if (address < 0xffffff) {
387 uint16_t a = read16(address);
388 uint16_t b = read16(address + 2);
389 return (a << 16) | b;
395 void m68k_write_memory_8(unsigned int address, unsigned int value) {
396 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
397 g_ram[address - FASTBASE] = value;
401 if (gayle_emulation_enabled) {
402 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
403 writeGayleB(address, value);
408 if (address == 0xbfe001) {
409 ovl = (value & (1 << 0));
410 printf("OVL:%x\n", ovl);
413 if (address < 0xffffff) {
414 write8((uint32_t)address, value);
421 void m68k_write_memory_16(unsigned int address, unsigned int value) {
422 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
423 *(uint16_t *)&g_ram[address - FASTBASE] = htobe16(value);
427 if (gayle_emulation_enabled) {
428 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
429 writeGayle(address, value);
434 if (address < 0xffffff) {
435 write16((uint32_t)address, value);
441 void m68k_write_memory_32(unsigned int address, unsigned int value) {
442 if (address > FASTBASE && address < FASTBASE + FASTSIZE) {
443 *(uint32_t *)&g_ram[address - FASTBASE] = htobe32(value);
447 if (gayle_emulation_enabled) {
448 if (address > GAYLEBASE && address < GAYLEBASE + GAYLESIZE) {
449 writeGayleL(address, value);
453 if (address < 0xffffff) {
454 write16(address, value >> 16);
455 write16(address + 2, value);
462 void write16(uint32_t address, uint32_t data) {
463 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
464 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
465 uint32_t addr_l_s = (address >> 16) << 8;
466 uint32_t addr_l_r = (~address >> 16) << 8;
467 uint32_t data_s = (data & 0x0000ffff) << 8;
468 uint32_t data_r = (~data & 0x0000ffff) << 8;
470 // asm volatile ("dmb" ::: "memory");
473 *(gpio + 1) = gpfsel1_o;
474 *(gpio + 2) = gpfsel2_o;
476 *(gpio + 7) = addr_h_s;
477 *(gpio + 10) = addr_h_r;
481 *(gpio + 7) = addr_l_s;
482 *(gpio + 10) = addr_l_r;
487 *(gpio + 7) = data_s;
488 *(gpio + 10) = data_r;
493 *(gpio + 1) = gpfsel1;
494 *(gpio + 2) = gpfsel2;
495 while ((GET_GPIO(0)))
497 // asm volatile ("dmb" ::: "memory");
500 void write8(uint32_t address, uint32_t data) {
501 if ((address & 1) == 0)
502 data = data + (data << 8); // EVEN, A0=0,UDS
504 data = data & 0xff; // ODD , A0=1,LDS
505 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
506 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
507 uint32_t addr_l_s = (address >> 16) << 8;
508 uint32_t addr_l_r = (~address >> 16) << 8;
509 uint32_t data_s = (data & 0x0000ffff) << 8;
510 uint32_t data_r = (~data & 0x0000ffff) << 8;
512 // asm volatile ("dmb" ::: "memory");
515 *(gpio + 1) = gpfsel1_o;
516 *(gpio + 2) = gpfsel2_o;
518 *(gpio + 7) = addr_h_s;
519 *(gpio + 10) = addr_h_r;
523 *(gpio + 7) = addr_l_s;
524 *(gpio + 10) = addr_l_r;
529 *(gpio + 7) = data_s;
530 *(gpio + 10) = data_r;
535 *(gpio + 1) = gpfsel1;
536 *(gpio + 2) = gpfsel2;
537 while ((GET_GPIO(0)))
539 // asm volatile ("dmb" ::: "memory");
542 uint32_t read16(uint32_t address) {
544 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
545 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
546 uint32_t addr_l_s = (address >> 16) << 8;
547 uint32_t addr_l_r = (~address >> 16) << 8;
549 // asm volatile ("dmb" ::: "memory");
552 *(gpio + 1) = gpfsel1_o;
553 *(gpio + 2) = gpfsel2_o;
555 *(gpio + 7) = addr_h_s;
556 *(gpio + 10) = addr_h_r;
560 *(gpio + 7) = addr_l_s;
561 *(gpio + 10) = addr_l_r;
567 *(gpio + 1) = gpfsel1;
568 *(gpio + 2) = gpfsel2;
570 while (!(GET_GPIO(0)))
575 // asm volatile ("dmb" ::: "memory");
576 return (val >> 8) & 0xffff;
579 uint32_t read8(uint32_t address) {
581 uint32_t addr_h_s = (address & 0x0000ffff) << 8;
582 uint32_t addr_h_r = (~address & 0x0000ffff) << 8;
583 uint32_t addr_l_s = (address >> 16) << 8;
584 uint32_t addr_l_r = (~address >> 16) << 8;
586 // asm volatile ("dmb" ::: "memory");
589 *(gpio + 1) = gpfsel1_o;
590 *(gpio + 2) = gpfsel2_o;
592 *(gpio + 7) = addr_h_s;
593 *(gpio + 10) = addr_h_r;
597 *(gpio + 7) = addr_l_s;
598 *(gpio + 10) = addr_l_r;
604 *(gpio + 1) = gpfsel1;
605 *(gpio + 2) = gpfsel2;
608 while (!(GET_GPIO(0)))
613 // asm volatile ("dmb" ::: "memory");
615 val = (val >> 8) & 0xffff;
616 if ((address & 1) == 0)
617 return (val >> 8) & 0xff; // EVEN, A0=0,UDS
619 return val & 0xff; // ODD , A0=1,LDS
622 /******************************************************/
624 void write_reg(unsigned int value) {
627 *(gpio + 1) = gpfsel1_o;
628 *(gpio + 2) = gpfsel2_o;
629 *(gpio + 7) = (value & 0xffff) << 8;
630 *(gpio + 10) = (~value & 0xffff) << 8;
632 GPIO_CLR = 1 << 7; // delay
637 *(gpio + 1) = gpfsel1;
638 *(gpio + 2) = gpfsel2;
641 uint16_t read_reg(void) {
646 *(gpio + 1) = gpfsel1;
647 *(gpio + 2) = gpfsel2;
649 GPIO_CLR = 1 << 6; // delay
654 return (uint16_t)(val >> 8);
658 // Set up a memory regions to access GPIO
662 if ((mem_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0) {
663 printf("can't open /dev/mem \n");
669 NULL, // Any adddress in our space will do
670 BCM2708_PERI_SIZE, // Map length
671 PROT_READ | PROT_WRITE, // Enable reading & writting to mapped memory
672 MAP_SHARED, // Shared with other processes
673 mem_fd, // File to map
674 BCM2708_PERI_BASE // Offset to GPIO peripheral
677 close(mem_fd); // No need to keep mem_fd open after mmap
679 if (gpio_map == MAP_FAILED) {
680 printf("gpio mmap error %d\n", (int)gpio_map); // errno also set!
684 gpio = ((volatile unsigned *)gpio_map) + GPIO_ADDR / 4;
685 gpclk = ((volatile unsigned *)gpio_map) + GPCLK_ADDR / 4;