git.sesse.net Git - ffmpeg/blob - libavcodec/arm/mdct_neon.S

   1 /*
   2  * ARM NEON optimised MDCT
   3  * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
   4  *
   5  * This file is part of FFmpeg.
   6  *
   7  * FFmpeg is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * FFmpeg is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with FFmpeg; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 #include "asm.S"
  23
  24         .fpu neon
  25         .text
  26
  27 function ff_imdct_half_neon, export=1
  28         push            {r4-r8,lr}
  29
  30         mov             r12, #1
  31         ldr             lr,  [r0, #4]           @ nbits
  32         ldr             r4,  [r0, #8]           @ tcos
  33         ldr             r5,  [r0, #12]          @ tsin
  34         ldr             r3,  [r0, #24]          @ revtab
  35         lsl             r12, r12, lr            @ n  = 1 << nbits
  36         lsr             lr,  r12, #2            @ n4 = n >> 2
  37         add             r7,  r2,  r12,  lsl #1
  38         mov             r12,  #-16
  39         sub             r7,  r7,  #16
  40
  41         vld2.32         {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0
  42         vld2.32         {d0-d1},  [r2,:128]!    @ d0 =m0,x d1 =m1,x
  43         vrev64.32       d17, d17
  44         vld1.32         {d2},     [r4,:64]!     @ d2=c0,c1
  45         vmul.f32        d6,  d17, d2
  46         vld1.32         {d3},     [r5,:64]!     @ d3=s0,s1
  47         vmul.f32        d7,  d0,  d2
  48 1:
  49         subs            lr,  lr,  #2
  50         ldr             r6,  [r3], #4
  51         vmul.f32        d4,  d0,  d3
  52         vmul.f32        d5,  d17, d3
  53         vsub.f32        d4,  d6,  d4
  54         vadd.f32        d5,  d5,  d7
  55         uxtah           r8,  r1,  r6,  ror #16
  56         uxtah           r6,  r1,  r6
  57         beq             1f
  58         vld2.32         {d16-d17},[r7,:128],r12
  59         vld2.32         {d0-d1},  [r2,:128]!
  60         vrev64.32       d17, d17
  61         vld1.32         {d2},     [r4,:64]!
  62         vmul.f32        d6,  d17, d2
  63         vld1.32         {d3},     [r5,:64]!
  64         vmul.f32        d7,  d0,  d2
  65         vst2.32         {d4[0],d5[0]}, [r6,:64]
  66         vst2.32         {d4[1],d5[1]}, [r8,:64]
  67         b               1b
  68 1:
  69         vst2.32         {d4[0],d5[0]}, [r6,:64]
  70         vst2.32         {d4[1],d5[1]}, [r8,:64]
  71
  72         mov             r4,  r0
  73         mov             r6,  r1
  74         add             r0,  r0,  #16
  75         bl              ff_fft_calc_neon
  76
  77         mov             r12, #1
  78         ldr             lr,  [r4, #4]           @ nbits
  79         ldr             r5,  [r4, #12]          @ tsin
  80         ldr             r4,  [r4, #8]           @ tcos
  81         lsl             r12, r12, lr            @ n  = 1 << nbits
  82         lsr             lr,  r12, #3            @ n8 = n >> 3
  83
  84         add             r4,  r4,  lr,  lsl #2
  85         add             r5,  r5,  lr,  lsl #2
  86         add             r6,  r6,  lr,  lsl #3
  87         sub             r1,  r4,  #8
  88         sub             r2,  r5,  #8
  89         sub             r3,  r6,  #16
  90
  91         mov             r7,  #-16
  92         mov             r12, #-8
  93         mov             r8,  r6
  94         mov             r0,  r3
  95
  96         vld2.32         {d0-d1},  [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0
  97         vld2.32         {d20-d21},[r6,:128]!    @ d20=i2,r2 d21=i3,r3
  98         vld1.32         {d18},    [r2,:64], r12 @ d18=s1,s0
  99 1:
 100         subs            lr,  lr,  #2
 101         vmul.f32        d7,  d0,  d18
 102         vld1.32         {d19},    [r5,:64]!     @ d19=s2,s3
 103         vmul.f32        d4,  d1,  d18
 104         vld1.32         {d16},    [r1,:64], r12 @ d16=c1,c0
 105         vmul.f32        d5,  d21, d19
 106         vld1.32         {d17},    [r4,:64]!     @ d17=c2,c3
 107         vmul.f32        d6,  d20, d19
 108         vmul.f32        d22, d1,  d16
 109         vmul.f32        d23, d21, d17
 110         vmul.f32        d24, d0,  d16
 111         vmul.f32        d25, d20, d17
 112         vadd.f32        d7,  d7,  d22
 113         vadd.f32        d6,  d6,  d23
 114         vsub.f32        d4,  d4,  d24
 115         vsub.f32        d5,  d5,  d25
 116         beq             1f
 117         vld2.32         {d0-d1},  [r3,:128], r7
 118         vld2.32         {d20-d21},[r6,:128]!
 119         vld1.32         {d18},    [r2,:64], r12
 120         vrev64.32       q3,  q3
 121         vst2.32         {d4,d6},  [r0,:128], r7
 122         vst2.32         {d5,d7},  [r8,:128]!
 123         b               1b
 124 1:
 125         vrev64.32       q3,  q3
 126         vst2.32         {d4,d6},  [r0,:128]
 127         vst2.32         {d5,d7},  [r8,:128]
 128
 129         pop             {r4-r8,pc}
 130 .endfunc
 131
 132 function ff_imdct_calc_neon, export=1
 133         push            {r4-r6,lr}
 134
 135         ldr             r3,  [r0, #4]
 136         mov             r4,  #1
 137         mov             r5,  r1
 138         lsl             r4,  r4,  r3
 139         add             r1,  r1,  r4
 140
 141         bl              ff_imdct_half_neon
 142
 143         add             r0,  r5,  r4,  lsl #2
 144         add             r1,  r5,  r4,  lsl #1
 145         sub             r0,  r0,  #8
 146         sub             r2,  r1,  #16
 147         mov             r3,  #-16
 148         mov             r6,  #-8
 149         vmov.i32        d30, #1<<31
 150 1:
 151         vld1.32         {d0-d1},  [r2,:128], r3
 152         pld             [r0, #-16]
 153         vrev64.32       q0,  q0
 154         vld1.32         {d2-d3},  [r1,:128]!
 155         veor            d4,  d1,  d30
 156         pld             [r2, #-16]
 157         vrev64.32       q1,  q1
 158         veor            d5,  d0,  d30
 159         vst1.32         {d2},     [r0,:64], r6
 160         vst1.32         {d3},     [r0,:64], r6
 161         vst1.32         {d4-d5},  [r5,:128]!
 162         subs            r4,  r4,  #16
 163         bgt             1b
 164
 165         pop             {r4-r6,pc}
 166 .endfunc