4 * Copyright (c) 2001 Michael Niedermayer <michaelni@gmx.at>
5 * Copyright (c) 2007 Mans Rullgard <mans@mansr.com>
7 * This file is part of FFmpeg.
9 * FFmpeg is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * FFmpeg is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with FFmpeg; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
24 #define W1 22725 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
25 #define W2 21407 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
26 #define W3 19266 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
27 #define W4 16383 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
28 #define W5 12873 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
29 #define W6 8867 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
30 #define W7 4520 /* cos(i*M_PI/16)*sqrt(2)*(1<<14) + 0.5 */
34 #define W13 (W1 | (W3 << 16))
35 #define W26 (W2 | (W6 << 16))
36 #define W42 (W4 | (W2 << 16))
37 #define W42n (-W4&0xffff | (-W2 << 16))
38 #define W46 (W4 | (W6 << 16))
39 #define W57 (W5 | (W7 << 16))
51 Compute partial IDCT of single row.
52 shift = left-shift amount
54 a3 = row[2,0] <= 2 cycles
58 Output in registers v1--v8
61 ldr lr, [pc, #(w46-.-8)] /* lr = W4 | (W6 << 16) */
62 mov a2, #(1<<(\shift-1))
65 ldr ip, [pc, #(w13-.-8)] /* ip = W1 | (W3 << 16) */
66 ldr v7, [pc, #(w57-.-8)] /* v7 = W5 | (W7 << 16) */
70 smuad v5, a4, ip /* v5 = B0 = W1*row[1] + W3*row[3] */
71 smusdx fp, a4, v7 /* fp = B3 = W7*row[1] - W5*row[3] */
72 ldr lr, [a1, #12] /* lr = row[7,5] */
73 pkhtb a3, ip, v7, asr #16 /* a4 = W7 | (W3 << 16) */
74 pkhbt a2, ip, v7, lsl #16 /* a2 = W1 | (W5 << 16) */
75 smusdx v6, a3, a4 /* v6 = -B1 = W7*row[3] - W3*row[1] */
76 smlad v5, lr, v7, v5 /* B0 += W5*row[5] + W7*row[7] */
77 smusdx v7, a4, a2 /* v7 = B2 = W5*row[1] - W1*row[3] */
79 ldr a4, [pc, #(w42n-.-8)] /* a4 = -W4 | (-W2 << 16) */
80 smlad v7, lr, a3, v7 /* B2 += W7*row[5] + W3*row[7] */
81 ldr a3, [a1, #4] /* a3 = row[6,4] */
82 smlsdx fp, lr, ip, fp /* B3 += W3*row[5] - W1*row[7] */
83 ldr ip, [pc, #(w46-.-8)] /* ip = W4 | (W6 << 16) */
84 smlad v6, lr, a2, v6 /* B1 -= W1*row[5] + W5*row[7] */
86 smlad v2, a3, a4, v2 /* A1 += -W4*row[4] - W2*row[6] */
87 smlsd v3, a3, a4, v3 /* A2 += -W4*row[4] + W2*row[6] */
88 smlad v1, a3, ip, v1 /* A0 += W4*row[4] + W6*row[6] */
89 smlsd v4, a3, ip, v4 /* A3 += W4*row[4] - W6*row[6] */
93 Compute partial IDCT of half row.
94 shift = left-shift amount
99 Output in registers v1--v8
101 .macro idct_row4 shift
102 ldr lr, [pc, #(w46-.-8)] /* lr = W4 | (W6 << 16) */
103 ldr v7, [pc, #(w57-.-8)] /* v7 = W5 | (W7 << 16) */
104 mov a2, #(1<<(\shift-1))
107 ldr ip, [pc, #(w13-.-8)] /* ip = W1 | (W3 << 16) */
110 smusdx fp, a4, v7 /* fp = B3 = W7*row[1] - W5*row[3] */
111 smuad v5, a4, ip /* v5 = B0 = W1*row[1] + W3*row[3] */
112 pkhtb a3, ip, v7, asr #16 /* a4 = W7 | (W3 << 16) */
113 pkhbt a2, ip, v7, lsl #16 /* a2 = W1 | (W5 << 16) */
114 smusdx v6, a3, a4 /* v6 = -B1 = W7*row[3] - W3*row[1] */
115 smusdx v7, a4, a2 /* v7 = B2 = W5*row[1] - W1*row[3] */
119 Compute final part of IDCT single row without shift.
120 Input in registers v1--v8
121 Output in registers ip, v1--v3, lr, v5--v7
124 add ip, v1, v5 /* a2 = A0 + B0 */
125 sub lr, v1, v5 /* a3 = A0 - B0 */
126 sub v1, v2, v6 /* a3 = A1 + B1 */
127 add v5, v2, v6 /* a3 = A1 - B1 */
128 add v2, v3, v7 /* a2 = A2 + B2 */
129 sub v6, v3, v7 /* a2 = A2 - B2 */
130 add v3, v4, fp /* a3 = A3 + B3 */
131 sub v7, v4, fp /* a3 = A3 - B3 */
135 Compute final part of IDCT single row.
136 shift = right-shift amount
137 Input/output in registers v1--v8
139 .macro idct_finish_shift shift
140 add a4, v1, v5 /* a4 = A0 + B0 */
141 sub a3, v1, v5 /* a3 = A0 - B0 */
142 mov v1, a4, asr #\shift
143 mov v5, a3, asr #\shift
145 sub a4, v2, v6 /* a4 = A1 + B1 */
146 add a3, v2, v6 /* a3 = A1 - B1 */
147 mov v2, a4, asr #\shift
148 mov v6, a3, asr #\shift
150 add a4, v3, v7 /* a4 = A2 + B2 */
151 sub a3, v3, v7 /* a3 = A2 - B2 */
152 mov v3, a4, asr #\shift
153 mov v7, a3, asr #\shift
155 add a4, v4, fp /* a4 = A3 + B3 */
156 sub a3, v4, fp /* a3 = A3 - B3 */
157 mov v4, a4, asr #\shift
158 mov fp, a3, asr #\shift
162 Compute final part of IDCT single row, saturating results at 8 bits.
163 shift = right-shift amount
164 Input/output in registers v1--v8
166 .macro idct_finish_shift_sat shift
167 add a4, v1, v5 /* a4 = A0 + B0 */
168 sub ip, v1, v5 /* ip = A0 - B0 */
169 usat v1, #8, a4, asr #\shift
170 usat v5, #8, ip, asr #\shift
172 sub a4, v2, v6 /* a4 = A1 + B1 */
173 add ip, v2, v6 /* ip = A1 - B1 */
174 usat v2, #8, a4, asr #\shift
175 usat v6, #8, ip, asr #\shift
177 add a4, v3, v7 /* a4 = A2 + B2 */
178 sub ip, v3, v7 /* ip = A2 - B2 */
179 usat v3, #8, a4, asr #\shift
180 usat v7, #8, ip, asr #\shift
182 add a4, v4, fp /* a4 = A3 + B3 */
183 sub ip, v4, fp /* ip = A3 - B3 */
184 usat v4, #8, a4, asr #\shift
185 usat fp, #8, ip, asr #\shift
189 Compute IDCT of single row, storing as column.
194 .type idct_row_armv6, %function
199 ldr lr, [a1, #12] /* lr = row[7,5] */
200 ldr ip, [a1, #4] /* ip = row[6,4] */
201 ldr a4, [a1, #8] /* a4 = row[3,1] */
202 ldr a3, [a1] /* a3 = row[2,0] */
205 cmpeq lr, a3, lsr #16
208 ldr ip, [pc, #(w42-.-8)] /* ip = W4 | (W2 << 16) */
215 2: idct_row4 ROW_SHIFT
218 idct_finish_shift ROW_SHIFT
221 strh v2, [a2, #(16*2)]
222 strh v3, [a2, #(16*4)]
223 strh v4, [a2, #(16*6)]
224 strh fp, [a2, #(16*1)]
225 strh v7, [a2, #(16*3)]
226 strh v6, [a2, #(16*5)]
227 strh v5, [a2, #(16*7)]
231 1: mov a3, a3, lsl #3
233 strh a3, [a2, #(16*2)]
234 strh a3, [a2, #(16*4)]
235 strh a3, [a2, #(16*6)]
236 strh a3, [a2, #(16*1)]
237 strh a3, [a2, #(16*3)]
238 strh a3, [a2, #(16*5)]
239 strh a3, [a2, #(16*7)]
244 Compute IDCT of single column, read as row.
249 .type idct_col_armv6, %function
254 ldr a3, [a1] /* a3 = row[2,0] */
255 ldr ip, [pc, #(w42-.-8)] /* ip = W4 | (W2 << 16) */
256 ldr a4, [a1, #8] /* a4 = row[3,1] */
259 idct_finish_shift COL_SHIFT
262 strh v2, [a2, #(16*1)]
263 strh v3, [a2, #(16*2)]
264 strh v4, [a2, #(16*3)]
265 strh fp, [a2, #(16*4)]
266 strh v7, [a2, #(16*5)]
267 strh v6, [a2, #(16*6)]
268 strh v5, [a2, #(16*7)]
274 Compute IDCT of single column, read as row, store saturated 8-bit.
280 .type idct_col_put_armv6, %function
281 .func idct_col_put_armv6
283 stmfd sp!, {a2, a3, lr}
285 ldr a3, [a1] /* a3 = row[2,0] */
286 ldr ip, [pc, #(w42-.-8)] /* ip = W4 | (W2 << 16) */
287 ldr a4, [a1, #8] /* a4 = row[3,1] */
290 idct_finish_shift_sat COL_SHIFT
301 sub a2, a2, a3, lsl #3
307 Compute IDCT of single column, read as row, add/store saturated 8-bit.
313 .type idct_col_add_armv6, %function
314 .func idct_col_add_armv6
316 stmfd sp!, {a2, a3, lr}
318 ldr a3, [a1] /* a3 = row[2,0] */
319 ldr ip, [pc, #(w42-.-8)] /* ip = W4 | (W2 << 16) */
320 ldr a4, [a1, #8] /* a4 = row[3,1] */
327 ldrb fp, [a2, a3, lsl #2]
328 add ip, a4, ip, asr #COL_SHIFT
330 add v1, v4, v1, asr #COL_SHIFT
334 ldrb fp, [a2, a3, lsl #2]
335 add v2, ip, v2, asr #COL_SHIFT
339 ldrb ip, [a2, a3, lsl #2]
342 ldrb v1, [a2, a3, lsl #2]
343 add v3, a4, v3, asr #COL_SHIFT
345 add v7, v4, v7, asr #COL_SHIFT
347 add v6, fp, v6, asr #COL_SHIFT
349 add v5, ip, v5, asr #COL_SHIFT
351 add lr, v1, lr, asr #COL_SHIFT
359 sub a2, a2, a3, lsl #3
365 Compute 8 IDCT row transforms.
366 func = IDCT row->col function
367 width = width of columns in bytes
369 .macro idct_rows func width
397 .global ff_simple_idct_armv6
398 .type ff_simple_idct_armv6, %function
399 .func ff_simple_idct_armv6
400 /* void ff_simple_idct_armv6(DCTELEM *data); */
401 ff_simple_idct_armv6:
402 stmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, lr}
406 idct_rows idct_row_armv6, 2
409 idct_rows idct_col_armv6, 2
412 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
416 .global ff_simple_idct_add_armv6
417 .type ff_simple_idct_add_armv6, %function
418 .func ff_simple_idct_add_armv6
419 /* ff_simple_idct_add_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
420 ff_simple_idct_add_armv6:
421 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
426 idct_rows idct_row_armv6, 2
429 ldr a3, [sp, #(128+4)]
430 idct_rows idct_col_add_armv6, 1
433 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}
437 .global ff_simple_idct_put_armv6
438 .type ff_simple_idct_put_armv6, %function
439 .func ff_simple_idct_put_armv6
440 /* ff_simple_idct_put_armv6(uint8_t *dest, int line_size, DCTELEM *data); */
441 ff_simple_idct_put_armv6:
442 stmfd sp!, {a1, a2, v1, v2, v3, v4, v5, v6, v7, fp, lr}
447 idct_rows idct_row_armv6, 2
450 ldr a3, [sp, #(128+4)]
451 idct_rows idct_col_put_armv6, 1
454 ldmfd sp!, {v1, v2, v3, v4, v5, v6, v7, fp, pc}