2 * H.264 hardware encoding using nvidia nvenc
3 * Copyright (c) 2014 Timo Rothenpieler <timo@rothenpieler.org>
5 * This file is part of FFmpeg.
7 * FFmpeg is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * FFmpeg is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with FFmpeg; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
27 #define CUDA_LIBNAME TEXT("nvcuda.dll")
29 #define NVENC_LIBNAME TEXT("nvEncodeAPI64.dll")
31 #define NVENC_LIBNAME TEXT("nvEncodeAPI.dll")
34 #define dlopen(filename, flags) LoadLibrary((filename))
35 #define dlsym(handle, symbol) GetProcAddress(handle, symbol)
36 #define dlclose(handle) FreeLibrary(handle)
40 #define CUDA_LIBNAME "libcuda.so"
41 #define NVENC_LIBNAME "libnvidia-encode.so"
44 #include "libavutil/hwcontext.h"
45 #include "libavutil/imgutils.h"
46 #include "libavutil/avassert.h"
47 #include "libavutil/mem.h"
51 #define NVENC_CAP 0x30
52 #define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR || \
53 rc == NV_ENC_PARAMS_RC_2_PASS_QUALITY || \
54 rc == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP)
56 #define LOAD_LIBRARY(l, path) \
58 if (!((l) = dlopen(path, RTLD_LAZY))) { \
59 av_log(avctx, AV_LOG_ERROR, \
62 return AVERROR_UNKNOWN; \
66 #define LOAD_SYMBOL(fun, lib, symbol) \
68 if (!((fun) = dlsym(lib, symbol))) { \
69 av_log(avctx, AV_LOG_ERROR, \
72 return AVERROR_UNKNOWN; \
76 const enum AVPixelFormat ff_nvenc_pix_fmts[] = {
91 { NV_ENC_SUCCESS, 0, "success" },
92 { NV_ENC_ERR_NO_ENCODE_DEVICE, AVERROR(ENOENT), "no encode device" },
93 { NV_ENC_ERR_UNSUPPORTED_DEVICE, AVERROR(ENOSYS), "unsupported device" },
94 { NV_ENC_ERR_INVALID_ENCODERDEVICE, AVERROR(EINVAL), "invalid encoder device" },
95 { NV_ENC_ERR_INVALID_DEVICE, AVERROR(EINVAL), "invalid device" },
96 { NV_ENC_ERR_DEVICE_NOT_EXIST, AVERROR(EIO), "device does not exist" },
97 { NV_ENC_ERR_INVALID_PTR, AVERROR(EFAULT), "invalid ptr" },
98 { NV_ENC_ERR_INVALID_EVENT, AVERROR(EINVAL), "invalid event" },
99 { NV_ENC_ERR_INVALID_PARAM, AVERROR(EINVAL), "invalid param" },
100 { NV_ENC_ERR_INVALID_CALL, AVERROR(EINVAL), "invalid call" },
101 { NV_ENC_ERR_OUT_OF_MEMORY, AVERROR(ENOMEM), "out of memory" },
102 { NV_ENC_ERR_ENCODER_NOT_INITIALIZED, AVERROR(EINVAL), "encoder not initialized" },
103 { NV_ENC_ERR_UNSUPPORTED_PARAM, AVERROR(ENOSYS), "unsupported param" },
104 { NV_ENC_ERR_LOCK_BUSY, AVERROR(EAGAIN), "lock busy" },
105 { NV_ENC_ERR_NOT_ENOUGH_BUFFER, AVERROR(ENOBUFS), "not enough buffer" },
106 { NV_ENC_ERR_INVALID_VERSION, AVERROR(EINVAL), "invalid version" },
107 { NV_ENC_ERR_MAP_FAILED, AVERROR(EIO), "map failed" },
108 { NV_ENC_ERR_NEED_MORE_INPUT, AVERROR(EAGAIN), "need more input" },
109 { NV_ENC_ERR_ENCODER_BUSY, AVERROR(EAGAIN), "encoder busy" },
110 { NV_ENC_ERR_EVENT_NOT_REGISTERD, AVERROR(EBADF), "event not registered" },
111 { NV_ENC_ERR_GENERIC, AVERROR_UNKNOWN, "generic error" },
112 { NV_ENC_ERR_INCOMPATIBLE_CLIENT_KEY, AVERROR(EINVAL), "incompatible client key" },
113 { NV_ENC_ERR_UNIMPLEMENTED, AVERROR(ENOSYS), "unimplemented" },
114 { NV_ENC_ERR_RESOURCE_REGISTER_FAILED, AVERROR(EIO), "resource register failed" },
115 { NV_ENC_ERR_RESOURCE_NOT_REGISTERED, AVERROR(EBADF), "resource not registered" },
116 { NV_ENC_ERR_RESOURCE_NOT_MAPPED, AVERROR(EBADF), "resource not mapped" },
119 static int nvenc_map_error(NVENCSTATUS err, const char **desc)
122 for (i = 0; i < FF_ARRAY_ELEMS(nvenc_errors); i++) {
123 if (nvenc_errors[i].nverr == err) {
125 *desc = nvenc_errors[i].desc;
126 return nvenc_errors[i].averr;
130 *desc = "unknown error";
131 return AVERROR_UNKNOWN;
134 static int nvenc_print_error(void *log_ctx, NVENCSTATUS err,
135 const char *error_string)
139 ret = nvenc_map_error(err, &desc);
140 av_log(log_ctx, AV_LOG_ERROR, "%s: %s (%d)\n", error_string, desc, err);
144 static av_cold int nvenc_load_libraries(AVCodecContext *avctx)
146 NvencContext *ctx = avctx->priv_data;
147 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
148 PNVENCODEAPICREATEINSTANCE nvenc_create_instance;
152 dl_fn->cu_init = cuInit;
153 dl_fn->cu_device_get_count = cuDeviceGetCount;
154 dl_fn->cu_device_get = cuDeviceGet;
155 dl_fn->cu_device_get_name = cuDeviceGetName;
156 dl_fn->cu_device_compute_capability = cuDeviceComputeCapability;
157 dl_fn->cu_ctx_create = cuCtxCreate_v2;
158 dl_fn->cu_ctx_pop_current = cuCtxPopCurrent_v2;
159 dl_fn->cu_ctx_destroy = cuCtxDestroy_v2;
161 LOAD_LIBRARY(dl_fn->cuda, CUDA_LIBNAME);
163 LOAD_SYMBOL(dl_fn->cu_init, dl_fn->cuda, "cuInit");
164 LOAD_SYMBOL(dl_fn->cu_device_get_count, dl_fn->cuda, "cuDeviceGetCount");
165 LOAD_SYMBOL(dl_fn->cu_device_get, dl_fn->cuda, "cuDeviceGet");
166 LOAD_SYMBOL(dl_fn->cu_device_get_name, dl_fn->cuda, "cuDeviceGetName");
167 LOAD_SYMBOL(dl_fn->cu_device_compute_capability, dl_fn->cuda,
168 "cuDeviceComputeCapability");
169 LOAD_SYMBOL(dl_fn->cu_ctx_create, dl_fn->cuda, "cuCtxCreate_v2");
170 LOAD_SYMBOL(dl_fn->cu_ctx_pop_current, dl_fn->cuda, "cuCtxPopCurrent_v2");
171 LOAD_SYMBOL(dl_fn->cu_ctx_destroy, dl_fn->cuda, "cuCtxDestroy_v2");
174 LOAD_LIBRARY(dl_fn->nvenc, NVENC_LIBNAME);
176 LOAD_SYMBOL(nvenc_create_instance, dl_fn->nvenc,
177 "NvEncodeAPICreateInstance");
179 dl_fn->nvenc_funcs.version = NV_ENCODE_API_FUNCTION_LIST_VER;
181 err = nvenc_create_instance(&dl_fn->nvenc_funcs);
182 if (err != NV_ENC_SUCCESS)
183 return nvenc_print_error(avctx, err, "Failed to create nvenc instance");
185 av_log(avctx, AV_LOG_VERBOSE, "Nvenc initialized successfully\n");
190 static av_cold int nvenc_open_session(AVCodecContext *avctx)
192 NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS params = { 0 };
193 NvencContext *ctx = avctx->priv_data;
194 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
197 params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER;
198 params.apiVersion = NVENCAPI_VERSION;
199 params.device = ctx->cu_context;
200 params.deviceType = NV_ENC_DEVICE_TYPE_CUDA;
202 ret = p_nvenc->nvEncOpenEncodeSessionEx(¶ms, &ctx->nvencoder);
203 if (ret != NV_ENC_SUCCESS) {
204 ctx->nvencoder = NULL;
205 return nvenc_print_error(avctx, ret, "OpenEncodeSessionEx failed");
211 static int nvenc_check_codec_support(AVCodecContext *avctx)
213 NvencContext *ctx = avctx->priv_data;
214 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
215 int i, ret, count = 0;
218 ret = p_nvenc->nvEncGetEncodeGUIDCount(ctx->nvencoder, &count);
220 if (ret != NV_ENC_SUCCESS || !count)
221 return AVERROR(ENOSYS);
223 guids = av_malloc(count * sizeof(GUID));
225 return AVERROR(ENOMEM);
227 ret = p_nvenc->nvEncGetEncodeGUIDs(ctx->nvencoder, guids, count, &count);
228 if (ret != NV_ENC_SUCCESS) {
229 ret = AVERROR(ENOSYS);
233 ret = AVERROR(ENOSYS);
234 for (i = 0; i < count; i++) {
235 if (!memcmp(&guids[i], &ctx->init_encode_params.encodeGUID, sizeof(*guids))) {
247 static int nvenc_check_cap(AVCodecContext *avctx, NV_ENC_CAPS cap)
249 NvencContext *ctx = avctx->priv_data;
250 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
251 NV_ENC_CAPS_PARAM params = { 0 };
254 params.version = NV_ENC_CAPS_PARAM_VER;
255 params.capsToQuery = cap;
257 ret = p_nvenc->nvEncGetEncodeCaps(ctx->nvencoder, ctx->init_encode_params.encodeGUID, ¶ms, &val);
259 if (ret == NV_ENC_SUCCESS)
264 static int nvenc_check_capabilities(AVCodecContext *avctx)
266 NvencContext *ctx = avctx->priv_data;
269 ret = nvenc_check_codec_support(avctx);
271 av_log(avctx, AV_LOG_VERBOSE, "Codec not supported\n");
275 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_YUV444_ENCODE);
276 if (ctx->data_pix_fmt == AV_PIX_FMT_YUV444P && ret <= 0) {
277 av_log(avctx, AV_LOG_VERBOSE, "YUV444P not supported\n");
278 return AVERROR(ENOSYS);
281 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOSSLESS_ENCODE);
282 if (ctx->preset >= PRESET_LOSSLESS_DEFAULT && ret <= 0) {
283 av_log(avctx, AV_LOG_VERBOSE, "Lossless encoding not supported\n");
284 return AVERROR(ENOSYS);
287 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_WIDTH_MAX);
288 if (ret < avctx->width) {
289 av_log(avctx, AV_LOG_VERBOSE, "Width %d exceeds %d\n",
291 return AVERROR(ENOSYS);
294 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_HEIGHT_MAX);
295 if (ret < avctx->height) {
296 av_log(avctx, AV_LOG_VERBOSE, "Height %d exceeds %d\n",
298 return AVERROR(ENOSYS);
301 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_NUM_MAX_BFRAMES);
302 if (ret < avctx->max_b_frames) {
303 av_log(avctx, AV_LOG_VERBOSE, "Max B-frames %d exceed %d\n",
304 avctx->max_b_frames, ret);
306 return AVERROR(ENOSYS);
309 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_FIELD_ENCODING);
310 if (ret < 1 && avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
311 av_log(avctx, AV_LOG_VERBOSE,
312 "Interlaced encoding is not supported. Supported level: %d\n",
314 return AVERROR(ENOSYS);
320 static av_cold int nvenc_check_device(AVCodecContext *avctx, int idx)
322 NvencContext *ctx = avctx->priv_data;
323 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
324 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
325 char name[128] = { 0};
326 int major, minor, ret;
330 int loglevel = AV_LOG_VERBOSE;
332 if (ctx->device == LIST_DEVICES)
333 loglevel = AV_LOG_INFO;
335 cu_res = dl_fn->cu_device_get(&cu_device, idx);
336 if (cu_res != CUDA_SUCCESS) {
337 av_log(avctx, AV_LOG_ERROR,
338 "Cannot access the CUDA device %d\n",
343 cu_res = dl_fn->cu_device_get_name(name, sizeof(name), cu_device);
344 if (cu_res != CUDA_SUCCESS)
347 cu_res = dl_fn->cu_device_compute_capability(&major, &minor, cu_device);
348 if (cu_res != CUDA_SUCCESS)
351 av_log(avctx, loglevel, "[ GPU #%d - < %s > has Compute SM %d.%d ]\n", idx, name, major, minor);
352 if (((major << 4) | minor) < NVENC_CAP) {
353 av_log(avctx, loglevel, "does not support NVENC\n");
357 cu_res = dl_fn->cu_ctx_create(&ctx->cu_context_internal, 0, cu_device);
358 if (cu_res != CUDA_SUCCESS) {
359 av_log(avctx, AV_LOG_FATAL, "Failed creating CUDA context for NVENC: 0x%x\n", (int)cu_res);
363 ctx->cu_context = ctx->cu_context_internal;
365 cu_res = dl_fn->cu_ctx_pop_current(&dummy);
366 if (cu_res != CUDA_SUCCESS) {
367 av_log(avctx, AV_LOG_FATAL, "Failed popping CUDA context: 0x%x\n", (int)cu_res);
371 if ((ret = nvenc_open_session(avctx)) < 0)
374 if ((ret = nvenc_check_capabilities(avctx)) < 0)
377 av_log(avctx, loglevel, "supports NVENC\n");
379 dl_fn->nvenc_device_count++;
381 if (ctx->device == dl_fn->nvenc_device_count - 1 || ctx->device == ANY_DEVICE)
385 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
386 ctx->nvencoder = NULL;
389 dl_fn->cu_ctx_destroy(ctx->cu_context_internal);
390 ctx->cu_context_internal = NULL;
393 return AVERROR(ENOSYS);
396 static av_cold int nvenc_setup_device(AVCodecContext *avctx)
398 NvencContext *ctx = avctx->priv_data;
399 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
401 switch (avctx->codec->id) {
402 case AV_CODEC_ID_H264:
403 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_H264_GUID;
405 case AV_CODEC_ID_HEVC:
406 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_HEVC_GUID;
412 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
414 AVHWFramesContext *frames_ctx;
415 AVCUDADeviceContext *device_hwctx;
418 if (!avctx->hw_frames_ctx)
419 return AVERROR(EINVAL);
421 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
422 device_hwctx = frames_ctx->device_ctx->hwctx;
424 ctx->cu_context = device_hwctx->cuda_ctx;
426 ret = nvenc_open_session(avctx);
430 ret = nvenc_check_capabilities(avctx);
432 av_log(avctx, AV_LOG_FATAL, "Provided device doesn't support required NVENC features\n");
439 int i, nb_devices = 0;
441 if ((dl_fn->cu_init(0)) != CUDA_SUCCESS) {
442 av_log(avctx, AV_LOG_ERROR,
443 "Cannot init CUDA\n");
444 return AVERROR_UNKNOWN;
447 if ((dl_fn->cu_device_get_count(&nb_devices)) != CUDA_SUCCESS) {
448 av_log(avctx, AV_LOG_ERROR,
449 "Cannot enumerate the CUDA devices\n");
450 return AVERROR_UNKNOWN;
454 av_log(avctx, AV_LOG_FATAL, "No CUDA capable devices found\n");
455 return AVERROR_EXTERNAL;
458 av_log(avctx, AV_LOG_VERBOSE, "%d CUDA capable devices found\n", nb_devices);
460 dl_fn->nvenc_device_count = 0;
461 for (i = 0; i < nb_devices; ++i) {
462 if ((nvenc_check_device(avctx, i)) >= 0 && ctx->device != LIST_DEVICES)
466 if (ctx->device == LIST_DEVICES)
469 if (!dl_fn->nvenc_device_count) {
470 av_log(avctx, AV_LOG_FATAL, "No NVENC capable devices found\n");
471 return AVERROR_EXTERNAL;
474 av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->device, dl_fn->nvenc_device_count);
475 return AVERROR(EINVAL);
481 typedef struct GUIDTuple {
486 static void nvenc_map_preset(NvencContext *ctx)
488 GUIDTuple presets[] = {
489 { NV_ENC_PRESET_DEFAULT_GUID },
490 { NV_ENC_PRESET_HQ_GUID, NVENC_TWO_PASSES }, /* slow */
491 { NV_ENC_PRESET_HQ_GUID, NVENC_ONE_PASS }, /* medium */
492 { NV_ENC_PRESET_HP_GUID, NVENC_ONE_PASS }, /* fast */
493 { NV_ENC_PRESET_HP_GUID },
494 { NV_ENC_PRESET_HQ_GUID },
495 { NV_ENC_PRESET_BD_GUID },
496 { NV_ENC_PRESET_LOW_LATENCY_DEFAULT_GUID, NVENC_LOWLATENCY },
497 { NV_ENC_PRESET_LOW_LATENCY_HQ_GUID, NVENC_LOWLATENCY },
498 { NV_ENC_PRESET_LOW_LATENCY_HP_GUID, NVENC_LOWLATENCY },
499 { NV_ENC_PRESET_LOSSLESS_DEFAULT_GUID, NVENC_LOSSLESS },
500 { NV_ENC_PRESET_LOSSLESS_HP_GUID, NVENC_LOSSLESS },
503 GUIDTuple *t = &presets[ctx->preset];
505 ctx->init_encode_params.presetGUID = t->guid;
506 ctx->flags = t->flags;
509 static av_cold void set_constqp(AVCodecContext *avctx)
511 NvencContext *ctx = avctx->priv_data;
512 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
514 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
515 rc->constQP.qpInterB = avctx->global_quality;
516 rc->constQP.qpInterP = avctx->global_quality;
517 rc->constQP.qpIntra = avctx->global_quality;
523 static av_cold void set_vbr(AVCodecContext *avctx)
525 NvencContext *ctx = avctx->priv_data;
526 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
529 if (avctx->qmin >= 0 && avctx->qmax >= 0) {
533 rc->minQP.qpInterB = avctx->qmin;
534 rc->minQP.qpInterP = avctx->qmin;
535 rc->minQP.qpIntra = avctx->qmin;
537 rc->maxQP.qpInterB = avctx->qmax;
538 rc->maxQP.qpInterP = avctx->qmax;
539 rc->maxQP.qpIntra = avctx->qmax;
541 qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin
542 } else if (avctx->qmin >= 0) {
545 rc->minQP.qpInterB = avctx->qmin;
546 rc->minQP.qpInterP = avctx->qmin;
547 rc->minQP.qpIntra = avctx->qmin;
549 qp_inter_p = avctx->qmin;
551 qp_inter_p = 26; // default to 26
554 rc->enableInitialRCQP = 1;
555 rc->initialRCQP.qpInterP = qp_inter_p;
557 if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
558 rc->initialRCQP.qpIntra = av_clip(
559 qp_inter_p * fabs(avctx->i_quant_factor) + avctx->i_quant_offset, 0, 51);
560 rc->initialRCQP.qpInterB = av_clip(
561 qp_inter_p * fabs(avctx->b_quant_factor) + avctx->b_quant_offset, 0, 51);
563 rc->initialRCQP.qpIntra = qp_inter_p;
564 rc->initialRCQP.qpInterB = qp_inter_p;
568 static av_cold void set_lossless(AVCodecContext *avctx)
570 NvencContext *ctx = avctx->priv_data;
571 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
573 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
574 rc->constQP.qpInterB = 0;
575 rc->constQP.qpInterP = 0;
576 rc->constQP.qpIntra = 0;
582 static void nvenc_override_rate_control(AVCodecContext *avctx)
584 NvencContext *ctx = avctx->priv_data;
585 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
588 case NV_ENC_PARAMS_RC_CONSTQP:
589 if (avctx->global_quality <= 0) {
590 av_log(avctx, AV_LOG_WARNING,
591 "The constant quality rate-control requires "
592 "the 'global_quality' option set.\n");
597 case NV_ENC_PARAMS_RC_2_PASS_VBR:
598 case NV_ENC_PARAMS_RC_VBR:
599 if (avctx->qmin < 0 && avctx->qmax < 0) {
600 av_log(avctx, AV_LOG_WARNING,
601 "The variable bitrate rate-control requires "
602 "the 'qmin' and/or 'qmax' option set.\n");
606 case NV_ENC_PARAMS_RC_VBR_MINQP:
607 if (avctx->qmin < 0) {
608 av_log(avctx, AV_LOG_WARNING,
609 "The variable bitrate rate-control requires "
610 "the 'qmin' option set.\n");
616 case NV_ENC_PARAMS_RC_CBR:
617 case NV_ENC_PARAMS_RC_2_PASS_QUALITY:
618 case NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP:
622 rc->rateControlMode = ctx->rc;
625 static av_cold void nvenc_setup_rate_control(AVCodecContext *avctx)
627 NvencContext *ctx = avctx->priv_data;
629 if (avctx->bit_rate > 0) {
630 ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate;
631 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
632 ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate;
635 if (avctx->rc_max_rate > 0)
636 ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
639 if (ctx->flags & NVENC_ONE_PASS)
641 if (ctx->flags & NVENC_TWO_PASSES)
644 if (ctx->twopass < 0)
645 ctx->twopass = (ctx->flags & NVENC_LOWLATENCY) != 0;
649 ctx->rc = NV_ENC_PARAMS_RC_2_PASS_QUALITY;
651 ctx->rc = NV_ENC_PARAMS_RC_CBR;
653 } else if (avctx->global_quality > 0) {
654 ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
655 } else if (ctx->twopass) {
656 ctx->rc = NV_ENC_PARAMS_RC_2_PASS_VBR;
657 } else if (avctx->qmin >= 0 && avctx->qmax >= 0) {
658 ctx->rc = NV_ENC_PARAMS_RC_VBR_MINQP;
662 if (ctx->flags & NVENC_LOSSLESS) {
664 } else if (ctx->rc >= 0) {
665 nvenc_override_rate_control(avctx);
667 ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR;
671 if (avctx->rc_buffer_size > 0) {
672 ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size;
673 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
674 ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate;
678 static av_cold int nvenc_setup_h264_config(AVCodecContext *avctx)
680 NvencContext *ctx = avctx->priv_data;
681 NV_ENC_CONFIG *cc = &ctx->encode_config;
682 NV_ENC_CONFIG_H264 *h264 = &cc->encodeCodecConfig.h264Config;
683 NV_ENC_CONFIG_H264_VUI_PARAMETERS *vui = &h264->h264VUIParameters;
685 vui->colourMatrix = avctx->colorspace;
686 vui->colourPrimaries = avctx->color_primaries;
687 vui->transferCharacteristics = avctx->color_trc;
688 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
689 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
691 vui->colourDescriptionPresentFlag =
692 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
694 vui->videoSignalTypePresentFlag =
695 (vui->colourDescriptionPresentFlag
696 || vui->videoFormat != 5
697 || vui->videoFullRangeFlag != 0);
700 h264->sliceModeData = 1;
702 h264->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
703 h264->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
706 if (avctx->refs >= 0) {
707 /* 0 means "let the hardware decide" */
708 h264->maxNumRefFrames = avctx->refs;
710 if (avctx->gop_size >= 0) {
711 h264->idrPeriod = cc->gopLength;
714 if (IS_CBR(cc->rcParams.rateControlMode)) {
715 h264->outputBufferingPeriodSEI = 1;
716 h264->outputPictureTimingSEI = 1;
719 if (cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_QUALITY ||
720 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP ||
721 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_VBR) {
722 h264->adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE;
723 h264->fmoMode = NV_ENC_H264_FMO_DISABLE;
726 if (ctx->flags & NVENC_LOSSLESS) {
727 h264->qpPrimeYZeroTransformBypassFlag = 1;
729 switch(ctx->profile) {
730 case NV_ENC_H264_PROFILE_BASELINE:
731 cc->profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID;
732 avctx->profile = FF_PROFILE_H264_BASELINE;
734 case NV_ENC_H264_PROFILE_MAIN:
735 cc->profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID;
736 avctx->profile = FF_PROFILE_H264_MAIN;
738 case NV_ENC_H264_PROFILE_HIGH:
739 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID;
740 avctx->profile = FF_PROFILE_H264_HIGH;
742 case NV_ENC_H264_PROFILE_HIGH_444P:
743 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
744 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
749 // force setting profile as high444p if input is AV_PIX_FMT_YUV444P
750 if (ctx->data_pix_fmt == AV_PIX_FMT_YUV444P) {
751 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
752 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
755 h264->chromaFormatIDC = avctx->profile == FF_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1;
757 h264->level = ctx->level;
762 static av_cold int nvenc_setup_hevc_config(AVCodecContext *avctx)
764 NvencContext *ctx = avctx->priv_data;
765 NV_ENC_CONFIG *cc = &ctx->encode_config;
766 NV_ENC_CONFIG_HEVC *hevc = &cc->encodeCodecConfig.hevcConfig;
767 NV_ENC_CONFIG_HEVC_VUI_PARAMETERS *vui = &hevc->hevcVUIParameters;
769 vui->colourMatrix = avctx->colorspace;
770 vui->colourPrimaries = avctx->color_primaries;
771 vui->transferCharacteristics = avctx->color_trc;
772 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
773 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
775 vui->colourDescriptionPresentFlag =
776 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
778 vui->videoSignalTypePresentFlag =
779 (vui->colourDescriptionPresentFlag
780 || vui->videoFormat != 5
781 || vui->videoFullRangeFlag != 0);
784 hevc->sliceModeData = 1;
786 hevc->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
787 hevc->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
790 if (avctx->refs >= 0) {
791 /* 0 means "let the hardware decide" */
792 hevc->maxNumRefFramesInDPB = avctx->refs;
794 if (avctx->gop_size >= 0) {
795 hevc->idrPeriod = cc->gopLength;
798 if (IS_CBR(cc->rcParams.rateControlMode)) {
799 hevc->outputBufferingPeriodSEI = 1;
800 hevc->outputPictureTimingSEI = 1;
803 /* No other profile is supported in the current SDK version 5 */
804 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID;
805 avctx->profile = FF_PROFILE_HEVC_MAIN;
807 hevc->level = ctx->level;
809 hevc->tier = ctx->tier;
814 static av_cold int nvenc_setup_codec_config(AVCodecContext *avctx)
816 switch (avctx->codec->id) {
817 case AV_CODEC_ID_H264:
818 return nvenc_setup_h264_config(avctx);
819 case AV_CODEC_ID_HEVC:
820 return nvenc_setup_hevc_config(avctx);
821 /* Earlier switch/case will return if unknown codec is passed. */
827 static av_cold int nvenc_setup_encoder(AVCodecContext *avctx)
829 NvencContext *ctx = avctx->priv_data;
830 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
831 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
833 NV_ENC_PRESET_CONFIG preset_config = { 0 };
834 NVENCSTATUS nv_status = NV_ENC_SUCCESS;
835 AVCPBProperties *cpb_props;
839 ctx->encode_config.version = NV_ENC_CONFIG_VER;
840 ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER;
842 ctx->init_encode_params.encodeHeight = avctx->height;
843 ctx->init_encode_params.encodeWidth = avctx->width;
845 ctx->init_encode_params.encodeConfig = &ctx->encode_config;
847 nvenc_map_preset(ctx);
849 preset_config.version = NV_ENC_PRESET_CONFIG_VER;
850 preset_config.presetCfg.version = NV_ENC_CONFIG_VER;
852 nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder,
853 ctx->init_encode_params.encodeGUID,
854 ctx->init_encode_params.presetGUID,
856 if (nv_status != NV_ENC_SUCCESS)
857 return nvenc_print_error(avctx, nv_status, "Cannot get the preset configuration");
859 memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config));
861 ctx->encode_config.version = NV_ENC_CONFIG_VER;
863 if (avctx->sample_aspect_ratio.num && avctx->sample_aspect_ratio.den &&
864 (avctx->sample_aspect_ratio.num != 1 || avctx->sample_aspect_ratio.num != 1)) {
866 avctx->width * avctx->sample_aspect_ratio.num,
867 avctx->height * avctx->sample_aspect_ratio.den,
869 ctx->init_encode_params.darHeight = dh;
870 ctx->init_encode_params.darWidth = dw;
872 ctx->init_encode_params.darHeight = avctx->height;
873 ctx->init_encode_params.darWidth = avctx->width;
876 // De-compensate for hardware, dubiously, trying to compensate for
877 // playback at 704 pixel width.
878 if (avctx->width == 720 &&
879 (avctx->height == 480 || avctx->height == 576)) {
881 ctx->init_encode_params.darWidth * 44,
882 ctx->init_encode_params.darHeight * 45,
884 ctx->init_encode_params.darHeight = dh;
885 ctx->init_encode_params.darWidth = dw;
888 ctx->init_encode_params.frameRateNum = avctx->time_base.den;
889 ctx->init_encode_params.frameRateDen = avctx->time_base.num * avctx->ticks_per_frame;
891 ctx->init_encode_params.enableEncodeAsync = 0;
892 ctx->init_encode_params.enablePTD = 1;
894 if (avctx->gop_size > 0) {
895 if (avctx->max_b_frames >= 0) {
896 /* 0 is intra-only, 1 is I/P only, 2 is one B-Frame, 3 two B-frames, and so on. */
897 ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1;
900 ctx->encode_config.gopLength = avctx->gop_size;
901 } else if (avctx->gop_size == 0) {
902 ctx->encode_config.frameIntervalP = 0;
903 ctx->encode_config.gopLength = 1;
906 ctx->initial_pts[0] = AV_NOPTS_VALUE;
907 ctx->initial_pts[1] = AV_NOPTS_VALUE;
909 nvenc_setup_rate_control(avctx);
911 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
912 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD;
914 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME;
917 res = nvenc_setup_codec_config(avctx);
921 nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params);
922 if (nv_status != NV_ENC_SUCCESS) {
923 return nvenc_print_error(avctx, nv_status, "InitializeEncoder failed");
926 if (ctx->encode_config.frameIntervalP > 1)
927 avctx->has_b_frames = 2;
929 if (ctx->encode_config.rcParams.averageBitRate > 0)
930 avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate;
932 cpb_props = ff_add_cpb_side_data(avctx);
934 return AVERROR(ENOMEM);
935 cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate;
936 cpb_props->avg_bitrate = avctx->bit_rate;
937 cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize;
942 static av_cold int nvenc_alloc_surface(AVCodecContext *avctx, int idx)
944 NvencContext *ctx = avctx->priv_data;
945 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
946 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
948 NVENCSTATUS nv_status;
949 NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 };
950 allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER;
952 switch (ctx->data_pix_fmt) {
953 case AV_PIX_FMT_YUV420P:
954 ctx->surfaces[idx].format = NV_ENC_BUFFER_FORMAT_YV12_PL;
957 case AV_PIX_FMT_NV12:
958 ctx->surfaces[idx].format = NV_ENC_BUFFER_FORMAT_NV12_PL;
961 case AV_PIX_FMT_YUV444P:
962 ctx->surfaces[idx].format = NV_ENC_BUFFER_FORMAT_YUV444_PL;
966 av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format\n");
967 return AVERROR(EINVAL);
970 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
971 ctx->surfaces[idx].in_ref = av_frame_alloc();
972 if (!ctx->surfaces[idx].in_ref)
973 return AVERROR(ENOMEM);
975 NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 };
976 allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER;
977 allocSurf.width = (avctx->width + 31) & ~31;
978 allocSurf.height = (avctx->height + 31) & ~31;
979 allocSurf.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
980 allocSurf.bufferFmt = ctx->surfaces[idx].format;
982 nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf);
983 if (nv_status != NV_ENC_SUCCESS) {
984 return nvenc_print_error(avctx, nv_status, "CreateInputBuffer failed");
987 ctx->surfaces[idx].input_surface = allocSurf.inputBuffer;
988 ctx->surfaces[idx].width = allocSurf.width;
989 ctx->surfaces[idx].height = allocSurf.height;
992 ctx->surfaces[idx].lockCount = 0;
994 /* 1MB is large enough to hold most output frames.
995 * NVENC increases this automaticaly if it is not enough. */
996 allocOut.size = 1024 * 1024;
998 allocOut.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
1000 nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut);
1001 if (nv_status != NV_ENC_SUCCESS) {
1002 int err = nvenc_print_error(avctx, nv_status, "CreateBitstreamBuffer failed");
1003 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1004 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[idx].input_surface);
1005 av_frame_free(&ctx->surfaces[idx].in_ref);
1009 ctx->surfaces[idx].output_surface = allocOut.bitstreamBuffer;
1010 ctx->surfaces[idx].size = allocOut.size;
1015 static av_cold int nvenc_setup_surfaces(AVCodecContext *avctx)
1017 NvencContext *ctx = avctx->priv_data;
1019 int num_mbs = ((avctx->width + 15) >> 4) * ((avctx->height + 15) >> 4);
1020 ctx->nb_surfaces = FFMAX((num_mbs >= 8160) ? 32 : 48,
1022 ctx->async_depth = FFMIN(ctx->async_depth, ctx->nb_surfaces - 1);
1025 ctx->surfaces = av_mallocz_array(ctx->nb_surfaces, sizeof(*ctx->surfaces));
1027 return AVERROR(ENOMEM);
1029 ctx->timestamp_list = av_fifo_alloc(ctx->nb_surfaces * sizeof(int64_t));
1030 if (!ctx->timestamp_list)
1031 return AVERROR(ENOMEM);
1032 ctx->output_surface_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1033 if (!ctx->output_surface_queue)
1034 return AVERROR(ENOMEM);
1035 ctx->output_surface_ready_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1036 if (!ctx->output_surface_ready_queue)
1037 return AVERROR(ENOMEM);
1039 for (i = 0; i < ctx->nb_surfaces; i++) {
1040 if ((res = nvenc_alloc_surface(avctx, i)) < 0)
1047 static av_cold int nvenc_setup_extradata(AVCodecContext *avctx)
1049 NvencContext *ctx = avctx->priv_data;
1050 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1051 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1053 NVENCSTATUS nv_status;
1054 uint32_t outSize = 0;
1055 char tmpHeader[256];
1056 NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 };
1057 payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER;
1059 payload.spsppsBuffer = tmpHeader;
1060 payload.inBufferSize = sizeof(tmpHeader);
1061 payload.outSPSPPSPayloadSize = &outSize;
1063 nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload);
1064 if (nv_status != NV_ENC_SUCCESS) {
1065 return nvenc_print_error(avctx, nv_status, "GetSequenceParams failed");
1068 avctx->extradata_size = outSize;
1069 avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE);
1071 if (!avctx->extradata) {
1072 return AVERROR(ENOMEM);
1075 memcpy(avctx->extradata, tmpHeader, outSize);
1080 av_cold int ff_nvenc_encode_close(AVCodecContext *avctx)
1082 NvencContext *ctx = avctx->priv_data;
1083 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1084 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1087 /* the encoder has to be flushed before it can be closed */
1088 if (ctx->nvencoder) {
1089 NV_ENC_PIC_PARAMS params = { .version = NV_ENC_PIC_PARAMS_VER,
1090 .encodePicFlags = NV_ENC_PIC_FLAG_EOS };
1092 p_nvenc->nvEncEncodePicture(ctx->nvencoder, ¶ms);
1095 av_fifo_freep(&ctx->timestamp_list);
1096 av_fifo_freep(&ctx->output_surface_ready_queue);
1097 av_fifo_freep(&ctx->output_surface_queue);
1099 if (ctx->surfaces && avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1100 for (i = 0; i < ctx->nb_surfaces; ++i) {
1101 if (ctx->surfaces[i].input_surface) {
1102 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->surfaces[i].in_map.mappedResource);
1105 for (i = 0; i < ctx->nb_registered_frames; i++) {
1106 if (ctx->registered_frames[i].regptr)
1107 p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
1109 ctx->nb_registered_frames = 0;
1112 if (ctx->surfaces) {
1113 for (i = 0; i < ctx->nb_surfaces; ++i) {
1114 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1115 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[i].input_surface);
1116 av_frame_free(&ctx->surfaces[i].in_ref);
1117 p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->surfaces[i].output_surface);
1120 av_freep(&ctx->surfaces);
1121 ctx->nb_surfaces = 0;
1124 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
1125 ctx->nvencoder = NULL;
1127 if (ctx->cu_context_internal)
1128 dl_fn->cu_ctx_destroy(ctx->cu_context_internal);
1129 ctx->cu_context = ctx->cu_context_internal = NULL;
1132 dlclose(dl_fn->nvenc);
1133 dl_fn->nvenc = NULL;
1135 dl_fn->nvenc_device_count = 0;
1139 dlclose(dl_fn->cuda);
1143 dl_fn->cu_init = NULL;
1144 dl_fn->cu_device_get_count = NULL;
1145 dl_fn->cu_device_get = NULL;
1146 dl_fn->cu_device_get_name = NULL;
1147 dl_fn->cu_device_compute_capability = NULL;
1148 dl_fn->cu_ctx_create = NULL;
1149 dl_fn->cu_ctx_pop_current = NULL;
1150 dl_fn->cu_ctx_destroy = NULL;
1152 av_log(avctx, AV_LOG_VERBOSE, "Nvenc unloaded\n");
1157 av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
1159 NvencContext *ctx = avctx->priv_data;
1162 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1163 AVHWFramesContext *frames_ctx;
1164 if (!avctx->hw_frames_ctx) {
1165 av_log(avctx, AV_LOG_ERROR,
1166 "hw_frames_ctx must be set when using GPU frames as input\n");
1167 return AVERROR(EINVAL);
1169 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
1170 ctx->data_pix_fmt = frames_ctx->sw_format;
1172 ctx->data_pix_fmt = avctx->pix_fmt;
1175 if ((ret = nvenc_load_libraries(avctx)) < 0)
1178 if ((ret = nvenc_setup_device(avctx)) < 0)
1181 if ((ret = nvenc_setup_encoder(avctx)) < 0)
1184 if ((ret = nvenc_setup_surfaces(avctx)) < 0)
1187 if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) {
1188 if ((ret = nvenc_setup_extradata(avctx)) < 0)
1195 static NvencSurface *get_free_frame(NvencContext *ctx)
1199 for (i = 0; i < ctx->nb_surfaces; ++i) {
1200 if (!ctx->surfaces[i].lockCount) {
1201 ctx->surfaces[i].lockCount = 1;
1202 return &ctx->surfaces[i];
1209 static int nvenc_copy_frame(AVCodecContext *avctx, NvencSurface *inSurf,
1210 NV_ENC_LOCK_INPUT_BUFFER *lockBufferParams, const AVFrame *frame)
1212 uint8_t *buf = lockBufferParams->bufferDataPtr;
1213 int off = inSurf->height * lockBufferParams->pitch;
1215 if (frame->format == AV_PIX_FMT_YUV420P) {
1216 av_image_copy_plane(buf, lockBufferParams->pitch,
1217 frame->data[0], frame->linesize[0],
1218 avctx->width, avctx->height);
1222 av_image_copy_plane(buf, lockBufferParams->pitch >> 1,
1223 frame->data[2], frame->linesize[2],
1224 avctx->width >> 1, avctx->height >> 1);
1228 av_image_copy_plane(buf, lockBufferParams->pitch >> 1,
1229 frame->data[1], frame->linesize[1],
1230 avctx->width >> 1, avctx->height >> 1);
1231 } else if (frame->format == AV_PIX_FMT_NV12) {
1232 av_image_copy_plane(buf, lockBufferParams->pitch,
1233 frame->data[0], frame->linesize[0],
1234 avctx->width, avctx->height);
1238 av_image_copy_plane(buf, lockBufferParams->pitch,
1239 frame->data[1], frame->linesize[1],
1240 avctx->width, avctx->height >> 1);
1241 } else if (frame->format == AV_PIX_FMT_YUV444P) {
1242 av_image_copy_plane(buf, lockBufferParams->pitch,
1243 frame->data[0], frame->linesize[0],
1244 avctx->width, avctx->height);
1248 av_image_copy_plane(buf, lockBufferParams->pitch,
1249 frame->data[1], frame->linesize[1],
1250 avctx->width, avctx->height);
1254 av_image_copy_plane(buf, lockBufferParams->pitch,
1255 frame->data[2], frame->linesize[2],
1256 avctx->width, avctx->height);
1258 av_log(avctx, AV_LOG_FATAL, "Invalid pixel format!\n");
1259 return AVERROR(EINVAL);
1265 static int nvenc_find_free_reg_resource(AVCodecContext *avctx)
1267 NvencContext *ctx = avctx->priv_data;
1268 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1269 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1273 if (ctx->nb_registered_frames == FF_ARRAY_ELEMS(ctx->registered_frames)) {
1274 for (i = 0; i < ctx->nb_registered_frames; i++) {
1275 if (!ctx->registered_frames[i].mapped) {
1276 if (ctx->registered_frames[i].regptr) {
1277 p_nvenc->nvEncUnregisterResource(ctx->nvencoder,
1278 ctx->registered_frames[i].regptr);
1279 ctx->registered_frames[i].regptr = NULL;
1285 return ctx->nb_registered_frames++;
1288 av_log(avctx, AV_LOG_ERROR, "Too many registered CUDA frames\n");
1289 return AVERROR(ENOMEM);
1292 static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
1294 NvencContext *ctx = avctx->priv_data;
1295 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1296 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1298 AVHWFramesContext *frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
1299 NV_ENC_REGISTER_RESOURCE reg;
1302 for (i = 0; i < ctx->nb_registered_frames; i++) {
1303 if (ctx->registered_frames[i].ptr == (CUdeviceptr)frame->data[0])
1307 idx = nvenc_find_free_reg_resource(avctx);
1311 reg.version = NV_ENC_REGISTER_RESOURCE_VER;
1312 reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_CUDADEVICEPTR;
1313 reg.width = frames_ctx->width;
1314 reg.height = frames_ctx->height;
1315 reg.bufferFormat = ctx->surfaces[0].format;
1316 reg.pitch = frame->linesize[0];
1317 reg.resourceToRegister = frame->data[0];
1319 ret = p_nvenc->nvEncRegisterResource(ctx->nvencoder, ®);
1320 if (ret != NV_ENC_SUCCESS) {
1321 nvenc_print_error(avctx, ret, "Error registering an input resource");
1322 return AVERROR_UNKNOWN;
1325 ctx->registered_frames[idx].ptr = (CUdeviceptr)frame->data[0];
1326 ctx->registered_frames[idx].regptr = reg.registeredResource;
1330 static int nvenc_upload_frame(AVCodecContext *avctx, const AVFrame *frame,
1331 NvencSurface *nvenc_frame)
1333 NvencContext *ctx = avctx->priv_data;
1334 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1335 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1338 NVENCSTATUS nv_status;
1340 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1341 int reg_idx = nvenc_register_frame(avctx, frame);
1343 av_log(avctx, AV_LOG_ERROR, "Could not register an input CUDA frame\n");
1347 res = av_frame_ref(nvenc_frame->in_ref, frame);
1351 nvenc_frame->in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER;
1352 nvenc_frame->in_map.registeredResource = ctx->registered_frames[reg_idx].regptr;
1353 nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &nvenc_frame->in_map);
1354 if (nv_status != NV_ENC_SUCCESS) {
1355 av_frame_unref(nvenc_frame->in_ref);
1356 return nvenc_print_error(avctx, nv_status, "Error mapping an input resource");
1359 ctx->registered_frames[reg_idx].mapped = 1;
1360 nvenc_frame->reg_idx = reg_idx;
1361 nvenc_frame->input_surface = nvenc_frame->in_map.mappedResource;
1364 NV_ENC_LOCK_INPUT_BUFFER lockBufferParams = { 0 };
1366 lockBufferParams.version = NV_ENC_LOCK_INPUT_BUFFER_VER;
1367 lockBufferParams.inputBuffer = nvenc_frame->input_surface;
1369 nv_status = p_nvenc->nvEncLockInputBuffer(ctx->nvencoder, &lockBufferParams);
1370 if (nv_status != NV_ENC_SUCCESS) {
1371 return nvenc_print_error(avctx, nv_status, "Failed locking nvenc input buffer");
1374 res = nvenc_copy_frame(avctx, nvenc_frame, &lockBufferParams, frame);
1376 nv_status = p_nvenc->nvEncUnlockInputBuffer(ctx->nvencoder, nvenc_frame->input_surface);
1377 if (nv_status != NV_ENC_SUCCESS) {
1378 return nvenc_print_error(avctx, nv_status, "Failed unlocking input buffer!");
1385 static void nvenc_codec_specific_pic_params(AVCodecContext *avctx,
1386 NV_ENC_PIC_PARAMS *params)
1388 NvencContext *ctx = avctx->priv_data;
1390 switch (avctx->codec->id) {
1391 case AV_CODEC_ID_H264:
1392 params->codecPicParams.h264PicParams.sliceMode =
1393 ctx->encode_config.encodeCodecConfig.h264Config.sliceMode;
1394 params->codecPicParams.h264PicParams.sliceModeData =
1395 ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1397 case AV_CODEC_ID_HEVC:
1398 params->codecPicParams.hevcPicParams.sliceMode =
1399 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode;
1400 params->codecPicParams.hevcPicParams.sliceModeData =
1401 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1406 static inline void timestamp_queue_enqueue(AVFifoBuffer* queue, int64_t timestamp)
1408 av_fifo_generic_write(queue, ×tamp, sizeof(timestamp), NULL);
1411 static inline int64_t timestamp_queue_dequeue(AVFifoBuffer* queue)
1413 int64_t timestamp = AV_NOPTS_VALUE;
1414 if (av_fifo_size(queue) > 0)
1415 av_fifo_generic_read(queue, ×tamp, sizeof(timestamp), NULL);
1420 static int nvenc_set_timestamp(AVCodecContext *avctx,
1421 NV_ENC_LOCK_BITSTREAM *params,
1424 NvencContext *ctx = avctx->priv_data;
1426 pkt->pts = params->outputTimeStamp;
1428 /* generate the first dts by linearly extrapolating the
1429 * first two pts values to the past */
1430 if (avctx->max_b_frames > 0 && !ctx->first_packet_output &&
1431 ctx->initial_pts[1] != AV_NOPTS_VALUE) {
1432 int64_t ts0 = ctx->initial_pts[0], ts1 = ctx->initial_pts[1];
1435 if ((ts0 < 0 && ts1 > INT64_MAX + ts0) ||
1436 (ts0 > 0 && ts1 < INT64_MIN + ts0))
1437 return AVERROR(ERANGE);
1440 if ((delta < 0 && ts0 > INT64_MAX + delta) ||
1441 (delta > 0 && ts0 < INT64_MIN + delta))
1442 return AVERROR(ERANGE);
1443 pkt->dts = ts0 - delta;
1445 ctx->first_packet_output = 1;
1449 pkt->dts = timestamp_queue_dequeue(ctx->timestamp_list);
1454 static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf)
1456 NvencContext *ctx = avctx->priv_data;
1457 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1458 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1460 uint32_t slice_mode_data;
1461 uint32_t *slice_offsets;
1462 NV_ENC_LOCK_BITSTREAM lock_params = { 0 };
1463 NVENCSTATUS nv_status;
1466 enum AVPictureType pict_type;
1468 switch (avctx->codec->id) {
1469 case AV_CODEC_ID_H264:
1470 slice_mode_data = ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1472 case AV_CODEC_ID_H265:
1473 slice_mode_data = ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1476 av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n");
1477 res = AVERROR(EINVAL);
1480 slice_offsets = av_mallocz(slice_mode_data * sizeof(*slice_offsets));
1485 lock_params.version = NV_ENC_LOCK_BITSTREAM_VER;
1487 lock_params.doNotWait = 0;
1488 lock_params.outputBitstream = tmpoutsurf->output_surface;
1489 lock_params.sliceOffsets = slice_offsets;
1491 nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params);
1492 if (nv_status != NV_ENC_SUCCESS) {
1493 res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer");
1497 if (res = ff_alloc_packet2(avctx, pkt, lock_params.bitstreamSizeInBytes,0)) {
1498 p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1502 memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes);
1504 nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1505 if (nv_status != NV_ENC_SUCCESS)
1506 nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open");
1509 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1510 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, tmpoutsurf->in_map.mappedResource);
1511 av_frame_unref(tmpoutsurf->in_ref);
1512 ctx->registered_frames[tmpoutsurf->reg_idx].mapped = 0;
1514 tmpoutsurf->input_surface = NULL;
1517 switch (lock_params.pictureType) {
1518 case NV_ENC_PIC_TYPE_IDR:
1519 pkt->flags |= AV_PKT_FLAG_KEY;
1520 case NV_ENC_PIC_TYPE_I:
1521 pict_type = AV_PICTURE_TYPE_I;
1523 case NV_ENC_PIC_TYPE_P:
1524 pict_type = AV_PICTURE_TYPE_P;
1526 case NV_ENC_PIC_TYPE_B:
1527 pict_type = AV_PICTURE_TYPE_B;
1529 case NV_ENC_PIC_TYPE_BI:
1530 pict_type = AV_PICTURE_TYPE_BI;
1533 av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n");
1534 av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n");
1535 res = AVERROR_EXTERNAL;
1539 #if FF_API_CODED_FRAME
1540 FF_DISABLE_DEPRECATION_WARNINGS
1541 avctx->coded_frame->pict_type = pict_type;
1542 FF_ENABLE_DEPRECATION_WARNINGS
1545 ff_side_data_set_encoder_stats(pkt,
1546 (lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type);
1548 res = nvenc_set_timestamp(avctx, &lock_params, pkt);
1552 av_free(slice_offsets);
1557 timestamp_queue_dequeue(ctx->timestamp_list);
1560 av_free(slice_offsets);
1565 static int output_ready(AVCodecContext *avctx, int flush)
1567 NvencContext *ctx = avctx->priv_data;
1568 int nb_ready, nb_pending;
1570 /* when B-frames are enabled, we wait for two initial timestamps to
1571 * calculate the first dts */
1572 if (!flush && avctx->max_b_frames > 0 &&
1573 (ctx->initial_pts[0] == AV_NOPTS_VALUE || ctx->initial_pts[1] == AV_NOPTS_VALUE))
1576 nb_ready = av_fifo_size(ctx->output_surface_ready_queue) / sizeof(NvencSurface*);
1577 nb_pending = av_fifo_size(ctx->output_surface_queue) / sizeof(NvencSurface*);
1579 return nb_ready > 0;
1580 return (nb_ready > 0) && (nb_ready + nb_pending >= ctx->async_depth);
1583 int ff_nvenc_encode_frame(AVCodecContext *avctx, AVPacket *pkt,
1584 const AVFrame *frame, int *got_packet)
1586 NVENCSTATUS nv_status;
1587 NvencSurface *tmpoutsurf, *inSurf;
1590 NvencContext *ctx = avctx->priv_data;
1591 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1592 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1594 NV_ENC_PIC_PARAMS pic_params = { 0 };
1595 pic_params.version = NV_ENC_PIC_PARAMS_VER;
1598 inSurf = get_free_frame(ctx);
1600 av_log(avctx, AV_LOG_ERROR, "No free surfaces\n");
1604 res = nvenc_upload_frame(avctx, frame, inSurf);
1606 inSurf->lockCount = 0;
1610 pic_params.inputBuffer = inSurf->input_surface;
1611 pic_params.bufferFmt = inSurf->format;
1612 pic_params.inputWidth = avctx->width;
1613 pic_params.inputHeight = avctx->height;
1614 pic_params.outputBitstream = inSurf->output_surface;
1616 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
1617 if (frame->top_field_first)
1618 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM;
1620 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP;
1622 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
1625 pic_params.encodePicFlags = 0;
1626 pic_params.inputTimeStamp = frame->pts;
1628 nvenc_codec_specific_pic_params(avctx, &pic_params);
1630 pic_params.encodePicFlags = NV_ENC_PIC_FLAG_EOS;
1633 nv_status = p_nvenc->nvEncEncodePicture(ctx->nvencoder, &pic_params);
1634 if (nv_status != NV_ENC_SUCCESS &&
1635 nv_status != NV_ENC_ERR_NEED_MORE_INPUT)
1636 return nvenc_print_error(avctx, nv_status, "EncodePicture failed!");
1639 av_fifo_generic_write(ctx->output_surface_queue, &inSurf, sizeof(inSurf), NULL);
1640 timestamp_queue_enqueue(ctx->timestamp_list, frame->pts);
1642 if (ctx->initial_pts[0] == AV_NOPTS_VALUE)
1643 ctx->initial_pts[0] = frame->pts;
1644 else if (ctx->initial_pts[1] == AV_NOPTS_VALUE)
1645 ctx->initial_pts[1] = frame->pts;
1648 /* all the pending buffers are now ready for output */
1649 if (nv_status == NV_ENC_SUCCESS) {
1650 while (av_fifo_size(ctx->output_surface_queue) > 0) {
1651 av_fifo_generic_read(ctx->output_surface_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1652 av_fifo_generic_write(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1656 if (output_ready(avctx, !frame)) {
1657 av_fifo_generic_read(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1659 res = process_output_surface(avctx, pkt, tmpoutsurf);
1664 av_assert0(tmpoutsurf->lockCount);
1665 tmpoutsurf->lockCount--;