2 * H.264/HEVC hardware encoding using nvidia nvenc
3 * Copyright (c) 2016 Timo Rothenpieler <timo@rothenpieler.org>
5 * This file is part of FFmpeg.
7 * FFmpeg is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * FFmpeg is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with FFmpeg; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
26 #include "libavutil/hwcontext_cuda.h"
27 #include "libavutil/hwcontext.h"
28 #include "libavutil/imgutils.h"
29 #include "libavutil/avassert.h"
30 #include "libavutil/mem.h"
31 #include "libavutil/pixdesc.h"
34 #define NVENC_CAP 0x30
35 #define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR || \
36 rc == NV_ENC_PARAMS_RC_2_PASS_QUALITY || \
37 rc == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP)
39 const enum AVPixelFormat ff_nvenc_pix_fmts[] = {
51 #define IS_10BIT(pix_fmt) (pix_fmt == AV_PIX_FMT_P010 || \
52 pix_fmt == AV_PIX_FMT_YUV444P16)
54 #define IS_YUV444(pix_fmt) (pix_fmt == AV_PIX_FMT_YUV444P || \
55 pix_fmt == AV_PIX_FMT_YUV444P16)
62 { NV_ENC_SUCCESS, 0, "success" },
63 { NV_ENC_ERR_NO_ENCODE_DEVICE, AVERROR(ENOENT), "no encode device" },
64 { NV_ENC_ERR_UNSUPPORTED_DEVICE, AVERROR(ENOSYS), "unsupported device" },
65 { NV_ENC_ERR_INVALID_ENCODERDEVICE, AVERROR(EINVAL), "invalid encoder device" },
66 { NV_ENC_ERR_INVALID_DEVICE, AVERROR(EINVAL), "invalid device" },
67 { NV_ENC_ERR_DEVICE_NOT_EXIST, AVERROR(EIO), "device does not exist" },
68 { NV_ENC_ERR_INVALID_PTR, AVERROR(EFAULT), "invalid ptr" },
69 { NV_ENC_ERR_INVALID_EVENT, AVERROR(EINVAL), "invalid event" },
70 { NV_ENC_ERR_INVALID_PARAM, AVERROR(EINVAL), "invalid param" },
71 { NV_ENC_ERR_INVALID_CALL, AVERROR(EINVAL), "invalid call" },
72 { NV_ENC_ERR_OUT_OF_MEMORY, AVERROR(ENOMEM), "out of memory" },
73 { NV_ENC_ERR_ENCODER_NOT_INITIALIZED, AVERROR(EINVAL), "encoder not initialized" },
74 { NV_ENC_ERR_UNSUPPORTED_PARAM, AVERROR(ENOSYS), "unsupported param" },
75 { NV_ENC_ERR_LOCK_BUSY, AVERROR(EAGAIN), "lock busy" },
76 { NV_ENC_ERR_NOT_ENOUGH_BUFFER, AVERROR_BUFFER_TOO_SMALL, "not enough buffer"},
77 { NV_ENC_ERR_INVALID_VERSION, AVERROR(EINVAL), "invalid version" },
78 { NV_ENC_ERR_MAP_FAILED, AVERROR(EIO), "map failed" },
79 { NV_ENC_ERR_NEED_MORE_INPUT, AVERROR(EAGAIN), "need more input" },
80 { NV_ENC_ERR_ENCODER_BUSY, AVERROR(EAGAIN), "encoder busy" },
81 { NV_ENC_ERR_EVENT_NOT_REGISTERD, AVERROR(EBADF), "event not registered" },
82 { NV_ENC_ERR_GENERIC, AVERROR_UNKNOWN, "generic error" },
83 { NV_ENC_ERR_INCOMPATIBLE_CLIENT_KEY, AVERROR(EINVAL), "incompatible client key" },
84 { NV_ENC_ERR_UNIMPLEMENTED, AVERROR(ENOSYS), "unimplemented" },
85 { NV_ENC_ERR_RESOURCE_REGISTER_FAILED, AVERROR(EIO), "resource register failed" },
86 { NV_ENC_ERR_RESOURCE_NOT_REGISTERED, AVERROR(EBADF), "resource not registered" },
87 { NV_ENC_ERR_RESOURCE_NOT_MAPPED, AVERROR(EBADF), "resource not mapped" },
90 static int nvenc_map_error(NVENCSTATUS err, const char **desc)
93 for (i = 0; i < FF_ARRAY_ELEMS(nvenc_errors); i++) {
94 if (nvenc_errors[i].nverr == err) {
96 *desc = nvenc_errors[i].desc;
97 return nvenc_errors[i].averr;
101 *desc = "unknown error";
102 return AVERROR_UNKNOWN;
105 static int nvenc_print_error(void *log_ctx, NVENCSTATUS err,
106 const char *error_string)
110 ret = nvenc_map_error(err, &desc);
111 av_log(log_ctx, AV_LOG_ERROR, "%s: %s (%d)\n", error_string, desc, err);
115 static av_cold int nvenc_load_libraries(AVCodecContext *avctx)
117 NvencContext *ctx = avctx->priv_data;
118 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
120 uint32_t nvenc_max_ver;
123 ret = cuda_load_functions(&dl_fn->cuda_dl);
127 ret = nvenc_load_functions(&dl_fn->nvenc_dl);
131 err = dl_fn->nvenc_dl->NvEncodeAPIGetMaxSupportedVersion(&nvenc_max_ver);
132 if (err != NV_ENC_SUCCESS)
133 return nvenc_print_error(avctx, err, "Failed to query nvenc max version");
135 av_log(avctx, AV_LOG_VERBOSE, "Loaded Nvenc version %d.%d\n", nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
137 if ((NVENCAPI_MAJOR_VERSION << 4 | NVENCAPI_MINOR_VERSION) > nvenc_max_ver) {
138 av_log(avctx, AV_LOG_ERROR, "Driver does not support the required nvenc API version. "
139 "Required: %d.%d Found: %d.%d\n",
140 NVENCAPI_MAJOR_VERSION, NVENCAPI_MINOR_VERSION,
141 nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
142 return AVERROR(ENOSYS);
145 dl_fn->nvenc_funcs.version = NV_ENCODE_API_FUNCTION_LIST_VER;
147 err = dl_fn->nvenc_dl->NvEncodeAPICreateInstance(&dl_fn->nvenc_funcs);
148 if (err != NV_ENC_SUCCESS)
149 return nvenc_print_error(avctx, err, "Failed to create nvenc instance");
151 av_log(avctx, AV_LOG_VERBOSE, "Nvenc initialized successfully\n");
156 static av_cold int nvenc_open_session(AVCodecContext *avctx)
158 NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS params = { 0 };
159 NvencContext *ctx = avctx->priv_data;
160 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
163 params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER;
164 params.apiVersion = NVENCAPI_VERSION;
165 params.device = ctx->cu_context;
166 params.deviceType = NV_ENC_DEVICE_TYPE_CUDA;
168 ret = p_nvenc->nvEncOpenEncodeSessionEx(¶ms, &ctx->nvencoder);
169 if (ret != NV_ENC_SUCCESS) {
170 ctx->nvencoder = NULL;
171 return nvenc_print_error(avctx, ret, "OpenEncodeSessionEx failed");
177 static int nvenc_check_codec_support(AVCodecContext *avctx)
179 NvencContext *ctx = avctx->priv_data;
180 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
181 int i, ret, count = 0;
184 ret = p_nvenc->nvEncGetEncodeGUIDCount(ctx->nvencoder, &count);
186 if (ret != NV_ENC_SUCCESS || !count)
187 return AVERROR(ENOSYS);
189 guids = av_malloc(count * sizeof(GUID));
191 return AVERROR(ENOMEM);
193 ret = p_nvenc->nvEncGetEncodeGUIDs(ctx->nvencoder, guids, count, &count);
194 if (ret != NV_ENC_SUCCESS) {
195 ret = AVERROR(ENOSYS);
199 ret = AVERROR(ENOSYS);
200 for (i = 0; i < count; i++) {
201 if (!memcmp(&guids[i], &ctx->init_encode_params.encodeGUID, sizeof(*guids))) {
213 static int nvenc_check_cap(AVCodecContext *avctx, NV_ENC_CAPS cap)
215 NvencContext *ctx = avctx->priv_data;
216 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
217 NV_ENC_CAPS_PARAM params = { 0 };
220 params.version = NV_ENC_CAPS_PARAM_VER;
221 params.capsToQuery = cap;
223 ret = p_nvenc->nvEncGetEncodeCaps(ctx->nvencoder, ctx->init_encode_params.encodeGUID, ¶ms, &val);
225 if (ret == NV_ENC_SUCCESS)
230 static int nvenc_check_capabilities(AVCodecContext *avctx)
232 NvencContext *ctx = avctx->priv_data;
235 ret = nvenc_check_codec_support(avctx);
237 av_log(avctx, AV_LOG_VERBOSE, "Codec not supported\n");
241 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_YUV444_ENCODE);
242 if (IS_YUV444(ctx->data_pix_fmt) && ret <= 0) {
243 av_log(avctx, AV_LOG_VERBOSE, "YUV444P not supported\n");
244 return AVERROR(ENOSYS);
247 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOSSLESS_ENCODE);
248 if (ctx->preset >= PRESET_LOSSLESS_DEFAULT && ret <= 0) {
249 av_log(avctx, AV_LOG_VERBOSE, "Lossless encoding not supported\n");
250 return AVERROR(ENOSYS);
253 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_WIDTH_MAX);
254 if (ret < avctx->width) {
255 av_log(avctx, AV_LOG_VERBOSE, "Width %d exceeds %d\n",
257 return AVERROR(ENOSYS);
260 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_HEIGHT_MAX);
261 if (ret < avctx->height) {
262 av_log(avctx, AV_LOG_VERBOSE, "Height %d exceeds %d\n",
264 return AVERROR(ENOSYS);
267 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_NUM_MAX_BFRAMES);
268 if (ret < avctx->max_b_frames) {
269 av_log(avctx, AV_LOG_VERBOSE, "Max B-frames %d exceed %d\n",
270 avctx->max_b_frames, ret);
272 return AVERROR(ENOSYS);
275 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_FIELD_ENCODING);
276 if (ret < 1 && avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
277 av_log(avctx, AV_LOG_VERBOSE,
278 "Interlaced encoding is not supported. Supported level: %d\n",
280 return AVERROR(ENOSYS);
283 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_10BIT_ENCODE);
284 if (IS_10BIT(ctx->data_pix_fmt) && ret <= 0) {
285 av_log(avctx, AV_LOG_VERBOSE, "10 bit encode not supported\n");
286 return AVERROR(ENOSYS);
289 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOOKAHEAD);
290 if (ctx->rc_lookahead > 0 && ret <= 0) {
291 av_log(avctx, AV_LOG_VERBOSE, "RC lookahead not supported\n");
292 return AVERROR(ENOSYS);
295 ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_TEMPORAL_AQ);
296 if (ctx->temporal_aq > 0 && ret <= 0) {
297 av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ not supported\n");
298 return AVERROR(ENOSYS);
304 static av_cold int nvenc_check_device(AVCodecContext *avctx, int idx)
306 NvencContext *ctx = avctx->priv_data;
307 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
308 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
309 char name[128] = { 0};
310 int major, minor, ret;
314 int loglevel = AV_LOG_VERBOSE;
316 if (ctx->device == LIST_DEVICES)
317 loglevel = AV_LOG_INFO;
319 cu_res = dl_fn->cuda_dl->cuDeviceGet(&cu_device, idx);
320 if (cu_res != CUDA_SUCCESS) {
321 av_log(avctx, AV_LOG_ERROR,
322 "Cannot access the CUDA device %d\n",
327 cu_res = dl_fn->cuda_dl->cuDeviceGetName(name, sizeof(name), cu_device);
328 if (cu_res != CUDA_SUCCESS) {
329 av_log(avctx, AV_LOG_ERROR, "cuDeviceGetName failed on device %d\n", idx);
333 cu_res = dl_fn->cuda_dl->cuDeviceComputeCapability(&major, &minor, cu_device);
334 if (cu_res != CUDA_SUCCESS) {
335 av_log(avctx, AV_LOG_ERROR, "cuDeviceComputeCapability failed on device %d\n", idx);
339 av_log(avctx, loglevel, "[ GPU #%d - < %s > has Compute SM %d.%d ]\n", idx, name, major, minor);
340 if (((major << 4) | minor) < NVENC_CAP) {
341 av_log(avctx, loglevel, "does not support NVENC\n");
345 if (ctx->device != idx && ctx->device != ANY_DEVICE)
348 cu_res = dl_fn->cuda_dl->cuCtxCreate(&ctx->cu_context_internal, 0, cu_device);
349 if (cu_res != CUDA_SUCCESS) {
350 av_log(avctx, AV_LOG_FATAL, "Failed creating CUDA context for NVENC: 0x%x\n", (int)cu_res);
354 ctx->cu_context = ctx->cu_context_internal;
356 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
357 if (cu_res != CUDA_SUCCESS) {
358 av_log(avctx, AV_LOG_FATAL, "Failed popping CUDA context: 0x%x\n", (int)cu_res);
362 if ((ret = nvenc_open_session(avctx)) < 0)
365 if ((ret = nvenc_check_capabilities(avctx)) < 0)
368 av_log(avctx, loglevel, "supports NVENC\n");
370 dl_fn->nvenc_device_count++;
372 if (ctx->device == idx || ctx->device == ANY_DEVICE)
376 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
377 ctx->nvencoder = NULL;
380 dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
381 ctx->cu_context_internal = NULL;
384 return AVERROR(ENOSYS);
387 static av_cold int nvenc_setup_device(AVCodecContext *avctx)
389 NvencContext *ctx = avctx->priv_data;
390 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
392 switch (avctx->codec->id) {
393 case AV_CODEC_ID_H264:
394 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_H264_GUID;
396 case AV_CODEC_ID_HEVC:
397 ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_HEVC_GUID;
403 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
404 AVHWFramesContext *frames_ctx;
405 AVCUDADeviceContext *device_hwctx;
408 if (!avctx->hw_frames_ctx)
409 return AVERROR(EINVAL);
411 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
412 device_hwctx = frames_ctx->device_ctx->hwctx;
414 ctx->cu_context = device_hwctx->cuda_ctx;
416 ret = nvenc_open_session(avctx);
420 ret = nvenc_check_capabilities(avctx);
422 av_log(avctx, AV_LOG_FATAL, "Provided device doesn't support required NVENC features\n");
426 int i, nb_devices = 0;
428 if ((dl_fn->cuda_dl->cuInit(0)) != CUDA_SUCCESS) {
429 av_log(avctx, AV_LOG_ERROR,
430 "Cannot init CUDA\n");
431 return AVERROR_UNKNOWN;
434 if ((dl_fn->cuda_dl->cuDeviceGetCount(&nb_devices)) != CUDA_SUCCESS) {
435 av_log(avctx, AV_LOG_ERROR,
436 "Cannot enumerate the CUDA devices\n");
437 return AVERROR_UNKNOWN;
441 av_log(avctx, AV_LOG_FATAL, "No CUDA capable devices found\n");
442 return AVERROR_EXTERNAL;
445 av_log(avctx, AV_LOG_VERBOSE, "%d CUDA capable devices found\n", nb_devices);
447 dl_fn->nvenc_device_count = 0;
448 for (i = 0; i < nb_devices; ++i) {
449 if ((nvenc_check_device(avctx, i)) >= 0 && ctx->device != LIST_DEVICES)
453 if (ctx->device == LIST_DEVICES)
456 if (!dl_fn->nvenc_device_count) {
457 av_log(avctx, AV_LOG_FATAL, "No NVENC capable devices found\n");
458 return AVERROR_EXTERNAL;
461 av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->device, nb_devices);
462 return AVERROR(EINVAL);
468 typedef struct GUIDTuple {
473 #define PRESET_ALIAS(alias, name, ...) \
474 [PRESET_ ## alias] = { NV_ENC_PRESET_ ## name ## _GUID, __VA_ARGS__ }
476 #define PRESET(name, ...) PRESET_ALIAS(name, name, __VA_ARGS__)
478 static void nvenc_map_preset(NvencContext *ctx)
480 GUIDTuple presets[] = {
485 PRESET_ALIAS(SLOW, HQ, NVENC_TWO_PASSES),
486 PRESET_ALIAS(MEDIUM, HQ, NVENC_ONE_PASS),
487 PRESET_ALIAS(FAST, HP, NVENC_ONE_PASS),
488 PRESET(LOW_LATENCY_DEFAULT, NVENC_LOWLATENCY),
489 PRESET(LOW_LATENCY_HP, NVENC_LOWLATENCY),
490 PRESET(LOW_LATENCY_HQ, NVENC_LOWLATENCY),
491 PRESET(LOSSLESS_DEFAULT, NVENC_LOSSLESS),
492 PRESET(LOSSLESS_HP, NVENC_LOSSLESS),
495 GUIDTuple *t = &presets[ctx->preset];
497 ctx->init_encode_params.presetGUID = t->guid;
498 ctx->flags = t->flags;
504 static av_cold void set_constqp(AVCodecContext *avctx)
506 NvencContext *ctx = avctx->priv_data;
507 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
509 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
511 if (ctx->init_qp_p >= 0) {
512 rc->constQP.qpInterP = ctx->init_qp_p;
513 if (ctx->init_qp_i >= 0 && ctx->init_qp_b >= 0) {
514 rc->constQP.qpIntra = ctx->init_qp_i;
515 rc->constQP.qpInterB = ctx->init_qp_b;
516 } else if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
517 rc->constQP.qpIntra = av_clip(
518 rc->constQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
519 rc->constQP.qpInterB = av_clip(
520 rc->constQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
522 rc->constQP.qpIntra = rc->constQP.qpInterP;
523 rc->constQP.qpInterB = rc->constQP.qpInterP;
525 } else if (avctx->global_quality > 0) {
526 rc->constQP.qpInterP = avctx->global_quality;
527 rc->constQP.qpInterB = avctx->global_quality;
528 rc->constQP.qpIntra = avctx->global_quality;
535 static av_cold void set_vbr(AVCodecContext *avctx)
537 NvencContext *ctx = avctx->priv_data;
538 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
541 if (avctx->qmin >= 0 && avctx->qmax >= 0) {
545 rc->minQP.qpInterB = avctx->qmin;
546 rc->minQP.qpInterP = avctx->qmin;
547 rc->minQP.qpIntra = avctx->qmin;
549 rc->maxQP.qpInterB = avctx->qmax;
550 rc->maxQP.qpInterP = avctx->qmax;
551 rc->maxQP.qpIntra = avctx->qmax;
553 qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin
554 } else if (avctx->qmin >= 0) {
557 rc->minQP.qpInterB = avctx->qmin;
558 rc->minQP.qpInterP = avctx->qmin;
559 rc->minQP.qpIntra = avctx->qmin;
561 qp_inter_p = avctx->qmin;
563 qp_inter_p = 26; // default to 26
566 rc->enableInitialRCQP = 1;
568 if (ctx->init_qp_p < 0) {
569 rc->initialRCQP.qpInterP = qp_inter_p;
571 rc->initialRCQP.qpInterP = ctx->init_qp_p;
574 if (ctx->init_qp_i < 0) {
575 if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
576 rc->initialRCQP.qpIntra = av_clip(
577 rc->initialRCQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, 51);
579 rc->initialRCQP.qpIntra = rc->initialRCQP.qpInterP;
582 rc->initialRCQP.qpIntra = ctx->init_qp_i;
585 if (ctx->init_qp_b < 0) {
586 if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
587 rc->initialRCQP.qpInterB = av_clip(
588 rc->initialRCQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, 51);
590 rc->initialRCQP.qpInterB = rc->initialRCQP.qpInterP;
593 rc->initialRCQP.qpInterB = ctx->init_qp_b;
597 static av_cold void set_lossless(AVCodecContext *avctx)
599 NvencContext *ctx = avctx->priv_data;
600 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
602 rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
603 rc->constQP.qpInterB = 0;
604 rc->constQP.qpInterP = 0;
605 rc->constQP.qpIntra = 0;
611 static void nvenc_override_rate_control(AVCodecContext *avctx)
613 NvencContext *ctx = avctx->priv_data;
614 NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
617 case NV_ENC_PARAMS_RC_CONSTQP:
620 case NV_ENC_PARAMS_RC_VBR_MINQP:
621 if (avctx->qmin < 0) {
622 av_log(avctx, AV_LOG_WARNING,
623 "The variable bitrate rate-control requires "
624 "the 'qmin' option set.\n");
629 case NV_ENC_PARAMS_RC_2_PASS_VBR:
630 case NV_ENC_PARAMS_RC_VBR:
633 case NV_ENC_PARAMS_RC_CBR:
634 case NV_ENC_PARAMS_RC_2_PASS_QUALITY:
635 case NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP:
639 rc->rateControlMode = ctx->rc;
642 static av_cold int nvenc_recalc_surfaces(AVCodecContext *avctx)
644 NvencContext *ctx = avctx->priv_data;
647 if (ctx->rc_lookahead > 0) {
648 nb_surfaces = ctx->rc_lookahead + ((ctx->encode_config.frameIntervalP > 0) ? ctx->encode_config.frameIntervalP : 0) + 1 + 4;
649 if (ctx->nb_surfaces < nb_surfaces) {
650 av_log(avctx, AV_LOG_WARNING,
651 "Defined rc_lookahead requires more surfaces, "
652 "increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
653 ctx->nb_surfaces = nb_surfaces;
657 ctx->nb_surfaces = FFMAX(1, FFMIN(MAX_REGISTERED_FRAMES, ctx->nb_surfaces));
658 ctx->async_depth = FFMIN(ctx->async_depth, ctx->nb_surfaces - 1);
663 static av_cold void nvenc_setup_rate_control(AVCodecContext *avctx)
665 NvencContext *ctx = avctx->priv_data;
667 if (avctx->bit_rate > 0) {
668 ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate;
669 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
670 ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate;
673 if (avctx->rc_max_rate > 0)
674 ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
677 if (ctx->flags & NVENC_ONE_PASS)
679 if (ctx->flags & NVENC_TWO_PASSES)
682 if (ctx->twopass < 0)
683 ctx->twopass = (ctx->flags & NVENC_LOWLATENCY) != 0;
687 ctx->rc = NV_ENC_PARAMS_RC_2_PASS_QUALITY;
689 ctx->rc = NV_ENC_PARAMS_RC_CBR;
691 } else if (avctx->global_quality > 0) {
692 ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
693 } else if (ctx->twopass) {
694 ctx->rc = NV_ENC_PARAMS_RC_2_PASS_VBR;
695 } else if (avctx->qmin >= 0 && avctx->qmax >= 0) {
696 ctx->rc = NV_ENC_PARAMS_RC_VBR_MINQP;
700 if (ctx->flags & NVENC_LOSSLESS) {
702 } else if (ctx->rc >= 0) {
703 nvenc_override_rate_control(avctx);
705 ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR;
709 if (avctx->rc_buffer_size > 0) {
710 ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size;
711 } else if (ctx->encode_config.rcParams.averageBitRate > 0) {
712 ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate;
716 ctx->encode_config.rcParams.enableAQ = 1;
717 ctx->encode_config.rcParams.aqStrength = ctx->aq_strength;
718 av_log(avctx, AV_LOG_VERBOSE, "AQ enabled.\n");
721 if (ctx->temporal_aq) {
722 ctx->encode_config.rcParams.enableTemporalAQ = 1;
723 av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ enabled.\n");
726 if (ctx->rc_lookahead > 0) {
727 int lkd_bound = FFMIN(ctx->nb_surfaces, ctx->async_depth) -
728 ctx->encode_config.frameIntervalP - 4;
731 av_log(avctx, AV_LOG_WARNING,
732 "Lookahead not enabled. Increase buffer delay (-delay).\n");
734 ctx->encode_config.rcParams.enableLookahead = 1;
735 ctx->encode_config.rcParams.lookaheadDepth = av_clip(ctx->rc_lookahead, 0, lkd_bound);
736 ctx->encode_config.rcParams.disableIadapt = ctx->no_scenecut;
737 ctx->encode_config.rcParams.disableBadapt = !ctx->b_adapt;
738 av_log(avctx, AV_LOG_VERBOSE,
739 "Lookahead enabled: depth %d, scenecut %s, B-adapt %s.\n",
740 ctx->encode_config.rcParams.lookaheadDepth,
741 ctx->encode_config.rcParams.disableIadapt ? "disabled" : "enabled",
742 ctx->encode_config.rcParams.disableBadapt ? "disabled" : "enabled");
746 if (ctx->strict_gop) {
747 ctx->encode_config.rcParams.strictGOPTarget = 1;
748 av_log(avctx, AV_LOG_VERBOSE, "Strict GOP target enabled.\n");
752 ctx->encode_config.rcParams.enableNonRefP = 1;
754 if (ctx->zerolatency)
755 ctx->encode_config.rcParams.zeroReorderDelay = 1;
758 ctx->encode_config.rcParams.targetQuality = ctx->quality;
761 static av_cold int nvenc_setup_h264_config(AVCodecContext *avctx)
763 NvencContext *ctx = avctx->priv_data;
764 NV_ENC_CONFIG *cc = &ctx->encode_config;
765 NV_ENC_CONFIG_H264 *h264 = &cc->encodeCodecConfig.h264Config;
766 NV_ENC_CONFIG_H264_VUI_PARAMETERS *vui = &h264->h264VUIParameters;
768 vui->colourMatrix = avctx->colorspace;
769 vui->colourPrimaries = avctx->color_primaries;
770 vui->transferCharacteristics = avctx->color_trc;
771 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
772 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
774 vui->colourDescriptionPresentFlag =
775 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
777 vui->videoSignalTypePresentFlag =
778 (vui->colourDescriptionPresentFlag
779 || vui->videoFormat != 5
780 || vui->videoFullRangeFlag != 0);
783 h264->sliceModeData = 1;
785 h264->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
786 h264->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
787 h264->outputAUD = ctx->aud;
789 if (avctx->refs >= 0) {
790 /* 0 means "let the hardware decide" */
791 h264->maxNumRefFrames = avctx->refs;
793 if (avctx->gop_size >= 0) {
794 h264->idrPeriod = cc->gopLength;
797 if (IS_CBR(cc->rcParams.rateControlMode)) {
798 h264->outputBufferingPeriodSEI = 1;
799 h264->outputPictureTimingSEI = 1;
802 if (cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_QUALITY ||
803 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP ||
804 cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_2_PASS_VBR) {
805 h264->adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE;
806 h264->fmoMode = NV_ENC_H264_FMO_DISABLE;
809 if (ctx->flags & NVENC_LOSSLESS) {
810 h264->qpPrimeYZeroTransformBypassFlag = 1;
812 switch(ctx->profile) {
813 case NV_ENC_H264_PROFILE_BASELINE:
814 cc->profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID;
815 avctx->profile = FF_PROFILE_H264_BASELINE;
817 case NV_ENC_H264_PROFILE_MAIN:
818 cc->profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID;
819 avctx->profile = FF_PROFILE_H264_MAIN;
821 case NV_ENC_H264_PROFILE_HIGH:
822 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID;
823 avctx->profile = FF_PROFILE_H264_HIGH;
825 case NV_ENC_H264_PROFILE_HIGH_444P:
826 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
827 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
832 // force setting profile as high444p if input is AV_PIX_FMT_YUV444P
833 if (ctx->data_pix_fmt == AV_PIX_FMT_YUV444P) {
834 cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
835 avctx->profile = FF_PROFILE_H264_HIGH_444_PREDICTIVE;
838 h264->chromaFormatIDC = avctx->profile == FF_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1;
840 h264->level = ctx->level;
845 static av_cold int nvenc_setup_hevc_config(AVCodecContext *avctx)
847 NvencContext *ctx = avctx->priv_data;
848 NV_ENC_CONFIG *cc = &ctx->encode_config;
849 NV_ENC_CONFIG_HEVC *hevc = &cc->encodeCodecConfig.hevcConfig;
850 NV_ENC_CONFIG_HEVC_VUI_PARAMETERS *vui = &hevc->hevcVUIParameters;
852 vui->colourMatrix = avctx->colorspace;
853 vui->colourPrimaries = avctx->color_primaries;
854 vui->transferCharacteristics = avctx->color_trc;
855 vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
856 || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
858 vui->colourDescriptionPresentFlag =
859 (avctx->colorspace != 2 || avctx->color_primaries != 2 || avctx->color_trc != 2);
861 vui->videoSignalTypePresentFlag =
862 (vui->colourDescriptionPresentFlag
863 || vui->videoFormat != 5
864 || vui->videoFullRangeFlag != 0);
867 hevc->sliceModeData = 1;
869 hevc->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
870 hevc->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
871 hevc->outputAUD = ctx->aud;
873 if (avctx->refs >= 0) {
874 /* 0 means "let the hardware decide" */
875 hevc->maxNumRefFramesInDPB = avctx->refs;
877 if (avctx->gop_size >= 0) {
878 hevc->idrPeriod = cc->gopLength;
881 if (IS_CBR(cc->rcParams.rateControlMode)) {
882 hevc->outputBufferingPeriodSEI = 1;
883 hevc->outputPictureTimingSEI = 1;
886 switch(ctx->profile) {
887 case NV_ENC_HEVC_PROFILE_MAIN:
888 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID;
889 avctx->profile = FF_PROFILE_HEVC_MAIN;
891 case NV_ENC_HEVC_PROFILE_MAIN_10:
892 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
893 avctx->profile = FF_PROFILE_HEVC_MAIN_10;
895 case NV_ENC_HEVC_PROFILE_REXT:
896 cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
897 avctx->profile = FF_PROFILE_HEVC_REXT;
901 // force setting profile as main10 if input is 10 bit
902 if (IS_10BIT(ctx->data_pix_fmt)) {
903 cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
904 avctx->profile = FF_PROFILE_HEVC_MAIN_10;
907 // force setting profile as rext if input is yuv444
908 if (IS_YUV444(ctx->data_pix_fmt)) {
909 cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
910 avctx->profile = FF_PROFILE_HEVC_REXT;
913 hevc->chromaFormatIDC = IS_YUV444(ctx->data_pix_fmt) ? 3 : 1;
915 hevc->pixelBitDepthMinus8 = IS_10BIT(ctx->data_pix_fmt) ? 2 : 0;
917 hevc->level = ctx->level;
919 hevc->tier = ctx->tier;
924 static av_cold int nvenc_setup_codec_config(AVCodecContext *avctx)
926 switch (avctx->codec->id) {
927 case AV_CODEC_ID_H264:
928 return nvenc_setup_h264_config(avctx);
929 case AV_CODEC_ID_HEVC:
930 return nvenc_setup_hevc_config(avctx);
931 /* Earlier switch/case will return if unknown codec is passed. */
937 static av_cold int nvenc_setup_encoder(AVCodecContext *avctx)
939 NvencContext *ctx = avctx->priv_data;
940 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
941 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
943 NV_ENC_PRESET_CONFIG preset_config = { 0 };
944 NVENCSTATUS nv_status = NV_ENC_SUCCESS;
945 AVCPBProperties *cpb_props;
949 ctx->encode_config.version = NV_ENC_CONFIG_VER;
950 ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER;
952 ctx->init_encode_params.encodeHeight = avctx->height;
953 ctx->init_encode_params.encodeWidth = avctx->width;
955 ctx->init_encode_params.encodeConfig = &ctx->encode_config;
957 nvenc_map_preset(ctx);
959 preset_config.version = NV_ENC_PRESET_CONFIG_VER;
960 preset_config.presetCfg.version = NV_ENC_CONFIG_VER;
962 nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder,
963 ctx->init_encode_params.encodeGUID,
964 ctx->init_encode_params.presetGUID,
966 if (nv_status != NV_ENC_SUCCESS)
967 return nvenc_print_error(avctx, nv_status, "Cannot get the preset configuration");
969 memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config));
971 ctx->encode_config.version = NV_ENC_CONFIG_VER;
975 if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0) {
976 dw*= avctx->sample_aspect_ratio.num;
977 dh*= avctx->sample_aspect_ratio.den;
979 av_reduce(&dw, &dh, dw, dh, 1024 * 1024);
980 ctx->init_encode_params.darHeight = dh;
981 ctx->init_encode_params.darWidth = dw;
983 ctx->init_encode_params.frameRateNum = avctx->time_base.den;
984 ctx->init_encode_params.frameRateDen = avctx->time_base.num * avctx->ticks_per_frame;
986 ctx->init_encode_params.enableEncodeAsync = 0;
987 ctx->init_encode_params.enablePTD = 1;
989 if (ctx->bluray_compat) {
991 avctx->refs = FFMIN(FFMAX(avctx->refs, 0), 6);
992 avctx->max_b_frames = FFMIN(avctx->max_b_frames, 3);
993 switch (avctx->codec->id) {
994 case AV_CODEC_ID_H264:
995 /* maximum level depends on used resolution */
997 case AV_CODEC_ID_HEVC:
998 ctx->level = NV_ENC_LEVEL_HEVC_51;
999 ctx->tier = NV_ENC_TIER_HEVC_HIGH;
1004 if (avctx->gop_size > 0) {
1005 if (avctx->max_b_frames >= 0) {
1006 /* 0 is intra-only, 1 is I/P only, 2 is one B-Frame, 3 two B-frames, and so on. */
1007 ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1;
1010 ctx->encode_config.gopLength = avctx->gop_size;
1011 } else if (avctx->gop_size == 0) {
1012 ctx->encode_config.frameIntervalP = 0;
1013 ctx->encode_config.gopLength = 1;
1016 ctx->initial_pts[0] = AV_NOPTS_VALUE;
1017 ctx->initial_pts[1] = AV_NOPTS_VALUE;
1019 nvenc_recalc_surfaces(avctx);
1021 nvenc_setup_rate_control(avctx);
1023 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
1024 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD;
1026 ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME;
1029 res = nvenc_setup_codec_config(avctx);
1033 nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params);
1034 if (nv_status != NV_ENC_SUCCESS) {
1035 return nvenc_print_error(avctx, nv_status, "InitializeEncoder failed");
1038 if (ctx->encode_config.frameIntervalP > 1)
1039 avctx->has_b_frames = 2;
1041 if (ctx->encode_config.rcParams.averageBitRate > 0)
1042 avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate;
1044 cpb_props = ff_add_cpb_side_data(avctx);
1046 return AVERROR(ENOMEM);
1047 cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate;
1048 cpb_props->avg_bitrate = avctx->bit_rate;
1049 cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize;
1054 static NV_ENC_BUFFER_FORMAT nvenc_map_buffer_format(enum AVPixelFormat pix_fmt)
1057 case AV_PIX_FMT_YUV420P:
1058 return NV_ENC_BUFFER_FORMAT_YV12_PL;
1059 case AV_PIX_FMT_NV12:
1060 return NV_ENC_BUFFER_FORMAT_NV12_PL;
1061 case AV_PIX_FMT_P010:
1062 return NV_ENC_BUFFER_FORMAT_YUV420_10BIT;
1063 case AV_PIX_FMT_YUV444P:
1064 return NV_ENC_BUFFER_FORMAT_YUV444_PL;
1065 case AV_PIX_FMT_YUV444P16:
1066 return NV_ENC_BUFFER_FORMAT_YUV444_10BIT;
1067 case AV_PIX_FMT_0RGB32:
1068 return NV_ENC_BUFFER_FORMAT_ARGB;
1069 case AV_PIX_FMT_0BGR32:
1070 return NV_ENC_BUFFER_FORMAT_ABGR;
1072 return NV_ENC_BUFFER_FORMAT_UNDEFINED;
1076 static av_cold int nvenc_alloc_surface(AVCodecContext *avctx, int idx)
1078 NvencContext *ctx = avctx->priv_data;
1079 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1080 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1082 NVENCSTATUS nv_status;
1083 NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 };
1084 allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER;
1086 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1087 ctx->surfaces[idx].in_ref = av_frame_alloc();
1088 if (!ctx->surfaces[idx].in_ref)
1089 return AVERROR(ENOMEM);
1091 NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 };
1093 ctx->surfaces[idx].format = nvenc_map_buffer_format(ctx->data_pix_fmt);
1094 if (ctx->surfaces[idx].format == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
1095 av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
1096 av_get_pix_fmt_name(ctx->data_pix_fmt));
1097 return AVERROR(EINVAL);
1100 allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER;
1101 allocSurf.width = (avctx->width + 31) & ~31;
1102 allocSurf.height = (avctx->height + 31) & ~31;
1103 allocSurf.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
1104 allocSurf.bufferFmt = ctx->surfaces[idx].format;
1106 nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf);
1107 if (nv_status != NV_ENC_SUCCESS) {
1108 return nvenc_print_error(avctx, nv_status, "CreateInputBuffer failed");
1111 ctx->surfaces[idx].input_surface = allocSurf.inputBuffer;
1112 ctx->surfaces[idx].width = allocSurf.width;
1113 ctx->surfaces[idx].height = allocSurf.height;
1116 ctx->surfaces[idx].lockCount = 0;
1118 /* 1MB is large enough to hold most output frames.
1119 * NVENC increases this automaticaly if it is not enough. */
1120 allocOut.size = 1024 * 1024;
1122 allocOut.memoryHeap = NV_ENC_MEMORY_HEAP_SYSMEM_CACHED;
1124 nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut);
1125 if (nv_status != NV_ENC_SUCCESS) {
1126 int err = nvenc_print_error(avctx, nv_status, "CreateBitstreamBuffer failed");
1127 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1128 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[idx].input_surface);
1129 av_frame_free(&ctx->surfaces[idx].in_ref);
1133 ctx->surfaces[idx].output_surface = allocOut.bitstreamBuffer;
1134 ctx->surfaces[idx].size = allocOut.size;
1139 static av_cold int nvenc_setup_surfaces(AVCodecContext *avctx)
1141 NvencContext *ctx = avctx->priv_data;
1144 ctx->surfaces = av_mallocz_array(ctx->nb_surfaces, sizeof(*ctx->surfaces));
1146 return AVERROR(ENOMEM);
1148 ctx->timestamp_list = av_fifo_alloc(ctx->nb_surfaces * sizeof(int64_t));
1149 if (!ctx->timestamp_list)
1150 return AVERROR(ENOMEM);
1151 ctx->output_surface_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1152 if (!ctx->output_surface_queue)
1153 return AVERROR(ENOMEM);
1154 ctx->output_surface_ready_queue = av_fifo_alloc(ctx->nb_surfaces * sizeof(NvencSurface*));
1155 if (!ctx->output_surface_ready_queue)
1156 return AVERROR(ENOMEM);
1158 for (i = 0; i < ctx->nb_surfaces; i++) {
1159 if ((res = nvenc_alloc_surface(avctx, i)) < 0)
1166 static av_cold int nvenc_setup_extradata(AVCodecContext *avctx)
1168 NvencContext *ctx = avctx->priv_data;
1169 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1170 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1172 NVENCSTATUS nv_status;
1173 uint32_t outSize = 0;
1174 char tmpHeader[256];
1175 NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 };
1176 payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER;
1178 payload.spsppsBuffer = tmpHeader;
1179 payload.inBufferSize = sizeof(tmpHeader);
1180 payload.outSPSPPSPayloadSize = &outSize;
1182 nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload);
1183 if (nv_status != NV_ENC_SUCCESS) {
1184 return nvenc_print_error(avctx, nv_status, "GetSequenceParams failed");
1187 avctx->extradata_size = outSize;
1188 avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE);
1190 if (!avctx->extradata) {
1191 return AVERROR(ENOMEM);
1194 memcpy(avctx->extradata, tmpHeader, outSize);
1199 av_cold int ff_nvenc_encode_close(AVCodecContext *avctx)
1201 NvencContext *ctx = avctx->priv_data;
1202 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1203 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1206 /* the encoder has to be flushed before it can be closed */
1207 if (ctx->nvencoder) {
1208 NV_ENC_PIC_PARAMS params = { .version = NV_ENC_PIC_PARAMS_VER,
1209 .encodePicFlags = NV_ENC_PIC_FLAG_EOS };
1211 p_nvenc->nvEncEncodePicture(ctx->nvencoder, ¶ms);
1214 av_fifo_freep(&ctx->timestamp_list);
1215 av_fifo_freep(&ctx->output_surface_ready_queue);
1216 av_fifo_freep(&ctx->output_surface_queue);
1218 if (ctx->surfaces && avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1219 for (i = 0; i < ctx->nb_surfaces; ++i) {
1220 if (ctx->surfaces[i].input_surface) {
1221 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->surfaces[i].in_map.mappedResource);
1224 for (i = 0; i < ctx->nb_registered_frames; i++) {
1225 if (ctx->registered_frames[i].regptr)
1226 p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
1228 ctx->nb_registered_frames = 0;
1231 if (ctx->surfaces) {
1232 for (i = 0; i < ctx->nb_surfaces; ++i) {
1233 if (avctx->pix_fmt != AV_PIX_FMT_CUDA)
1234 p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[i].input_surface);
1235 av_frame_free(&ctx->surfaces[i].in_ref);
1236 p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->surfaces[i].output_surface);
1239 av_freep(&ctx->surfaces);
1240 ctx->nb_surfaces = 0;
1243 p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
1244 ctx->nvencoder = NULL;
1246 if (ctx->cu_context_internal)
1247 dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal);
1248 ctx->cu_context = ctx->cu_context_internal = NULL;
1250 nvenc_free_functions(&dl_fn->nvenc_dl);
1251 cuda_free_functions(&dl_fn->cuda_dl);
1253 dl_fn->nvenc_device_count = 0;
1255 av_log(avctx, AV_LOG_VERBOSE, "Nvenc unloaded\n");
1260 av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
1262 NvencContext *ctx = avctx->priv_data;
1265 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1266 AVHWFramesContext *frames_ctx;
1267 if (!avctx->hw_frames_ctx) {
1268 av_log(avctx, AV_LOG_ERROR,
1269 "hw_frames_ctx must be set when using GPU frames as input\n");
1270 return AVERROR(EINVAL);
1272 frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
1273 ctx->data_pix_fmt = frames_ctx->sw_format;
1275 ctx->data_pix_fmt = avctx->pix_fmt;
1278 if ((ret = nvenc_load_libraries(avctx)) < 0)
1281 if ((ret = nvenc_setup_device(avctx)) < 0)
1284 if ((ret = nvenc_setup_encoder(avctx)) < 0)
1287 if ((ret = nvenc_setup_surfaces(avctx)) < 0)
1290 if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) {
1291 if ((ret = nvenc_setup_extradata(avctx)) < 0)
1298 static NvencSurface *get_free_frame(NvencContext *ctx)
1302 for (i = 0; i < ctx->nb_surfaces; ++i) {
1303 if (!ctx->surfaces[i].lockCount) {
1304 ctx->surfaces[i].lockCount = 1;
1305 return &ctx->surfaces[i];
1312 static int nvenc_copy_frame(AVCodecContext *avctx, NvencSurface *nv_surface,
1313 NV_ENC_LOCK_INPUT_BUFFER *lock_buffer_params, const AVFrame *frame)
1315 int dst_linesize[4] = {
1316 lock_buffer_params->pitch,
1317 lock_buffer_params->pitch,
1318 lock_buffer_params->pitch,
1319 lock_buffer_params->pitch
1321 uint8_t *dst_data[4];
1324 if (frame->format == AV_PIX_FMT_YUV420P)
1325 dst_linesize[1] = dst_linesize[2] >>= 1;
1327 ret = av_image_fill_pointers(dst_data, frame->format, nv_surface->height,
1328 lock_buffer_params->bufferDataPtr, dst_linesize);
1332 if (frame->format == AV_PIX_FMT_YUV420P)
1333 FFSWAP(uint8_t*, dst_data[1], dst_data[2]);
1335 av_image_copy(dst_data, dst_linesize,
1336 (const uint8_t**)frame->data, frame->linesize, frame->format,
1337 avctx->width, avctx->height);
1342 static int nvenc_find_free_reg_resource(AVCodecContext *avctx)
1344 NvencContext *ctx = avctx->priv_data;
1345 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1346 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1350 if (ctx->nb_registered_frames == FF_ARRAY_ELEMS(ctx->registered_frames)) {
1351 for (i = 0; i < ctx->nb_registered_frames; i++) {
1352 if (!ctx->registered_frames[i].mapped) {
1353 if (ctx->registered_frames[i].regptr) {
1354 p_nvenc->nvEncUnregisterResource(ctx->nvencoder,
1355 ctx->registered_frames[i].regptr);
1356 ctx->registered_frames[i].regptr = NULL;
1362 return ctx->nb_registered_frames++;
1365 av_log(avctx, AV_LOG_ERROR, "Too many registered CUDA frames\n");
1366 return AVERROR(ENOMEM);
1369 static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
1371 NvencContext *ctx = avctx->priv_data;
1372 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1373 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1375 AVHWFramesContext *frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
1376 NV_ENC_REGISTER_RESOURCE reg;
1379 for (i = 0; i < ctx->nb_registered_frames; i++) {
1380 if (ctx->registered_frames[i].ptr == (CUdeviceptr)frame->data[0])
1384 idx = nvenc_find_free_reg_resource(avctx);
1388 reg.version = NV_ENC_REGISTER_RESOURCE_VER;
1389 reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_CUDADEVICEPTR;
1390 reg.width = frames_ctx->width;
1391 reg.height = frames_ctx->height;
1392 reg.pitch = frame->linesize[0];
1393 reg.resourceToRegister = frame->data[0];
1395 reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
1396 if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
1397 av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
1398 av_get_pix_fmt_name(frames_ctx->sw_format));
1399 return AVERROR(EINVAL);
1402 ret = p_nvenc->nvEncRegisterResource(ctx->nvencoder, ®);
1403 if (ret != NV_ENC_SUCCESS) {
1404 nvenc_print_error(avctx, ret, "Error registering an input resource");
1405 return AVERROR_UNKNOWN;
1408 ctx->registered_frames[idx].ptr = (CUdeviceptr)frame->data[0];
1409 ctx->registered_frames[idx].regptr = reg.registeredResource;
1413 static int nvenc_upload_frame(AVCodecContext *avctx, const AVFrame *frame,
1414 NvencSurface *nvenc_frame)
1416 NvencContext *ctx = avctx->priv_data;
1417 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1418 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1421 NVENCSTATUS nv_status;
1423 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1424 int reg_idx = nvenc_register_frame(avctx, frame);
1426 av_log(avctx, AV_LOG_ERROR, "Could not register an input CUDA frame\n");
1430 res = av_frame_ref(nvenc_frame->in_ref, frame);
1434 nvenc_frame->in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER;
1435 nvenc_frame->in_map.registeredResource = ctx->registered_frames[reg_idx].regptr;
1436 nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &nvenc_frame->in_map);
1437 if (nv_status != NV_ENC_SUCCESS) {
1438 av_frame_unref(nvenc_frame->in_ref);
1439 return nvenc_print_error(avctx, nv_status, "Error mapping an input resource");
1442 ctx->registered_frames[reg_idx].mapped = 1;
1443 nvenc_frame->reg_idx = reg_idx;
1444 nvenc_frame->input_surface = nvenc_frame->in_map.mappedResource;
1445 nvenc_frame->format = nvenc_frame->in_map.mappedBufferFmt;
1446 nvenc_frame->pitch = frame->linesize[0];
1449 NV_ENC_LOCK_INPUT_BUFFER lockBufferParams = { 0 };
1451 lockBufferParams.version = NV_ENC_LOCK_INPUT_BUFFER_VER;
1452 lockBufferParams.inputBuffer = nvenc_frame->input_surface;
1454 nv_status = p_nvenc->nvEncLockInputBuffer(ctx->nvencoder, &lockBufferParams);
1455 if (nv_status != NV_ENC_SUCCESS) {
1456 return nvenc_print_error(avctx, nv_status, "Failed locking nvenc input buffer");
1459 nvenc_frame->pitch = lockBufferParams.pitch;
1460 res = nvenc_copy_frame(avctx, nvenc_frame, &lockBufferParams, frame);
1462 nv_status = p_nvenc->nvEncUnlockInputBuffer(ctx->nvencoder, nvenc_frame->input_surface);
1463 if (nv_status != NV_ENC_SUCCESS) {
1464 return nvenc_print_error(avctx, nv_status, "Failed unlocking input buffer!");
1471 static void nvenc_codec_specific_pic_params(AVCodecContext *avctx,
1472 NV_ENC_PIC_PARAMS *params)
1474 NvencContext *ctx = avctx->priv_data;
1476 switch (avctx->codec->id) {
1477 case AV_CODEC_ID_H264:
1478 params->codecPicParams.h264PicParams.sliceMode =
1479 ctx->encode_config.encodeCodecConfig.h264Config.sliceMode;
1480 params->codecPicParams.h264PicParams.sliceModeData =
1481 ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1483 case AV_CODEC_ID_HEVC:
1484 params->codecPicParams.hevcPicParams.sliceMode =
1485 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode;
1486 params->codecPicParams.hevcPicParams.sliceModeData =
1487 ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1492 static inline void timestamp_queue_enqueue(AVFifoBuffer* queue, int64_t timestamp)
1494 av_fifo_generic_write(queue, ×tamp, sizeof(timestamp), NULL);
1497 static inline int64_t timestamp_queue_dequeue(AVFifoBuffer* queue)
1499 int64_t timestamp = AV_NOPTS_VALUE;
1500 if (av_fifo_size(queue) > 0)
1501 av_fifo_generic_read(queue, ×tamp, sizeof(timestamp), NULL);
1506 static int nvenc_set_timestamp(AVCodecContext *avctx,
1507 NV_ENC_LOCK_BITSTREAM *params,
1510 NvencContext *ctx = avctx->priv_data;
1512 pkt->pts = params->outputTimeStamp;
1514 /* generate the first dts by linearly extrapolating the
1515 * first two pts values to the past */
1516 if (avctx->max_b_frames > 0 && !ctx->first_packet_output &&
1517 ctx->initial_pts[1] != AV_NOPTS_VALUE) {
1518 int64_t ts0 = ctx->initial_pts[0], ts1 = ctx->initial_pts[1];
1521 if ((ts0 < 0 && ts1 > INT64_MAX + ts0) ||
1522 (ts0 > 0 && ts1 < INT64_MIN + ts0))
1523 return AVERROR(ERANGE);
1526 if ((delta < 0 && ts0 > INT64_MAX + delta) ||
1527 (delta > 0 && ts0 < INT64_MIN + delta))
1528 return AVERROR(ERANGE);
1529 pkt->dts = ts0 - delta;
1531 ctx->first_packet_output = 1;
1535 pkt->dts = timestamp_queue_dequeue(ctx->timestamp_list);
1540 static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf)
1542 NvencContext *ctx = avctx->priv_data;
1543 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1544 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1546 uint32_t slice_mode_data;
1547 uint32_t *slice_offsets = NULL;
1548 NV_ENC_LOCK_BITSTREAM lock_params = { 0 };
1549 NVENCSTATUS nv_status;
1552 enum AVPictureType pict_type;
1554 switch (avctx->codec->id) {
1555 case AV_CODEC_ID_H264:
1556 slice_mode_data = ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
1558 case AV_CODEC_ID_H265:
1559 slice_mode_data = ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
1562 av_log(avctx, AV_LOG_ERROR, "Unknown codec name\n");
1563 res = AVERROR(EINVAL);
1566 slice_offsets = av_mallocz(slice_mode_data * sizeof(*slice_offsets));
1571 lock_params.version = NV_ENC_LOCK_BITSTREAM_VER;
1573 lock_params.doNotWait = 0;
1574 lock_params.outputBitstream = tmpoutsurf->output_surface;
1575 lock_params.sliceOffsets = slice_offsets;
1577 nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params);
1578 if (nv_status != NV_ENC_SUCCESS) {
1579 res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer");
1583 if (res = ff_alloc_packet2(avctx, pkt, lock_params.bitstreamSizeInBytes,0)) {
1584 p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1588 memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes);
1590 nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
1591 if (nv_status != NV_ENC_SUCCESS)
1592 nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open");
1595 if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
1596 p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, tmpoutsurf->in_map.mappedResource);
1597 av_frame_unref(tmpoutsurf->in_ref);
1598 ctx->registered_frames[tmpoutsurf->reg_idx].mapped = 0;
1600 tmpoutsurf->input_surface = NULL;
1603 switch (lock_params.pictureType) {
1604 case NV_ENC_PIC_TYPE_IDR:
1605 pkt->flags |= AV_PKT_FLAG_KEY;
1606 case NV_ENC_PIC_TYPE_I:
1607 pict_type = AV_PICTURE_TYPE_I;
1609 case NV_ENC_PIC_TYPE_P:
1610 pict_type = AV_PICTURE_TYPE_P;
1612 case NV_ENC_PIC_TYPE_B:
1613 pict_type = AV_PICTURE_TYPE_B;
1615 case NV_ENC_PIC_TYPE_BI:
1616 pict_type = AV_PICTURE_TYPE_BI;
1619 av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n");
1620 av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n");
1621 res = AVERROR_EXTERNAL;
1625 #if FF_API_CODED_FRAME
1626 FF_DISABLE_DEPRECATION_WARNINGS
1627 avctx->coded_frame->pict_type = pict_type;
1628 FF_ENABLE_DEPRECATION_WARNINGS
1631 ff_side_data_set_encoder_stats(pkt,
1632 (lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type);
1634 res = nvenc_set_timestamp(avctx, &lock_params, pkt);
1638 av_free(slice_offsets);
1643 timestamp_queue_dequeue(ctx->timestamp_list);
1646 av_free(slice_offsets);
1651 static int output_ready(AVCodecContext *avctx, int flush)
1653 NvencContext *ctx = avctx->priv_data;
1654 int nb_ready, nb_pending;
1656 /* when B-frames are enabled, we wait for two initial timestamps to
1657 * calculate the first dts */
1658 if (!flush && avctx->max_b_frames > 0 &&
1659 (ctx->initial_pts[0] == AV_NOPTS_VALUE || ctx->initial_pts[1] == AV_NOPTS_VALUE))
1662 nb_ready = av_fifo_size(ctx->output_surface_ready_queue) / sizeof(NvencSurface*);
1663 nb_pending = av_fifo_size(ctx->output_surface_queue) / sizeof(NvencSurface*);
1665 return nb_ready > 0;
1666 return (nb_ready > 0) && (nb_ready + nb_pending >= ctx->async_depth);
1669 int ff_nvenc_encode_frame(AVCodecContext *avctx, AVPacket *pkt,
1670 const AVFrame *frame, int *got_packet)
1672 NVENCSTATUS nv_status;
1675 NvencSurface *tmpoutsurf, *inSurf;
1678 NvencContext *ctx = avctx->priv_data;
1679 NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
1680 NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
1682 NV_ENC_PIC_PARAMS pic_params = { 0 };
1683 pic_params.version = NV_ENC_PIC_PARAMS_VER;
1686 inSurf = get_free_frame(ctx);
1688 av_log(avctx, AV_LOG_ERROR, "No free surfaces\n");
1692 cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
1693 if (cu_res != CUDA_SUCCESS) {
1694 av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
1695 return AVERROR_EXTERNAL;
1698 res = nvenc_upload_frame(avctx, frame, inSurf);
1700 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
1701 if (cu_res != CUDA_SUCCESS) {
1702 av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
1703 return AVERROR_EXTERNAL;
1707 inSurf->lockCount = 0;
1711 pic_params.inputBuffer = inSurf->input_surface;
1712 pic_params.bufferFmt = inSurf->format;
1713 pic_params.inputWidth = avctx->width;
1714 pic_params.inputHeight = avctx->height;
1715 pic_params.inputPitch = inSurf->pitch;
1716 pic_params.outputBitstream = inSurf->output_surface;
1718 if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
1719 if (frame->top_field_first)
1720 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM;
1722 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP;
1724 pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
1727 if (ctx->forced_idr >= 0 && frame->pict_type == AV_PICTURE_TYPE_I) {
1728 pic_params.encodePicFlags =
1729 ctx->forced_idr ? NV_ENC_PIC_FLAG_FORCEIDR : NV_ENC_PIC_FLAG_FORCEINTRA;
1731 pic_params.encodePicFlags = 0;
1734 pic_params.inputTimeStamp = frame->pts;
1736 nvenc_codec_specific_pic_params(avctx, &pic_params);
1738 pic_params.encodePicFlags = NV_ENC_PIC_FLAG_EOS;
1741 cu_res = dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context);
1742 if (cu_res != CUDA_SUCCESS) {
1743 av_log(avctx, AV_LOG_ERROR, "cuCtxPushCurrent failed\n");
1744 return AVERROR_EXTERNAL;
1747 nv_status = p_nvenc->nvEncEncodePicture(ctx->nvencoder, &pic_params);
1749 cu_res = dl_fn->cuda_dl->cuCtxPopCurrent(&dummy);
1750 if (cu_res != CUDA_SUCCESS) {
1751 av_log(avctx, AV_LOG_ERROR, "cuCtxPopCurrent failed\n");
1752 return AVERROR_EXTERNAL;
1755 if (nv_status != NV_ENC_SUCCESS &&
1756 nv_status != NV_ENC_ERR_NEED_MORE_INPUT)
1757 return nvenc_print_error(avctx, nv_status, "EncodePicture failed!");
1760 av_fifo_generic_write(ctx->output_surface_queue, &inSurf, sizeof(inSurf), NULL);
1761 timestamp_queue_enqueue(ctx->timestamp_list, frame->pts);
1763 if (ctx->initial_pts[0] == AV_NOPTS_VALUE)
1764 ctx->initial_pts[0] = frame->pts;
1765 else if (ctx->initial_pts[1] == AV_NOPTS_VALUE)
1766 ctx->initial_pts[1] = frame->pts;
1769 /* all the pending buffers are now ready for output */
1770 if (nv_status == NV_ENC_SUCCESS) {
1771 while (av_fifo_size(ctx->output_surface_queue) > 0) {
1772 av_fifo_generic_read(ctx->output_surface_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1773 av_fifo_generic_write(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1777 if (output_ready(avctx, !frame)) {
1778 av_fifo_generic_read(ctx->output_surface_ready_queue, &tmpoutsurf, sizeof(tmpoutsurf), NULL);
1780 res = process_output_surface(avctx, pkt, tmpoutsurf);
1785 av_assert0(tmpoutsurf->lockCount);
1786 tmpoutsurf->lockCount--;