2 * Copyright (c) 2002 Brian Foley
3 * Copyright (c) 2002 Dieter Shirley
4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
6 * This file is part of FFmpeg.
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 #include "libavutil/cpu.h"
24 #include "libavcodec/dsputil.h"
25 #include "dsputil_altivec.h"
27 /* ***** WARNING ***** WARNING ***** WARNING ***** */
29 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
30 cache line size not equal to 32 bytes.
31 Fortunately all processor used by Apple up to at least the 7450 (aka second
32 generation G4) use 32 bytes cache line.
33 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
34 single cache line, so you need to know the cache line size to use it !
35 It's absurd, but it's fast...
37 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
38 size: 128 bytes. Oups.
39 The semantic of dcbz was changed, it always clear 32 bytes. so the function
40 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
41 which is defined to clear a cache line (as dcbz before). So we still can
42 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
44 see <http://developer.apple.com/technotes/tn/tn2087.html>
45 and <http://developer.apple.com/technotes/tn/tn2086.html>
47 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
49 register int misal = ((unsigned long)blocks & 0x00000010);
52 ((unsigned long*)blocks)[0] = 0L;
53 ((unsigned long*)blocks)[1] = 0L;
54 ((unsigned long*)blocks)[2] = 0L;
55 ((unsigned long*)blocks)[3] = 0L;
58 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
59 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
62 ((unsigned long*)blocks)[188] = 0L;
63 ((unsigned long*)blocks)[189] = 0L;
64 ((unsigned long*)blocks)[190] = 0L;
65 ((unsigned long*)blocks)[191] = 0L;
70 /* same as above, when dcbzl clear a whole 128B cache line
71 i.e. the PPC970 aka G5 */
73 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
75 register int misal = ((unsigned long)blocks & 0x0000007f);
78 // we could probably also optimize this case,
79 // but there's not much point as the machines
80 // aren't available yet (2003-06-26)
81 memset(blocks, 0, sizeof(DCTELEM)*6*64);
84 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
85 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
89 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
91 memset(blocks, 0, sizeof(DCTELEM)*6*64);
96 /* check dcbz report how many bytes are set to 0 by dcbz */
97 /* update 24/06/2003 : replace dcbz by dcbzl to get
98 the intended effect (Apple "fixed" dcbz)
99 unfortunately this cannot be used unless the assembler
100 knows about dcbzl ... */
101 static long check_dcbzl_effect(void)
103 register char *fakedata = av_malloc(1024);
104 register char *fakedata_middle;
105 register long zero = 0;
113 fakedata_middle = (fakedata + 512);
115 memset(fakedata, 0xFF, 1024);
117 /* below the constraint "b" seems to mean "Address base register"
118 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
119 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
121 for (i = 0; i < 1024 ; i ++) {
122 if (fakedata[i] == (char)0)
131 static long check_dcbzl_effect(void)
137 static void prefetch_ppc(void *mem, int stride, int h)
139 register const uint8_t *p = mem;
141 __asm__ volatile ("dcbt 0,%0" : : "r" (p));
146 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
148 const int high_bit_depth = avctx->bits_per_raw_sample > 8;
149 int mm_flags = av_get_cpu_flags();
151 if (avctx->dsp_mask) {
152 if (avctx->dsp_mask & AV_CPU_FLAG_FORCE)
153 mm_flags |= (avctx->dsp_mask & 0xffff);
155 mm_flags &= ~(avctx->dsp_mask & 0xffff);
158 // Common optimizations whether AltiVec is available or not
159 c->prefetch = prefetch_ppc;
160 if (!high_bit_depth) {
161 switch (check_dcbzl_effect()) {
163 c->clear_blocks = clear_blocks_dcbz32_ppc;
166 c->clear_blocks = clear_blocks_dcbz128_ppc;
174 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx);
176 if (mm_flags & AV_CPU_FLAG_ALTIVEC) {
177 dsputil_init_altivec(c, avctx);
178 float_init_altivec(c, avctx);
179 int_init_altivec(c, avctx);
180 c->gmc1 = gmc1_altivec;
183 if (avctx->bits_per_raw_sample <= 8 &&
184 (avctx->dct_algo == FF_DCT_AUTO ||
185 avctx->dct_algo == FF_DCT_ALTIVEC)) {
186 c->fdct = fdct_altivec;
188 #endif //CONFIG_ENCODERS
190 if (avctx->lowres == 0 && avctx->bits_per_raw_sample <= 8) {
191 if ((avctx->idct_algo == FF_IDCT_AUTO) ||
192 (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
193 c->idct_put = idct_put_altivec;
194 c->idct_add = idct_add_altivec;
195 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
196 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) &&
197 avctx->idct_algo==FF_IDCT_VP3){
198 c->idct_put = ff_vp3_idct_put_altivec;
199 c->idct_add = ff_vp3_idct_add_altivec;
200 c->idct = ff_vp3_idct_altivec;
201 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
206 #endif /* HAVE_ALTIVEC */