2 * Copyright (c) 2002 Brian Foley
3 * Copyright (c) 2002 Dieter Shirley
4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
6 * This file is part of Libav.
8 * Libav is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * Libav is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with Libav; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include "libavutil/cpu.h"
26 #include "libavutil/mem.h"
27 #include "libavcodec/dsputil.h"
28 #include "dsputil_altivec.h"
30 /* ***** WARNING ***** WARNING ***** WARNING ***** */
32 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
33 cache line size not equal to 32 bytes.
34 Fortunately all processor used by Apple up to at least the 7450 (aka second
35 generation G4) use 32 bytes cache line.
36 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
37 single cache line, so you need to know the cache line size to use it !
38 It's absurd, but it's fast...
40 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
41 size: 128 bytes. Oups.
42 The semantic of dcbz was changed, it always clear 32 bytes. so the function
43 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
44 which is defined to clear a cache line (as dcbz before). So we still can
45 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
47 see <http://developer.apple.com/technotes/tn/tn2087.html>
48 and <http://developer.apple.com/technotes/tn/tn2086.html>
50 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
52 register int misal = ((unsigned long)blocks & 0x00000010);
55 ((unsigned long*)blocks)[0] = 0L;
56 ((unsigned long*)blocks)[1] = 0L;
57 ((unsigned long*)blocks)[2] = 0L;
58 ((unsigned long*)blocks)[3] = 0L;
61 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
62 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
65 ((unsigned long*)blocks)[188] = 0L;
66 ((unsigned long*)blocks)[189] = 0L;
67 ((unsigned long*)blocks)[190] = 0L;
68 ((unsigned long*)blocks)[191] = 0L;
73 /* same as above, when dcbzl clear a whole 128B cache line
74 i.e. the PPC970 aka G5 */
76 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
78 register int misal = ((unsigned long)blocks & 0x0000007f);
81 // we could probably also optimize this case,
82 // but there's not much point as the machines
83 // aren't available yet (2003-06-26)
84 memset(blocks, 0, sizeof(DCTELEM)*6*64);
87 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
88 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
92 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
94 memset(blocks, 0, sizeof(DCTELEM)*6*64);
99 /* check dcbz report how many bytes are set to 0 by dcbz */
100 /* update 24/06/2003 : replace dcbz by dcbzl to get
101 the intended effect (Apple "fixed" dcbz)
102 unfortunately this cannot be used unless the assembler
103 knows about dcbzl ... */
104 static long check_dcbzl_effect(void)
106 register char *fakedata = av_malloc(1024);
107 register char *fakedata_middle;
108 register long zero = 0;
116 fakedata_middle = (fakedata + 512);
118 memset(fakedata, 0xFF, 1024);
120 /* below the constraint "b" seems to mean "Address base register"
121 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
122 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
124 for (i = 0; i < 1024 ; i ++) {
125 if (fakedata[i] == (char)0)
134 static long check_dcbzl_effect(void)
140 static void prefetch_ppc(void *mem, int stride, int h)
142 register const uint8_t *p = mem;
144 __asm__ volatile ("dcbt 0,%0" : : "r" (p));
149 void ff_dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
151 const int high_bit_depth = avctx->bits_per_raw_sample > 8;
153 // Common optimizations whether AltiVec is available or not
154 c->prefetch = prefetch_ppc;
155 if (!high_bit_depth) {
156 switch (check_dcbzl_effect()) {
158 c->clear_blocks = clear_blocks_dcbz32_ppc;
161 c->clear_blocks = clear_blocks_dcbz128_ppc;
169 if(CONFIG_H264_DECODER) ff_dsputil_h264_init_ppc(c, avctx);
171 if (av_get_cpu_flags() & AV_CPU_FLAG_ALTIVEC) {
172 ff_dsputil_init_altivec(c, avctx);
173 ff_float_init_altivec(c, avctx);
174 ff_int_init_altivec(c, avctx);
175 c->gmc1 = ff_gmc1_altivec;
178 if (avctx->bits_per_raw_sample <= 8 &&
179 (avctx->dct_algo == FF_DCT_AUTO ||
180 avctx->dct_algo == FF_DCT_ALTIVEC)) {
181 c->fdct = ff_fdct_altivec;
183 #endif //CONFIG_ENCODERS
185 if (avctx->bits_per_raw_sample <= 8) {
186 if ((avctx->idct_algo == FF_IDCT_AUTO) ||
187 (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
188 c->idct_put = ff_idct_put_altivec;
189 c->idct_add = ff_idct_add_altivec;
190 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
195 #endif /* HAVE_ALTIVEC */