1 ;*****************************************************************************
2 ;* MMX/SSE2-optimized H.264 iDCT
3 ;*****************************************************************************
4 ;* Copyright (C) 2004-2005 Michael Niedermayer, Loren Merritt
5 ;* Copyright (C) 2003-2008 x264 project
7 ;* Authors: Laurent Aimar <fenrir@via.ecp.fr>
8 ;* Loren Merritt <lorenm@u.washington.edu>
9 ;* Holger Lubitz <hal@duncan.ol.sub.de>
10 ;* Min Chen <chenm001.163.com>
12 ;* This file is part of FFmpeg.
14 ;* FFmpeg is free software; you can redistribute it and/or
15 ;* modify it under the terms of the GNU Lesser General Public
16 ;* License as published by the Free Software Foundation; either
17 ;* version 2.1 of the License, or (at your option) any later version.
19 ;* FFmpeg is distributed in the hope that it will be useful,
20 ;* but WITHOUT ANY WARRANTY; without even the implied warranty of
21 ;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 ;* Lesser General Public License for more details.
24 ;* You should have received a copy of the GNU Lesser General Public
25 ;* License along with FFmpeg; if not, write to the Free Software
26 ;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
27 ;*****************************************************************************
29 %include "libavutil/x86/x86inc.asm"
30 %include "libavutil/x86/x86util.asm"
34 ; FIXME this table is a duplicate from h264data.h, and will be removed once the tables from, h264 have been split
35 scan8_mem: db 4+ 1*8, 5+ 1*8, 4+ 2*8, 5+ 2*8
36 db 6+ 1*8, 7+ 1*8, 6+ 2*8, 7+ 2*8
37 db 4+ 3*8, 5+ 3*8, 4+ 4*8, 5+ 4*8
38 db 6+ 3*8, 7+ 3*8, 6+ 4*8, 7+ 4*8
39 db 4+ 6*8, 5+ 6*8, 4+ 7*8, 5+ 7*8
40 db 6+ 6*8, 7+ 6*8, 6+ 7*8, 7+ 7*8
41 db 4+ 8*8, 5+ 8*8, 4+ 9*8, 5+ 9*8
42 db 6+ 8*8, 7+ 8*8, 6+ 9*8, 7+ 9*8
43 db 4+11*8, 5+11*8, 4+12*8, 5+12*8
44 db 6+11*8, 7+11*8, 6+12*8, 7+12*8
45 db 4+13*8, 5+13*8, 4+14*8, 5+14*8
46 db 6+13*8, 7+13*8, 6+14*8, 7+14*8
52 %define scan8 scan8_mem
60 ; %1=uint8_t *dst, %2=int16_t *block, %3=int stride
68 IDCT4_1D w, 0, 1, 2, 3, 4, 5
70 TRANSPOSE4x4W 0, 1, 2, 3, 4
72 IDCT4_1D w, 0, 1, 2, 3, 4, 5
75 STORE_DIFFx2 m0, m1, m4, m5, m7, 6, %1, %3
77 STORE_DIFFx2 m2, m3, m4, m5, m7, 6, %1, %3
81 ; ff_h264_idct_add_mmx(uint8_t *dst, int16_t *block, int stride)
82 cglobal h264_idct_add_8_mmx, 3, 3, 0
134 SWAP 7, 6, 4, 5, 2, 3, 1, 0 ; 70315246 -> 01234567
137 %macro IDCT8_1D_FULL 1
144 IDCT8_1D [%1], [%1+ 64]
147 ; %1=int16_t *block, %2=int16_t *dstblock
148 %macro IDCT8_ADD_MMX_START 2
151 TRANSPOSE4x4W 0, 1, 2, 3, 7
157 TRANSPOSE4x4W 4, 5, 6, 7, 3
164 ; %1=uint8_t *dst, %2=int16_t *block, %3=int stride
165 %macro IDCT8_ADD_MMX_END 3
172 STORE_DIFFx2 m0, m1, m5, m6, m7, 6, %1, %3
174 STORE_DIFFx2 m2, m3, m5, m6, m7, 6, %1, %3
179 STORE_DIFFx2 m4, m0, m5, m6, m7, 6, %1, %3
181 STORE_DIFFx2 m1, m2, m5, m6, m7, 6, %1, %3
185 ; ff_h264_idct8_add_mmx(uint8_t *dst, int16_t *block, int stride)
186 cglobal h264_idct8_add_8_mmx, 3, 4, 0
187 %assign pad 128+4-(stack_offset&7)
191 IDCT8_ADD_MMX_START r1 , rsp
192 IDCT8_ADD_MMX_START r1+8, rsp+64
194 IDCT8_ADD_MMX_END r0 , rsp, r2
195 IDCT8_ADD_MMX_END r3 , rsp+8, r2
200 ; %1=uint8_t *dst, %2=int16_t *block, %3=int stride
201 %macro IDCT8_ADD_SSE 4
204 TRANSPOSE8x8W 0, 1, 2, 3, 4, 5, 6, 7, 8
206 TRANSPOSE8x8W 0, 1, 2, 3, 4, 5, 6, 7, [%2], [%2+16]
213 IDCT8_1D [%2], [%2+ 16]
226 STORE_DIFF m0, m6, m7, [%1 ]
227 STORE_DIFF m1, m6, m7, [%1+%3 ]
228 STORE_DIFF m2, m6, m7, [%1+%3*2]
229 STORE_DIFF m3, m6, m7, [%1+%4 ]
238 STORE_DIFF m4, m6, m7, [%1 ]
239 STORE_DIFF m5, m6, m7, [%1+%3 ]
240 STORE_DIFF m0, m6, m7, [%1+%3*2]
241 STORE_DIFF m1, m6, m7, [%1+%4 ]
245 ; ff_h264_idct8_add_sse2(uint8_t *dst, int16_t *block, int stride)
246 cglobal h264_idct8_add_8_sse2, 3, 4, 10
247 IDCT8_ADD_SSE r0, r1, r2, r3
250 %macro DC_ADD_MMX2_INIT 2-3
270 %macro DC_ADD_MMX2_OP 4
290 ; ff_h264_idct_dc_add_mmx2(uint8_t *dst, int16_t *block, int stride)
291 cglobal h264_idct_dc_add_8_mmx2, 3, 3, 0
292 DC_ADD_MMX2_INIT r1, r2
293 DC_ADD_MMX2_OP movh, r0, r2, r1
296 ; ff_h264_idct8_dc_add_mmx2(uint8_t *dst, int16_t *block, int stride)
297 cglobal h264_idct8_dc_add_8_mmx2, 3, 3, 0
298 DC_ADD_MMX2_INIT r1, r2
299 DC_ADD_MMX2_OP mova, r0, r2, r1
301 DC_ADD_MMX2_OP mova, r0, r2, r1
304 ; ff_h264_idct_add16_mmx(uint8_t *dst, const int *block_offset,
305 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
306 cglobal h264_idct_add16_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
309 lea picregq, [scan8_mem]
312 movzx r6, byte [scan8+r5]
313 movzx r6, byte [r4+r6]
316 mov r6d, dword [r1+r5*4]
326 ; ff_h264_idct8_add4_mmx(uint8_t *dst, const int *block_offset,
327 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
328 cglobal h264_idct8_add4_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
329 %assign pad 128+4-(stack_offset&7)
334 lea picregq, [scan8_mem]
337 movzx r6, byte [scan8+r5]
338 movzx r6, byte [r4+r6]
341 mov r6d, dword [r1+r5*4]
344 IDCT8_ADD_MMX_START r2 , rsp
345 IDCT8_ADD_MMX_START r2+8, rsp+64
346 IDCT8_ADD_MMX_END r6 , rsp, r3
347 mov r6d, dword [r1+r5*4]
349 IDCT8_ADD_MMX_END r6 , rsp+8, r3
358 ; ff_h264_idct_add16_mmx2(uint8_t *dst, const int *block_offset,
359 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
360 cglobal h264_idct_add16_8_mmx2, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
363 lea picregq, [scan8_mem]
366 movzx r6, byte [scan8+r5]
367 movzx r6, byte [r4+r6]
375 DC_ADD_MMX2_INIT r2, r3, r6
380 mov dst2d, dword [r1+r5*4]
381 lea dst2q, [r0+dst2q]
382 DC_ADD_MMX2_OP movh, dst2q, r3, r6
392 mov r6d, dword [r1+r5*4]
402 ; ff_h264_idct_add16intra_mmx(uint8_t *dst, const int *block_offset,
403 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
404 cglobal h264_idct_add16intra_8_mmx, 5, 7 + npicregs, 0, dst, block_offset, block, stride, nnzc, cntr, coeff, picreg
407 lea picregq, [scan8_mem]
410 movzx r6, byte [scan8+r5]
411 movzx r6, byte [r4+r6]
415 mov r6d, dword [r1+r5*4]
425 ; ff_h264_idct_add16intra_mmx2(uint8_t *dst, const int *block_offset,
426 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
427 cglobal h264_idct_add16intra_8_mmx2, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
430 lea picregq, [scan8_mem]
433 movzx r6, byte [scan8+r5]
434 movzx r6, byte [r4+r6]
437 mov r6d, dword [r1+r5*4]
449 DC_ADD_MMX2_INIT r2, r3, r6
454 mov dst2d, dword [r1+r5*4]
456 DC_ADD_MMX2_OP movh, dst2q, r3, r6
467 ; ff_h264_idct8_add4_mmx2(uint8_t *dst, const int *block_offset,
468 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
469 cglobal h264_idct8_add4_8_mmx2, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
470 %assign pad 128+4-(stack_offset&7)
475 lea picregq, [scan8_mem]
478 movzx r6, byte [scan8+r5]
479 movzx r6, byte [r4+r6]
487 DC_ADD_MMX2_INIT r2, r3, r6
492 mov dst2d, dword [r1+r5*4]
493 lea dst2q, [r0+dst2q]
494 DC_ADD_MMX2_OP mova, dst2q, r3, r6
495 lea dst2q, [dst2q+r3*4]
496 DC_ADD_MMX2_OP mova, dst2q, r3, r6
508 mov r6d, dword [r1+r5*4]
511 IDCT8_ADD_MMX_START r2 , rsp
512 IDCT8_ADD_MMX_START r2+8, rsp+64
513 IDCT8_ADD_MMX_END r6 , rsp, r3
514 mov r6d, dword [r1+r5*4]
516 IDCT8_ADD_MMX_END r6 , rsp+8, r3
527 ; ff_h264_idct8_add4_sse2(uint8_t *dst, const int *block_offset,
528 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
529 cglobal h264_idct8_add4_8_sse2, 5, 8 + npicregs, 10, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
532 lea picregq, [scan8_mem]
535 movzx r6, byte [scan8+r5]
536 movzx r6, byte [r4+r6]
545 DC_ADD_MMX2_INIT r2, r3, r6
550 mov dst2d, dword [r1+r5*4]
552 DC_ADD_MMX2_OP mova, dst2q, r3, r6
553 lea dst2q, [dst2q+r3*4]
554 DC_ADD_MMX2_OP mova, dst2q, r3, r6
565 mov dst2d, dword [r1+r5*4]
567 IDCT8_ADD_SSE dst2q, r2, r3, r6
579 h264_idct_add8_mmx_plane:
581 movzx r6, byte [scan8+r5]
582 movzx r6, byte [r4+r6]
587 mov r0d, dword [r1+r5*4]
590 mov r0, r1m ; XXX r1m here is actually r0m of the calling func
592 add r0, dword [r1+r5*4]
602 ; ff_h264_idct_add8_mmx(uint8_t **dest, const int *block_offset,
603 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
604 cglobal h264_idct_add8_8_mmx, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
608 lea picregq, [scan8_mem]
613 call h264_idct_add8_mmx_plane
621 call h264_idct_add8_mmx_plane
624 h264_idct_add8_mmx2_plane:
626 movzx r6, byte [scan8+r5]
627 movzx r6, byte [r4+r6]
631 mov r0d, dword [r1+r5*4]
634 mov r0, r1m ; XXX r1m here is actually r0m of the calling func
636 add r0, dword [r1+r5*4]
648 DC_ADD_MMX2_INIT r2, r3, r6
650 mov r0d, dword [r1+r5*4]
653 mov r0, r1m ; XXX r1m here is actually r0m of the calling func
655 add r0, dword [r1+r5*4]
657 DC_ADD_MMX2_OP movh, r0, r3, r6
665 ; ff_h264_idct_add8_mmx2(uint8_t **dest, const int *block_offset,
666 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
667 cglobal h264_idct_add8_8_mmx2, 5, 8 + npicregs, 0, dst1, block_offset, block, stride, nnzc, cntr, coeff, dst2, picreg
674 lea picregq, [scan8_mem]
676 call h264_idct_add8_mmx2_plane
684 call h264_idct_add8_mmx2_plane
688 ; r0 = uint8_t *dst, r2 = int16_t *block, r3 = int stride, r6=clobbered
689 h264_idct_dc_add8_mmx2:
690 movd m0, [r2 ] ; 0 0 X D
691 punpcklwd m0, [r2+32] ; x X d D
694 punpcklwd m0, m0 ; d d D D
695 pxor m1, m1 ; 0 0 0 0
696 psubw m1, m0 ; -d-d-D-D
697 packuswb m0, m1 ; -d-d-D-D d d D D
698 pshufw m1, m0, 0xFA ; -d-d-d-d-D-D-D-D
699 punpcklwd m0, m0 ; d d d d D D D D
701 DC_ADD_MMX2_OP movq, r0, r3, r6
706 ; r0 = uint8_t *dst (clobbered), r2 = int16_t *block, r3 = int stride
707 h264_add8x4_idct_sse2:
716 IDCT4_1D w,0,1,2,3,4,5
717 TRANSPOSE2x4x4W 0,1,2,3,4
719 IDCT4_1D w,0,1,2,3,4,5
721 STORE_DIFFx2 m0, m1, m4, m5, m7, 6, r0, r3
723 STORE_DIFFx2 m2, m3, m4, m5, m7, 6, r0, r3
726 %macro add16_sse2_cycle 2
727 movzx r0, word [r4+%2]
730 mov r0d, dword [r1+%1*8]
736 call h264_add8x4_idct_sse2
743 ; ff_h264_idct_add16_sse2(uint8_t *dst, const int *block_offset,
744 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
745 cglobal h264_idct_add16_8_sse2, 5, 5 + ARCH_X86_64, 8
749 ; unrolling of the loop leads to an average performance gain of
751 add16_sse2_cycle 0, 0xc
752 add16_sse2_cycle 1, 0x14
753 add16_sse2_cycle 2, 0xe
754 add16_sse2_cycle 3, 0x16
755 add16_sse2_cycle 4, 0x1c
756 add16_sse2_cycle 5, 0x24
757 add16_sse2_cycle 6, 0x1e
758 add16_sse2_cycle 7, 0x26
761 %macro add16intra_sse2_cycle 2
762 movzx r0, word [r4+%2]
765 mov r0d, dword [r1+%1*8]
771 call h264_add8x4_idct_sse2
777 mov r0d, dword [r1+%1*8]
783 call h264_idct_dc_add8_mmx2
790 ; ff_h264_idct_add16intra_sse2(uint8_t *dst, const int *block_offset,
791 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
792 cglobal h264_idct_add16intra_8_sse2, 5, 7 + ARCH_X86_64, 8
796 add16intra_sse2_cycle 0, 0xc
797 add16intra_sse2_cycle 1, 0x14
798 add16intra_sse2_cycle 2, 0xe
799 add16intra_sse2_cycle 3, 0x16
800 add16intra_sse2_cycle 4, 0x1c
801 add16intra_sse2_cycle 5, 0x24
802 add16intra_sse2_cycle 6, 0x1e
803 add16intra_sse2_cycle 7, 0x26
806 %macro add8_sse2_cycle 2
807 movzx r0, word [r4+%2]
811 mov r0d, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
816 add r0, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
818 call h264_add8x4_idct_sse2
825 mov r0d, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
830 add r0, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
832 call h264_idct_dc_add8_mmx2
841 ; ff_h264_idct_add8_sse2(uint8_t **dest, const int *block_offset,
842 ; DCTELEM *block, int stride, const uint8_t nnzc[6*8])
843 cglobal h264_idct_add8_8_sse2, 5, 7 + ARCH_X86_64, 8
848 add8_sse2_cycle 0, 0x34
849 add8_sse2_cycle 1, 0x3c
855 add8_sse2_cycle 2, 0x5c
856 add8_sse2_cycle 3, 0x64
859 ;void ff_h264_luma_dc_dequant_idct_mmx(DCTELEM *output, DCTELEM *input, int qmul)
862 SUMSUB_BADC w, %4, %3, %2, %1, %5
863 SUMSUB_BADC w, %4, %2, %3, %1, %5
889 %macro STORE_WORDS_MMX 5
901 %macro DEQUANT_STORE_MMX 1
902 DEQUANT_MMX m0, m1, %1
903 STORE_WORDS_MMX m0, 0, 1, 4, 5
904 STORE_WORDS_MMX m1, 2, 3, 6, 7
906 DEQUANT_MMX m2, m3, %1
907 STORE_WORDS_MMX m2, 8, 9, 12, 13
908 STORE_WORDS_MMX m3, 10, 11, 14, 15
911 %macro STORE_WORDS_SSE 9
933 %macro DEQUANT_STORE_SSE2 1
955 STORE_WORDS_SSE xmm0, 0, 1, 4, 5, 2, 3, 6, 7
956 STORE_WORDS_SSE xmm2, 8, 9, 12, 13, 10, 11, 14, 15
959 %macro IDCT_DC_DEQUANT 2
960 cglobal h264_luma_dc_dequant_idct_%1, 3,4,%2
961 ; manually spill XMM registers for Win64 because
962 ; the code here is initialized with INIT_MMX
969 TRANSPOSE4x4W 0,1,2,3,4
972 ; shift, tmp, output, qmul
974 DECLARE_REG_TMP 0,3,1,2
975 ; we can't avoid this, because r0 is the shift register (ecx) on win64
978 DECLARE_REG_TMP 3,1,0,2
980 DECLARE_REG_TMP 1,3,0,2
1003 DEQUANT_STORE_MMX m6
1006 DEQUANT_STORE_SSE2 xmm6
1012 IDCT_DC_DEQUANT mmx, 0
1013 IDCT_DC_DEQUANT sse2, 7