2 * CPU detection code, extracted from mmx.h
3 * (c)1997-99 by H. Dietz and R. Fisher
4 * Converted to C and improved by Fabrice Bellard.
6 * This file is part of FFmpeg.
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include "libavutil/x86/asm.h"
26 #include "libavutil/cpu.h"
29 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
30 #define cpuid(index, eax, ebx, ecx, edx) \
32 "mov %%"REG_b", %%"REG_S" \n\t" \
34 "xchg %%"REG_b", %%"REG_S \
35 : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
40 #define cpuid(index, eax, ebx, ecx, edx) \
43 __cpuid(info, index); \
49 #endif /* HAVE_CPUID */
52 #define xgetbv(index, eax, edx) \
53 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
55 #include <immintrin.h>
57 #define xgetbv(index, eax, edx) \
59 uint64_t res = __xgetbv(index); \
63 #endif /* HAVE_XGETBV */
67 #define get_eflags(x) \
68 __asm__ volatile ("pushfl \n" \
72 #define set_eflags(x) \
73 __asm__ volatile ("push %0 \n" \
81 #define get_eflags(x) \
84 #define set_eflags(x) \
87 #endif /* HAVE_INLINE_ASM */
89 /* Function to test if multimedia instructions are supported... */
90 int ff_get_cpu_flags_x86(void)
93 int eax, ebx, ecx, edx;
94 int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
95 int family = 0, model = 0;
96 union { int i[3]; char c[12]; } vendor;
101 /* Check if CPUID is supported by attempting to toggle the ID bit in
102 * the EFLAGS register. */
104 set_eflags(a ^ 0x200000);
108 return 0; /* CPUID not supported */
111 cpuid(0, max_std_level, ebx, ecx, edx);
116 if (max_std_level >= 1) {
117 cpuid(1, eax, ebx, ecx, std_caps);
118 family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
119 model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
120 if (std_caps & (1 << 15))
121 rval |= AV_CPU_FLAG_CMOV;
122 if (std_caps & (1 << 23))
123 rval |= AV_CPU_FLAG_MMX;
124 if (std_caps & (1 << 25))
125 rval |= AV_CPU_FLAG_MMXEXT;
127 if (std_caps & (1 << 25))
128 rval |= AV_CPU_FLAG_SSE;
129 if (std_caps & (1 << 26))
130 rval |= AV_CPU_FLAG_SSE2;
132 rval |= AV_CPU_FLAG_SSE3;
133 if (ecx & 0x00000200 )
134 rval |= AV_CPU_FLAG_SSSE3;
135 if (ecx & 0x00080000 )
136 rval |= AV_CPU_FLAG_SSE4;
137 if (ecx & 0x00100000 )
138 rval |= AV_CPU_FLAG_SSE42;
140 /* Check OXSAVE and AVX bits */
141 if ((ecx & 0x18000000) == 0x18000000) {
142 /* Check for OS support */
144 if ((eax & 0x6) == 0x6)
145 rval |= AV_CPU_FLAG_AVX;
147 #endif /* HAVE_AVX */
148 #endif /* HAVE_SSE */
151 cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
153 if (max_ext_level >= 0x80000001) {
154 cpuid(0x80000001, eax, ebx, ecx, ext_caps);
155 if (ext_caps & (1U << 31))
156 rval |= AV_CPU_FLAG_3DNOW;
157 if (ext_caps & (1 << 30))
158 rval |= AV_CPU_FLAG_3DNOWEXT;
159 if (ext_caps & (1 << 23))
160 rval |= AV_CPU_FLAG_MMX;
161 if (ext_caps & (1 << 22))
162 rval |= AV_CPU_FLAG_MMXEXT;
164 /* Allow for selectively disabling SSE2 functions on AMD processors
165 with SSE2 support but not SSE4a. This includes Athlon64, some
166 Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
167 than SSE2 often enough to utilize this special-case flag.
168 AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
169 so that SSE2 is used unless explicitly disabled by checking
170 AV_CPU_FLAG_SSE2SLOW. */
171 if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
172 rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
173 rval |= AV_CPU_FLAG_SSE2SLOW;
176 /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
177 * used unless the OS has AVX support. */
178 if (rval & AV_CPU_FLAG_AVX) {
179 if (ecx & 0x00000800)
180 rval |= AV_CPU_FLAG_XOP;
181 if (ecx & 0x00010000)
182 rval |= AV_CPU_FLAG_FMA4;
186 if (!strncmp(vendor.c, "GenuineIntel", 12)) {
187 if (family == 6 && (model == 9 || model == 13 || model == 14)) {
188 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
189 * 6/14 (core1 "yonah") theoretically support sse2, but it's
190 * usually slower than mmx, so let's just pretend they don't.
191 * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
192 * enabled so that SSE2 is not used unless explicitly enabled
193 * by checking AV_CPU_FLAG_SSE2SLOW. The same situation
194 * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
195 if (rval & AV_CPU_FLAG_SSE2)
196 rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
197 if (rval & AV_CPU_FLAG_SSE3)
198 rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
200 /* The Atom processor has SSSE3 support, which is useful in many cases,
201 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
202 * on the Atom, but is generally faster on other processors supporting
203 * SSSE3. This flag allows for selectively disabling certain SSSE3
204 * functions on the Atom. */
205 if (family == 6 && model == 28)
206 rval |= AV_CPU_FLAG_ATOM;