2 * CPU detection code, extracted from mmx.h
3 * (c)1997-99 by H. Dietz and R. Fisher
4 * Converted to C and improved by Fabrice Bellard.
6 * This file is part of FFmpeg.
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include "libavutil/x86_cpu.h"
26 #include "libavutil/cpu.h"
28 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
29 #define cpuid(index,eax,ebx,ecx,edx)\
31 ("mov %%"REG_b", %%"REG_S"\n\t"\
33 "xchg %%"REG_b", %%"REG_S\
34 : "=a" (eax), "=S" (ebx),\
35 "=c" (ecx), "=d" (edx)\
38 #define xgetbv(index,eax,edx) \
39 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
41 /* Function to test if multimedia instructions are supported... */
42 int ff_get_cpu_flags_x86(void)
45 int eax, ebx, ecx, edx;
46 int max_std_level, max_ext_level, std_caps=0, ext_caps=0;
47 int family=0, model=0;
48 union { int i[3]; char c[12]; } vendor;
53 /* See if CPUID instruction is supported ... */
54 /* ... Get copies of EFLAGS into eax and ecx */
59 /* ... Toggle the ID bit in one copy and store */
60 /* to the EFLAGS reg */
61 "xor $0x200000, %0\n\t"
65 /* ... Get the (hopefully modified) EFLAGS */
74 return 0; /* CPUID not supported */
77 cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);
79 if(max_std_level >= 1){
80 cpuid(1, eax, ebx, ecx, std_caps);
81 family = ((eax>>8)&0xf) + ((eax>>20)&0xff);
82 model = ((eax>>4)&0xf) + ((eax>>12)&0xf0);
83 if (std_caps & (1<<23))
84 rval |= AV_CPU_FLAG_MMX;
85 if (std_caps & (1<<25))
86 rval |= AV_CPU_FLAG_MMX2
89 if (std_caps & (1<<26))
90 rval |= AV_CPU_FLAG_SSE2;
92 rval |= AV_CPU_FLAG_SSE3;
93 if (ecx & 0x00000200 )
94 rval |= AV_CPU_FLAG_SSSE3;
95 if (ecx & 0x00080000 )
96 rval |= AV_CPU_FLAG_SSE4;
97 if (ecx & 0x00100000 )
98 rval |= AV_CPU_FLAG_SSE42;
100 /* Check OXSAVE and AVX bits */
101 if ((ecx & 0x18000000) == 0x18000000) {
102 /* Check for OS support */
104 if ((eax & 0x6) == 0x6)
105 rval |= AV_CPU_FLAG_AVX;
112 cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
114 if(max_ext_level >= 0x80000001){
115 cpuid(0x80000001, eax, ebx, ecx, ext_caps);
116 if (ext_caps & (1U<<31))
117 rval |= AV_CPU_FLAG_3DNOW;
118 if (ext_caps & (1<<30))
119 rval |= AV_CPU_FLAG_3DNOWEXT;
120 if (ext_caps & (1<<23))
121 rval |= AV_CPU_FLAG_MMX;
122 if (ext_caps & (1<<22))
123 rval |= AV_CPU_FLAG_MMX2;
125 /* Allow for selectively disabling SSE2 functions on AMD processors
126 with SSE2 support but not SSE4a. This includes Athlon64, some
127 Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
128 than SSE2 often enough to utilize this special-case flag.
129 AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
130 so that SSE2 is used unless explicitly disabled by checking
131 AV_CPU_FLAG_SSE2SLOW. */
132 if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
133 rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
134 rval |= AV_CPU_FLAG_SSE2SLOW;
137 /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
138 * used unless the OS has AVX support. */
139 if (rval & AV_CPU_FLAG_AVX) {
140 if (ecx & 0x00000800)
141 rval |= AV_CPU_FLAG_XOP;
142 if (ecx & 0x00010000)
143 rval |= AV_CPU_FLAG_FMA4;
147 if (!strncmp(vendor.c, "GenuineIntel", 12)) {
148 if (family == 6 && (model == 9 || model == 13 || model == 14)) {
149 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
150 * theoretically support sse2, but it's usually slower than mmx,
151 * so let's just pretend they don't. AV_CPU_FLAG_SSE2 is disabled and
152 * AV_CPU_FLAG_SSE2SLOW is enabled so that SSE2 is not used unless
153 * explicitly enabled by checking AV_CPU_FLAG_SSE2SLOW. The same
154 * situation applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
155 if (rval & AV_CPU_FLAG_SSE2) rval ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;
156 if (rval & AV_CPU_FLAG_SSE3) rval ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;
158 /* The Atom processor has SSSE3 support, which is useful in many cases,
159 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
160 * on the Atom, but is generally faster on other processors supporting
161 * SSSE3. This flag allows for selectively disabling certain SSSE3
162 * functions on the Atom. */
163 if (family == 6 && model == 28)
164 rval |= AV_CPU_FLAG_ATOM;