2 * CPU detection code, extracted from mmx.h
3 * (c)1997-99 by H. Dietz and R. Fisher
4 * Converted to C and improved by Fabrice Bellard.
6 * This file is part of FFmpeg.
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include "libavutil/x86_cpu.h"
26 #include "libavutil/cpu.h"
28 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
29 #define cpuid(index, eax, ebx, ecx, edx) \
31 "mov %%"REG_b", %%"REG_S" \n\t" \
33 "xchg %%"REG_b", %%"REG_S \
34 : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
37 #define xgetbv(index, eax, edx) \
38 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
40 /* Function to test if multimedia instructions are supported... */
41 int ff_get_cpu_flags_x86(void)
44 int eax, ebx, ecx, edx;
45 int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
46 int family = 0, model = 0;
47 union { int i[3]; char c[12]; } vendor;
52 /* See if CPUID instruction is supported ... */
53 /* ... Get copies of EFLAGS into eax and ecx */
58 /* ... Toggle the ID bit in one copy and store */
59 /* to the EFLAGS reg */
60 "xor $0x200000, %0\n\t"
64 /* ... Get the (hopefully modified) EFLAGS */
73 return 0; /* CPUID not supported */
76 cpuid(0, max_std_level, ebx, ecx, edx);
81 if (max_std_level >= 1) {
82 cpuid(1, eax, ebx, ecx, std_caps);
83 family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
84 model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
85 if (std_caps & (1 << 15))
86 rval |= AV_CPU_FLAG_CMOV;
87 if (std_caps & (1 << 23))
88 rval |= AV_CPU_FLAG_MMX;
89 if (std_caps & (1 << 25))
90 rval |= AV_CPU_FLAG_MMX2;
92 if (std_caps & (1 << 25))
93 rval |= AV_CPU_FLAG_SSE;
94 if (std_caps & (1 << 26))
95 rval |= AV_CPU_FLAG_SSE2;
97 rval |= AV_CPU_FLAG_SSE3;
98 if (ecx & 0x00000200 )
99 rval |= AV_CPU_FLAG_SSSE3;
100 if (ecx & 0x00080000 )
101 rval |= AV_CPU_FLAG_SSE4;
102 if (ecx & 0x00100000 )
103 rval |= AV_CPU_FLAG_SSE42;
105 /* Check OXSAVE and AVX bits */
106 if ((ecx & 0x18000000) == 0x18000000) {
107 /* Check for OS support */
109 if ((eax & 0x6) == 0x6)
110 rval |= AV_CPU_FLAG_AVX;
116 cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
118 if (max_ext_level >= 0x80000001) {
119 cpuid(0x80000001, eax, ebx, ecx, ext_caps);
120 if (ext_caps & (1U << 31))
121 rval |= AV_CPU_FLAG_3DNOW;
122 if (ext_caps & (1 << 30))
123 rval |= AV_CPU_FLAG_3DNOWEXT;
124 if (ext_caps & (1 << 23))
125 rval |= AV_CPU_FLAG_MMX;
126 if (ext_caps & (1 << 22))
127 rval |= AV_CPU_FLAG_MMX2;
129 /* Allow for selectively disabling SSE2 functions on AMD processors
130 with SSE2 support but not SSE4a. This includes Athlon64, some
131 Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
132 than SSE2 often enough to utilize this special-case flag.
133 AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
134 so that SSE2 is used unless explicitly disabled by checking
135 AV_CPU_FLAG_SSE2SLOW. */
136 if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
137 rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
138 rval |= AV_CPU_FLAG_SSE2SLOW;
141 /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
142 * used unless the OS has AVX support. */
143 if (rval & AV_CPU_FLAG_AVX) {
144 if (ecx & 0x00000800)
145 rval |= AV_CPU_FLAG_XOP;
146 if (ecx & 0x00010000)
147 rval |= AV_CPU_FLAG_FMA4;
151 if (!strncmp(vendor.c, "GenuineIntel", 12)) {
152 if (family == 6 && (model == 9 || model == 13 || model == 14)) {
153 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
154 * 6/14 (core1 "yonah") theoretically support sse2, but it's
155 * usually slower than mmx, so let's just pretend they don't.
156 * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
157 * enabled so that SSE2 is not used unless explicitly enabled
158 * by checking AV_CPU_FLAG_SSE2SLOW. The same situation
159 * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
160 if (rval & AV_CPU_FLAG_SSE2)
161 rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
162 if (rval & AV_CPU_FLAG_SSE3)
163 rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
165 /* The Atom processor has SSSE3 support, which is useful in many cases,
166 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
167 * on the Atom, but is generally faster on other processors supporting
168 * SSSE3. This flag allows for selectively disabling certain SSSE3
169 * functions on the Atom. */
170 if (family == 6 && model == 28)
171 rval |= AV_CPU_FLAG_ATOM;