2 * CPU detection code, extracted from mmx.h
3 * (c)1997-99 by H. Dietz and R. Fisher
4 * Converted to C and improved by Fabrice Bellard.
6 * This file is part of Libav.
8 * Libav is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * Libav is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with Libav; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include "libavutil/x86_cpu.h"
26 #include "libavutil/cpu.h"
29 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
30 #define cpuid(index, eax, ebx, ecx, edx) \
32 "mov %%"REG_b", %%"REG_S" \n\t" \
34 "xchg %%"REG_b", %%"REG_S \
35 : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
40 #define cpuid(index, eax, ebx, ecx, edx) \
43 __cpuid(info, index); \
49 #endif /* HAVE_CPUID */
52 #define xgetbv(index, eax, edx) \
53 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
55 #include <immintrin.h>
57 #define xgetbv(index, eax, edx) \
59 uint64_t res = __xgetbv(index); \
63 #endif /* HAVE_XGETBV */
65 #define get_eflags(x) \
66 __asm__ volatile ("pushfl \n" \
70 #define set_eflags(x) \
71 __asm__ volatile ("push %0 \n" \
75 /* Function to test if multimedia instructions are supported... */
76 int ff_get_cpu_flags_x86(void)
79 int eax, ebx, ecx, edx;
80 int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
81 int family = 0, model = 0;
82 union { int i[3]; char c[12]; } vendor;
87 /* Check if CPUID is supported by attempting to toggle the ID bit in
88 * the EFLAGS register. */
90 set_eflags(a ^ 0x200000);
94 return 0; /* CPUID not supported */
97 cpuid(0, max_std_level, ebx, ecx, edx);
102 if (max_std_level >= 1) {
103 cpuid(1, eax, ebx, ecx, std_caps);
104 family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
105 model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
106 if (std_caps & (1 << 15))
107 rval |= AV_CPU_FLAG_CMOV;
108 if (std_caps & (1 << 23))
109 rval |= AV_CPU_FLAG_MMX;
110 if (std_caps & (1 << 25))
111 rval |= AV_CPU_FLAG_MMX2;
113 if (std_caps & (1 << 25))
114 rval |= AV_CPU_FLAG_SSE;
115 if (std_caps & (1 << 26))
116 rval |= AV_CPU_FLAG_SSE2;
118 rval |= AV_CPU_FLAG_SSE3;
119 if (ecx & 0x00000200 )
120 rval |= AV_CPU_FLAG_SSSE3;
121 if (ecx & 0x00080000 )
122 rval |= AV_CPU_FLAG_SSE4;
123 if (ecx & 0x00100000 )
124 rval |= AV_CPU_FLAG_SSE42;
126 /* Check OXSAVE and AVX bits */
127 if ((ecx & 0x18000000) == 0x18000000) {
128 /* Check for OS support */
130 if ((eax & 0x6) == 0x6)
131 rval |= AV_CPU_FLAG_AVX;
137 cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
139 if (max_ext_level >= 0x80000001) {
140 cpuid(0x80000001, eax, ebx, ecx, ext_caps);
141 if (ext_caps & (1U << 31))
142 rval |= AV_CPU_FLAG_3DNOW;
143 if (ext_caps & (1 << 30))
144 rval |= AV_CPU_FLAG_3DNOWEXT;
145 if (ext_caps & (1 << 23))
146 rval |= AV_CPU_FLAG_MMX;
147 if (ext_caps & (1 << 22))
148 rval |= AV_CPU_FLAG_MMX2;
150 /* Allow for selectively disabling SSE2 functions on AMD processors
151 with SSE2 support but not SSE4a. This includes Athlon64, some
152 Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
153 than SSE2 often enough to utilize this special-case flag.
154 AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
155 so that SSE2 is used unless explicitly disabled by checking
156 AV_CPU_FLAG_SSE2SLOW. */
157 if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
158 rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
159 rval |= AV_CPU_FLAG_SSE2SLOW;
162 /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
163 * used unless the OS has AVX support. */
164 if (rval & AV_CPU_FLAG_AVX) {
165 if (ecx & 0x00000800)
166 rval |= AV_CPU_FLAG_XOP;
167 if (ecx & 0x00010000)
168 rval |= AV_CPU_FLAG_FMA4;
172 if (!strncmp(vendor.c, "GenuineIntel", 12)) {
173 if (family == 6 && (model == 9 || model == 13 || model == 14)) {
174 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
175 * 6/14 (core1 "yonah") theoretically support sse2, but it's
176 * usually slower than mmx, so let's just pretend they don't.
177 * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
178 * enabled so that SSE2 is not used unless explicitly enabled
179 * by checking AV_CPU_FLAG_SSE2SLOW. The same situation
180 * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
181 if (rval & AV_CPU_FLAG_SSE2)
182 rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
183 if (rval & AV_CPU_FLAG_SSE3)
184 rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
186 /* The Atom processor has SSSE3 support, which is useful in many cases,
187 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
188 * on the Atom, but is generally faster on other processors supporting
189 * SSSE3. This flag allows for selectively disabling certain SSSE3
190 * functions on the Atom. */
191 if (family == 6 && model == 28)
192 rval |= AV_CPU_FLAG_ATOM;