2 * CPU detection code, extracted from mmx.h
3 * (c)1997-99 by H. Dietz and R. Fisher
4 * Converted to C and improved by Fabrice Bellard.
6 * This file is part of FFmpeg.
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
26 #include "libavutil/x86/asm.h"
27 #include "libavutil/x86/cpu.h"
28 #include "libavutil/cpu.h"
29 #include "libavutil/cpu_internal.h"
33 #define cpuid(index, eax, ebx, ecx, edx) \
34 ff_cpu_cpuid(index, &eax, &ebx, &ecx, &edx)
36 #define xgetbv(index, eax, edx) \
37 ff_cpu_xgetbv(index, &eax, &edx)
41 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
42 #define cpuid(index, eax, ebx, ecx, edx) \
44 "mov %%"REG_b", %%"REG_S" \n\t" \
46 "xchg %%"REG_b", %%"REG_S \
47 : "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
50 #define xgetbv(index, eax, edx) \
51 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
53 #define get_eflags(x) \
54 __asm__ volatile ("pushfl \n" \
58 #define set_eflags(x) \
59 __asm__ volatile ("push %0 \n" \
63 #endif /* HAVE_INLINE_ASM */
67 #define cpuid_test() 1
71 #define cpuid_test ff_cpu_cpuid_test
75 static int cpuid_test(void)
79 /* Check if CPUID is supported by attempting to toggle the ID bit in
80 * the EFLAGS register. */
82 set_eflags(a ^ 0x200000);
89 /* Function to test if multimedia instructions are supported... */
90 int ff_get_cpu_flags_x86(void)
96 int eax, ebx, ecx, edx;
97 int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0;
98 int family = 0, model = 0;
99 union { int i[3]; char c[12]; } vendor;
102 return 0; /* CPUID not supported */
104 cpuid(0, max_std_level, vendor.i[0], vendor.i[2], vendor.i[1]);
106 if (max_std_level >= 1) {
107 cpuid(1, eax, ebx, ecx, std_caps);
108 family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
109 model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0);
110 if (std_caps & (1 << 15))
111 rval |= AV_CPU_FLAG_CMOV;
112 if (std_caps & (1 << 23))
113 rval |= AV_CPU_FLAG_MMX;
114 if (std_caps & (1 << 25))
115 rval |= AV_CPU_FLAG_MMXEXT;
117 if (std_caps & (1 << 25))
118 rval |= AV_CPU_FLAG_SSE;
119 if (std_caps & (1 << 26))
120 rval |= AV_CPU_FLAG_SSE2;
122 rval |= AV_CPU_FLAG_SSE3;
123 if (ecx & 0x00000200 )
124 rval |= AV_CPU_FLAG_SSSE3;
125 if (ecx & 0x00080000 )
126 rval |= AV_CPU_FLAG_SSE4;
127 if (ecx & 0x00100000 )
128 rval |= AV_CPU_FLAG_SSE42;
130 /* Check OXSAVE and AVX bits */
131 if ((ecx & 0x18000000) == 0x18000000) {
132 /* Check for OS support */
134 if ((eax & 0x6) == 0x6) {
135 rval |= AV_CPU_FLAG_AVX;
137 rval |= AV_CPU_FLAG_FMA3;
140 #endif /* HAVE_AVX */
141 #endif /* HAVE_SSE */
142 if (max_std_level >= 7) {
143 cpuid(7, eax, ebx, ecx, edx);
146 rval |= AV_CPU_FLAG_AVX2;
147 #endif /* HAVE_AVX2 */
148 /* BMI1/2 don't need OS support */
151 rval |= AV_CPU_FLAG_BMI1;
153 rval |= AV_CPU_FLAG_BMI2;
158 cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
160 if (max_ext_level >= 0x80000001) {
161 cpuid(0x80000001, eax, ebx, ecx, ext_caps);
162 if (ext_caps & (1U << 31))
163 rval |= AV_CPU_FLAG_3DNOW;
164 if (ext_caps & (1 << 30))
165 rval |= AV_CPU_FLAG_3DNOWEXT;
166 if (ext_caps & (1 << 23))
167 rval |= AV_CPU_FLAG_MMX;
168 if (ext_caps & (1 << 22))
169 rval |= AV_CPU_FLAG_MMXEXT;
171 /* Allow for selectively disabling SSE2 functions on AMD processors
172 with SSE2 support but not SSE4a. This includes Athlon64, some
173 Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
174 than SSE2 often enough to utilize this special-case flag.
175 AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
176 so that SSE2 is used unless explicitly disabled by checking
177 AV_CPU_FLAG_SSE2SLOW. */
178 if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
179 rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
180 rval |= AV_CPU_FLAG_SSE2SLOW;
183 /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
184 * used unless the OS has AVX support. */
185 if (rval & AV_CPU_FLAG_AVX) {
186 if (ecx & 0x00000800)
187 rval |= AV_CPU_FLAG_XOP;
188 if (ecx & 0x00010000)
189 rval |= AV_CPU_FLAG_FMA4;
193 if (!strncmp(vendor.c, "GenuineIntel", 12)) {
194 if (family == 6 && (model == 9 || model == 13 || model == 14)) {
195 /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
196 * 6/14 (core1 "yonah") theoretically support sse2, but it's
197 * usually slower than mmx, so let's just pretend they don't.
198 * AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
199 * enabled so that SSE2 is not used unless explicitly enabled
200 * by checking AV_CPU_FLAG_SSE2SLOW. The same situation
201 * applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
202 if (rval & AV_CPU_FLAG_SSE2)
203 rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
204 if (rval & AV_CPU_FLAG_SSE3)
205 rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
207 /* The Atom processor has SSSE3 support, which is useful in many cases,
208 * but sometimes the SSSE3 version is slower than the SSE2 equivalent
209 * on the Atom, but is generally faster on other processors supporting
210 * SSSE3. This flag allows for selectively disabling certain SSSE3
211 * functions on the Atom. */
212 if (family == 6 && model == 28)
213 rval |= AV_CPU_FLAG_ATOM;