1 ;*****************************************************************************
2 ;* x86inc.asm: x264asm abstraction layer
3 ;*****************************************************************************
4 ;* Copyright (C) 2005-2016 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Anton Mitrofanov <BugMaster@narod.ru>
8 ;* Fiona Glaser <fiona@x264.com>
9 ;* Henrik Gramner <henrik@gramner.com>
11 ;* Permission to use, copy, modify, and/or distribute this software for any
12 ;* purpose with or without fee is hereby granted, provided that the above
13 ;* copyright notice and this permission notice appear in all copies.
15 ;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 ;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 ;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 ;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 ;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 ;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 ;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 ;*****************************************************************************
24 ; This is a header file for the x264ASM assembly language, which uses
25 ; NASM/YASM syntax combined with a large number of macros to provide easy
26 ; abstraction between different calling conventions (x86_32, win64, linux64).
27 ; It also has various other useful features to simplify writing the kind of
28 ; DSP functions that are most often used in x264.
30 ; Unlike the rest of x264, this file is available under an ISC license, as it
31 ; has significant usefulness outside of x264 and we want it to be available
32 ; to the largest audience possible. Of course, if you modify it for your own
33 ; purposes to add a new feature, we strongly encourage contributing a patch
34 ; as this feature might be useful for others as well. Send patches or ideas
35 ; to x264-devel@videolan.org .
37 %ifndef private_prefix
38 %define private_prefix x264
42 %define public_prefix private_prefix
45 %if HAVE_ALIGNED_STACK
46 %define STACK_ALIGNMENT 16
48 %ifndef STACK_ALIGNMENT
50 %define STACK_ALIGNMENT 16
52 %define STACK_ALIGNMENT 4
59 %ifidn __OUTPUT_FORMAT__,win32
61 %elifidn __OUTPUT_FORMAT__,win64
63 %elifidn __OUTPUT_FORMAT__,x64
71 %ifidn __OUTPUT_FORMAT__,elf
73 %elifidn __OUTPUT_FORMAT__,elf32
75 %elifidn __OUTPUT_FORMAT__,elf64
80 %define mangle(x) _ %+ x
85 ; aout does not support align=
86 ; NOTE: This section is out of sync with x264, in order to
87 ; keep supporting OS/2.
88 %macro SECTION_RODATA 0-1 16
89 %ifidn __OUTPUT_FORMAT__,aout
92 SECTION .rodata align=%1
98 %elif ARCH_X86_64 == 0
99 ; x86_32 doesn't require PIC.
100 ; Some distros prefer shared objects to be PIC, but nothing breaks if
101 ; the code contains a few textrels, so we'll skip that complexity.
114 ; Macros to eliminate most code duplication between x86_32 and x86_64:
115 ; Currently this works only for leaf functions which load all their arguments
116 ; into registers at the start, and make no other use of the stack. Luckily that
117 ; covers most of x264's asm.
120 ; %1 = number of arguments. loads them from stack if needed.
121 ; %2 = number of registers used. pushes callee-saved regs if needed.
122 ; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
123 ; %4 = (optional) stack size to be allocated. The stack will be aligned before
124 ; allocating the specified stack size. If the required stack alignment is
125 ; larger than the known stack alignment the stack will be manually aligned
126 ; and an extra register will be allocated to hold the original stack
127 ; pointer (to not invalidate r0m etc.). To prevent the use of an extra
128 ; register as stack pointer, request a negative stack size.
129 ; %4+/%5+ = list of names to define to registers
130 ; PROLOGUE can also be invoked by adding the same options to cglobal
133 ; cglobal foo, 2,3,7,0x40, dst, src, tmp
134 ; declares a function (foo) that automatically loads two arguments (dst and
135 ; src) into registers, uses one additional register (tmp) plus 7 vector
136 ; registers (m0-m6) and allocates 0x40 bytes of stack space.
138 ; TODO Some functions can use some args directly from the stack. If they're the
139 ; last args then you can just not declare them, but if they're in the middle
140 ; we need more flexible macro.
143 ; Pops anything that was pushed by PROLOGUE, and returns.
146 ; Use this instead of RET if it's a branch target.
149 ; rN and rNq are the native-size register holding function argument N
150 ; rNd, rNw, rNb are dword, word, and byte size
151 ; rNh is the high 8 bits of the word size
152 ; rNm is the original location of arg N (a register or on the stack), dword
153 ; rNmp is native size
155 %macro DECLARE_REG 2-3
165 %elif ARCH_X86_64 ; memory
166 %define r%1m [rstk + stack_offset + %3]
167 %define r%1mp qword r %+ %1 %+ m
169 %define r%1m [rstk + stack_offset + %3]
170 %define r%1mp dword r %+ %1 %+ m
175 %macro DECLARE_REG_SIZE 3
191 DECLARE_REG_SIZE ax, al, ah
192 DECLARE_REG_SIZE bx, bl, bh
193 DECLARE_REG_SIZE cx, cl, ch
194 DECLARE_REG_SIZE dx, dl, dh
195 DECLARE_REG_SIZE si, sil, null
196 DECLARE_REG_SIZE di, dil, null
197 DECLARE_REG_SIZE bp, bpl, null
199 ; t# defines for when per-arch register allocation is more complex than just function arguments
201 %macro DECLARE_REG_TMP 1-*
204 CAT_XDEFINE t, %%i, r%1
210 %macro DECLARE_REG_TMP_SIZE 0-*
212 %define t%1q t%1 %+ q
213 %define t%1d t%1 %+ d
214 %define t%1w t%1 %+ w
215 %define t%1h t%1 %+ h
216 %define t%1b t%1 %+ b
221 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
232 %assign stack_offset stack_offset+gprsize
239 %assign stack_offset stack_offset-gprsize
243 %macro PUSH_IF_USED 1-*
252 %macro POP_IF_USED 1-*
261 %macro LOAD_IF_USED 1-*
264 mov r%1, r %+ %1 %+ mp
273 %assign stack_offset stack_offset+(%2)
280 %assign stack_offset stack_offset-(%2)
290 %macro movsxdifnidn 2
298 %error assertion ``%1'' failed
302 %macro DEFINE_ARGS 0-*
306 CAT_UNDEF arg_name %+ %%i, q
307 CAT_UNDEF arg_name %+ %%i, d
308 CAT_UNDEF arg_name %+ %%i, w
309 CAT_UNDEF arg_name %+ %%i, h
310 CAT_UNDEF arg_name %+ %%i, b
311 CAT_UNDEF arg_name %+ %%i, m
312 CAT_UNDEF arg_name %+ %%i, mp
313 CAT_UNDEF arg_name, %%i
318 %xdefine %%stack_offset stack_offset
319 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
322 %xdefine %1q r %+ %%i %+ q
323 %xdefine %1d r %+ %%i %+ d
324 %xdefine %1w r %+ %%i %+ w
325 %xdefine %1h r %+ %%i %+ h
326 %xdefine %1b r %+ %%i %+ b
327 %xdefine %1m r %+ %%i %+ m
328 %xdefine %1mp r %+ %%i %+ mp
329 CAT_XDEFINE arg_name, %%i, %1
333 %xdefine stack_offset %%stack_offset
334 %assign n_arg_names %0
337 %define required_stack_alignment ((mmsize + 15) & ~15)
339 %macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
343 %assign stack_size %1
345 %assign stack_size -stack_size
348 %assign %%pad %%pad + 32 ; shadow space
350 %assign xmm_regs_used %2
351 %if xmm_regs_used > 8
352 %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers
356 %if required_stack_alignment <= STACK_ALIGNMENT
357 ; maintain the current stack alignment
358 %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
359 SUB rsp, stack_size_padded
361 %assign %%reg_num (regs_used - 1)
362 %xdefine rstk r %+ %%reg_num
363 ; align stack, and save original stack location directly above
364 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
365 ; stack in a single instruction (i.e. mov rsp, rstk or mov
366 ; rsp, [rsp+stack_size_padded])
367 %if %1 < 0 ; need to store rsp on stack
368 %xdefine rstkm [rsp + stack_size + %%pad]
369 %assign %%pad %%pad + gprsize
370 %else ; can keep rsp in rstk during whole function
373 %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))
375 and rsp, ~(required_stack_alignment-1)
376 sub rsp, stack_size_padded
377 movifnidn rstkm, rstk
384 %macro SETUP_STACK_POINTER 1
386 %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT
388 %assign regs_used (regs_used + 1)
390 %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3
391 ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)
392 ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.
393 %assign regs_used 5 + UNIX64 * 3
399 %macro DEFINE_ARGS_INTERNAL 3+
409 %if WIN64 ; Windows x64 ;=================================================
415 DECLARE_REG 4, R10, 40
416 DECLARE_REG 5, R11, 48
417 DECLARE_REG 6, rax, 56
418 DECLARE_REG 7, rdi, 64
419 DECLARE_REG 8, rsi, 72
420 DECLARE_REG 9, rbx, 80
421 DECLARE_REG 10, rbp, 88
422 DECLARE_REG 11, R12, 96
423 DECLARE_REG 12, R13, 104
424 DECLARE_REG 13, R14, 112
425 DECLARE_REG 14, R15, 120
427 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
430 ASSERT regs_used >= num_args
431 SETUP_STACK_POINTER %4
432 ASSERT regs_used <= 15
433 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
435 %if mmsize != 8 && stack_size == 0
438 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
439 DEFINE_ARGS_INTERNAL %0, %4, %5
442 %macro WIN64_PUSH_XMM 0
443 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
444 %if xmm_regs_used > 6
445 movaps [rstk + stack_offset + 8], xmm6
447 %if xmm_regs_used > 7
448 movaps [rstk + stack_offset + 24], xmm7
450 %if xmm_regs_used > 8
453 movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
459 %macro WIN64_SPILL_XMM 1
460 %assign xmm_regs_used %1
461 ASSERT xmm_regs_used <= 16
462 %if xmm_regs_used > 8
463 ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.
464 %assign %%pad (xmm_regs_used-8)*16 + 32
465 %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
466 SUB rsp, stack_size_padded
471 %macro WIN64_RESTORE_XMM_INTERNAL 1
473 %if xmm_regs_used > 8
474 %assign %%i xmm_regs_used
477 movaps xmm %+ %%i, [%1 + (%%i-8)*16 + stack_size + 32]
480 %if stack_size_padded > 0
481 %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT
484 add %1, stack_size_padded
485 %assign %%pad_size stack_size_padded
488 %if xmm_regs_used > 7
489 movaps xmm7, [%1 + stack_offset - %%pad_size + 24]
491 %if xmm_regs_used > 6
492 movaps xmm6, [%1 + stack_offset - %%pad_size + 8]
496 %macro WIN64_RESTORE_XMM 1
497 WIN64_RESTORE_XMM_INTERNAL %1
498 %assign stack_offset (stack_offset-stack_size_padded)
499 %assign xmm_regs_used 0
502 %define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
505 WIN64_RESTORE_XMM_INTERNAL rsp
506 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
513 %elif ARCH_X86_64 ; *nix x64 ;=============================================
521 DECLARE_REG 6, rax, 8
522 DECLARE_REG 7, R10, 16
523 DECLARE_REG 8, R11, 24
524 DECLARE_REG 9, rbx, 32
525 DECLARE_REG 10, rbp, 40
526 DECLARE_REG 11, R12, 48
527 DECLARE_REG 12, R13, 56
528 DECLARE_REG 13, R14, 64
529 DECLARE_REG 14, R15, 72
531 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
534 ASSERT regs_used >= num_args
535 SETUP_STACK_POINTER %4
536 ASSERT regs_used <= 15
537 PUSH_IF_USED 9, 10, 11, 12, 13, 14
539 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
540 DEFINE_ARGS_INTERNAL %0, %4, %5
543 %define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
546 %if stack_size_padded > 0
547 %if required_stack_alignment > STACK_ALIGNMENT
550 add rsp, stack_size_padded
553 POP_IF_USED 14, 13, 12, 11, 10, 9
560 %else ; X86_32 ;==============================================================
562 DECLARE_REG 0, eax, 4
563 DECLARE_REG 1, ecx, 8
564 DECLARE_REG 2, edx, 12
565 DECLARE_REG 3, ebx, 16
566 DECLARE_REG 4, esi, 20
567 DECLARE_REG 5, edi, 24
568 DECLARE_REG 6, ebp, 28
571 %macro DECLARE_ARG 1-*
573 %define r%1m [rstk + stack_offset + 4*%1 + 4]
574 %define r%1mp dword r%1m
579 DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
581 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
584 ASSERT regs_used >= num_args
591 SETUP_STACK_POINTER %4
592 ASSERT regs_used <= 7
593 PUSH_IF_USED 3, 4, 5, 6
595 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
596 DEFINE_ARGS_INTERNAL %0, %4, %5
599 %define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
602 %if stack_size_padded > 0
603 %if required_stack_alignment > STACK_ALIGNMENT
606 add rsp, stack_size_padded
609 POP_IF_USED 6, 5, 4, 3
616 %endif ;======================================================================
619 %macro WIN64_SPILL_XMM 1
621 %macro WIN64_RESTORE_XMM 1
623 %macro WIN64_PUSH_XMM 0
627 ; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
628 ; a branch or a branch target. So switch to a 2-byte form of ret in that case.
629 ; We can automatically detect "follows a branch", but not a branch target.
630 ; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
637 annotate_function_size
640 %define last_branch_adr $$
641 %macro AUTO_REP_RET 0
642 %if notcpuflag(ssse3)
643 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ == last_branch_adr.
646 annotate_function_size
649 %macro BRANCH_INSTR 0-*
653 %if notcpuflag(ssse3)
655 %xdefine last_branch_adr %%branch_instr
662 BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
664 %macro TAIL_CALL 2 ; callee, is_nonadjacent
671 annotate_function_size
674 ;=============================================================================
675 ; arch-independent part
676 ;=============================================================================
678 %assign function_align 16
681 ; Applies any symbol mangling needed for C linkage, and sets up a define such that
682 ; subsequent uses of the function name automatically refer to the mangled version.
683 ; Appends cpuflags to the function name if cpuflags has been specified.
684 ; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
685 ; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
686 %macro cglobal 1-2+ "" ; name, [PROLOGUE args]
687 cglobal_internal 1, %1 %+ SUFFIX, %2
689 %macro cvisible 1-2+ "" ; name, [PROLOGUE args]
690 cglobal_internal 0, %1 %+ SUFFIX, %2
692 %macro cglobal_internal 2-3+
693 annotate_function_size
695 %xdefine %%FUNCTION_PREFIX private_prefix
696 %xdefine %%VISIBILITY hidden
698 %xdefine %%FUNCTION_PREFIX public_prefix
699 %xdefine %%VISIBILITY
702 %xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
703 %xdefine %2.skip_prologue %2 %+ .skip_prologue
704 CAT_XDEFINE cglobaled_, %2, 1
706 %xdefine current_function %2
707 %xdefine current_function_section __SECT__
709 global %2:function %%VISIBILITY
715 RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
716 %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
717 %assign stack_offset 0 ; stack pointer offset relative to the return address
718 %assign stack_size 0 ; amount of stack space that can be freely used inside a function
719 %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
720 %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
727 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
728 CAT_XDEFINE cglobaled_, %1, 1
732 ; like cextern, but without the prefix
733 %macro cextern_naked 1
735 %xdefine %1 mangle(%1)
737 CAT_XDEFINE cglobaled_, %1, 1
742 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
744 global %1:data hidden
751 ; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.
753 [SECTION .note.GNU-stack noalloc noexec nowrite progbits]
756 ; Tell debuggers how large the function was.
757 ; This may be invoked multiple times per function; we rely on later instances overriding earlier ones.
758 ; This is invoked by RET and similar macros, and also cglobal does it for the previous function,
759 ; but if the last function in a source file doesn't use any of the standard macros for its epilogue,
760 ; then its size might be unspecified.
761 %macro annotate_function_size 0
763 %ifdef current_function
765 current_function_section
767 size current_function %%ecf - current_function
776 %assign cpuflags_mmx (1<<0)
777 %assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
778 %assign cpuflags_3dnow (1<<2) | cpuflags_mmx
779 %assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
780 %assign cpuflags_sse (1<<4) | cpuflags_mmx2
781 %assign cpuflags_sse2 (1<<5) | cpuflags_sse
782 %assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
783 %assign cpuflags_sse3 (1<<7) | cpuflags_sse2
784 %assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
785 %assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
786 %assign cpuflags_sse42 (1<<10)| cpuflags_sse4
787 %assign cpuflags_avx (1<<11)| cpuflags_sse42
788 %assign cpuflags_xop (1<<12)| cpuflags_avx
789 %assign cpuflags_fma4 (1<<13)| cpuflags_avx
790 %assign cpuflags_fma3 (1<<14)| cpuflags_avx
791 %assign cpuflags_avx2 (1<<15)| cpuflags_fma3
793 %assign cpuflags_cache32 (1<<16)
794 %assign cpuflags_cache64 (1<<17)
795 %assign cpuflags_slowctz (1<<18)
796 %assign cpuflags_lzcnt (1<<19)
797 %assign cpuflags_aligned (1<<20) ; not a cpu feature, but a function variant
798 %assign cpuflags_atom (1<<21)
799 %assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
800 %assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
801 %assign cpuflags_aesni (1<<24)|cpuflags_sse42
803 ; Returns a boolean value expressing whether or not the specified cpuflag is enabled.
804 %define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)
805 %define notcpuflag(x) (cpuflag(x) ^ 1)
807 ; Takes an arbitrary number of cpuflags from the above list.
808 ; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
809 ; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
810 %macro INIT_CPUFLAGS 0-*
818 %xdefine cpuname cpuname %+ _%1
822 %assign cpuflags cpuflags | cpuflags_%1
825 %xdefine SUFFIX _ %+ cpuname
828 %assign avx_enabled 1
830 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
833 %define movnta movntps
837 %elif cpuflag(sse3) && notcpuflag(ssse3)
842 %if ARCH_X86_64 || cpuflag(sse2)
850 ; m# is a simd register of the currently selected size
851 ; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
852 ; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
853 ; (All 3 remain in sync through SWAP.)
864 %assign avx_enabled 0
865 %define RESET_MM_PERMUTATION INIT_MMX %1
871 %define movnta movntq
874 CAT_XDEFINE m, %%i, mm %+ %%i
875 CAT_XDEFINE nnmm, %%i, %%i
887 %assign avx_enabled 0
888 %define RESET_MM_PERMUTATION INIT_XMM %1
892 %define num_mmregs 16
897 %define movnta movntdq
900 CAT_XDEFINE m, %%i, xmm %+ %%i
901 CAT_XDEFINE nnxmm, %%i, %%i
908 %assign avx_enabled 1
909 %define RESET_MM_PERMUTATION INIT_YMM %1
913 %define num_mmregs 16
918 %define movnta movntdq
921 CAT_XDEFINE m, %%i, ymm %+ %%i
922 CAT_XDEFINE nnymm, %%i, %%i
930 %macro DECLARE_MMCAST 1
935 %define xmmxmm%1 xmm%1
936 %define xmmymm%1 xmm%1
938 %define ymmxmm%1 xmm%1
939 %define ymmymm%1 ymm%1
940 %define xm%1 xmm %+ m%1
941 %define ym%1 ymm %+ m%1
950 ; I often want to use macros that permute their arguments. e.g. there's no
951 ; efficient way to implement butterfly or transpose or dct without swapping some
954 ; I would like to not have to manually keep track of the permutations:
955 ; If I insert a permutation in the middle of a function, it should automatically
956 ; change everything that follows. For more complex macros I may also have multiple
957 ; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
959 ; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
960 ; permutes its arguments. It's equivalent to exchanging the contents of the
961 ; registers, except that this way you exchange the register names instead, so it
962 ; doesn't cost any cycles.
964 %macro PERMUTE 2-* ; takes a list of pairs to swap
971 CAT_XDEFINE nn, m%1, %1
976 %macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
977 %ifnum %1 ; SWAP 0, 1, ...
978 SWAP_INTERNAL_NUM %1, %2
979 %else ; SWAP m0, m1, ...
980 SWAP_INTERNAL_NAME %1, %2
984 %macro SWAP_INTERNAL_NUM 2-*
989 CAT_XDEFINE nn, m%1, %1
990 CAT_XDEFINE nn, m%2, %2
995 %macro SWAP_INTERNAL_NAME 2-*
996 %xdefine %%args nn %+ %1
998 %xdefine %%args %%args, nn %+ %2
1001 SWAP_INTERNAL_NUM %%args
1004 ; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
1005 ; calls to that function will automatically load the permutation, so values can
1006 ; be returned in mmregs.
1007 %macro SAVE_MM_PERMUTATION 0-1
1011 %xdefine %%f current_function %+ _m
1015 CAT_XDEFINE %%f, %%i, m %+ %%i
1020 %macro LOAD_MM_PERMUTATION 1 ; name to load from
1024 CAT_XDEFINE m, %%i, %1_m %+ %%i
1025 CAT_XDEFINE nn, m %+ %%i, %%i
1031 ; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
1033 call_internal %1 %+ SUFFIX, %1
1035 %macro call_internal 2
1037 %ifndef cglobaled_%2
1043 LOAD_MM_PERMUTATION %%i
1046 ; Substitutions that reduce instruction size but are functionally equivalent
1071 ;=============================================================================
1072 ; AVX abstraction layer
1073 ;=============================================================================
1078 CAT_XDEFINE sizeofmm, i, 8
1080 CAT_XDEFINE sizeofxmm, i, 16
1081 CAT_XDEFINE sizeofymm, i, 32
1086 %macro CHECK_AVX_INSTR_EMU 3-*
1087 %xdefine %%opcode %1
1091 %error non-avx emulation of ``%%opcode'' is not supported
1098 ;%2 == minimal instruction set
1099 ;%3 == 1 if float, 0 if int
1100 ;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1101 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1103 %macro RUN_AVX_INSTR 6-9+
1105 %assign __sizeofreg sizeof%7
1107 %assign __sizeofreg sizeof%6
1109 %assign __sizeofreg mmsize
1111 %assign __emulate_avx 0
1112 %if avx_enabled && __sizeofreg >= 16
1113 %xdefine __instr v%1
1117 %assign __emulate_avx 1
1123 %error use of ``%1'' %2 instruction in cpuname function: current_function
1124 %elif cpuflags_%2 < cpuflags_sse && notcpuflag(sse2) && __sizeofreg > 8
1125 %error use of ``%1'' sse2 instruction in cpuname function: current_function
1135 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, %8, %9
1137 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, %8
1141 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1142 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1143 ; So, if the instruction is commutative with a memory arg, swap them.
1148 %if __sizeofreg == 8
1162 __instr %6, %7, %8, %9
1173 ;%2 == minimal instruction set
1174 ;%3 == 1 if float, 0 if int
1175 ;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1176 ;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1177 %macro AVX_INSTR 1-5 fnord, 0, 1, 0
1178 %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5
1180 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1
1182 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2
1184 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3
1186 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4
1188 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5
1193 ; Instructions with both VEX and non-VEX encodings
1194 ; Non-destructive instructions are written without parameters
1195 AVX_INSTR addpd, sse2, 1, 0, 1
1196 AVX_INSTR addps, sse, 1, 0, 1
1197 AVX_INSTR addsd, sse2, 1, 0, 1
1198 AVX_INSTR addss, sse, 1, 0, 1
1199 AVX_INSTR addsubpd, sse3, 1, 0, 0
1200 AVX_INSTR addsubps, sse3, 1, 0, 0
1201 AVX_INSTR aesdec, aesni, 0, 0, 0
1202 AVX_INSTR aesdeclast, aesni, 0, 0, 0
1203 AVX_INSTR aesenc, aesni, 0, 0, 0
1204 AVX_INSTR aesenclast, aesni, 0, 0, 0
1205 AVX_INSTR aesimc, aesni
1206 AVX_INSTR aeskeygenassist, aesni
1207 AVX_INSTR andnpd, sse2, 1, 0, 0
1208 AVX_INSTR andnps, sse, 1, 0, 0
1209 AVX_INSTR andpd, sse2, 1, 0, 1
1210 AVX_INSTR andps, sse, 1, 0, 1
1211 AVX_INSTR blendpd, sse4, 1, 0, 0
1212 AVX_INSTR blendps, sse4, 1, 0, 0
1213 AVX_INSTR blendvpd, sse4, 1, 0, 0
1214 AVX_INSTR blendvps, sse4, 1, 0, 0
1215 AVX_INSTR cmppd, sse2, 1, 1, 0
1216 AVX_INSTR cmpps, sse, 1, 1, 0
1217 AVX_INSTR cmpsd, sse2, 1, 1, 0
1218 AVX_INSTR cmpss, sse, 1, 1, 0
1219 AVX_INSTR comisd, sse2
1220 AVX_INSTR comiss, sse
1221 AVX_INSTR cvtdq2pd, sse2
1222 AVX_INSTR cvtdq2ps, sse2
1223 AVX_INSTR cvtpd2dq, sse2
1224 AVX_INSTR cvtpd2ps, sse2
1225 AVX_INSTR cvtps2dq, sse2
1226 AVX_INSTR cvtps2pd, sse2
1227 AVX_INSTR cvtsd2si, sse2
1228 AVX_INSTR cvtsd2ss, sse2
1229 AVX_INSTR cvtsi2sd, sse2
1230 AVX_INSTR cvtsi2ss, sse
1231 AVX_INSTR cvtss2sd, sse2
1232 AVX_INSTR cvtss2si, sse
1233 AVX_INSTR cvttpd2dq, sse2
1234 AVX_INSTR cvttps2dq, sse2
1235 AVX_INSTR cvttsd2si, sse2
1236 AVX_INSTR cvttss2si, sse
1237 AVX_INSTR divpd, sse2, 1, 0, 0
1238 AVX_INSTR divps, sse, 1, 0, 0
1239 AVX_INSTR divsd, sse2, 1, 0, 0
1240 AVX_INSTR divss, sse, 1, 0, 0
1241 AVX_INSTR dppd, sse4, 1, 1, 0
1242 AVX_INSTR dpps, sse4, 1, 1, 0
1243 AVX_INSTR extractps, sse4
1244 AVX_INSTR haddpd, sse3, 1, 0, 0
1245 AVX_INSTR haddps, sse3, 1, 0, 0
1246 AVX_INSTR hsubpd, sse3, 1, 0, 0
1247 AVX_INSTR hsubps, sse3, 1, 0, 0
1248 AVX_INSTR insertps, sse4, 1, 1, 0
1249 AVX_INSTR lddqu, sse3
1250 AVX_INSTR ldmxcsr, sse
1251 AVX_INSTR maskmovdqu, sse2
1252 AVX_INSTR maxpd, sse2, 1, 0, 1
1253 AVX_INSTR maxps, sse, 1, 0, 1
1254 AVX_INSTR maxsd, sse2, 1, 0, 1
1255 AVX_INSTR maxss, sse, 1, 0, 1
1256 AVX_INSTR minpd, sse2, 1, 0, 1
1257 AVX_INSTR minps, sse, 1, 0, 1
1258 AVX_INSTR minsd, sse2, 1, 0, 1
1259 AVX_INSTR minss, sse, 1, 0, 1
1260 AVX_INSTR movapd, sse2
1261 AVX_INSTR movaps, sse
1263 AVX_INSTR movddup, sse3
1264 AVX_INSTR movdqa, sse2
1265 AVX_INSTR movdqu, sse2
1266 AVX_INSTR movhlps, sse, 1, 0, 0
1267 AVX_INSTR movhpd, sse2, 1, 0, 0
1268 AVX_INSTR movhps, sse, 1, 0, 0
1269 AVX_INSTR movlhps, sse, 1, 0, 0
1270 AVX_INSTR movlpd, sse2, 1, 0, 0
1271 AVX_INSTR movlps, sse, 1, 0, 0
1272 AVX_INSTR movmskpd, sse2
1273 AVX_INSTR movmskps, sse
1274 AVX_INSTR movntdq, sse2
1275 AVX_INSTR movntdqa, sse4
1276 AVX_INSTR movntpd, sse2
1277 AVX_INSTR movntps, sse
1279 AVX_INSTR movsd, sse2, 1, 0, 0
1280 AVX_INSTR movshdup, sse3
1281 AVX_INSTR movsldup, sse3
1282 AVX_INSTR movss, sse, 1, 0, 0
1283 AVX_INSTR movupd, sse2
1284 AVX_INSTR movups, sse
1285 AVX_INSTR mpsadbw, sse4
1286 AVX_INSTR mulpd, sse2, 1, 0, 1
1287 AVX_INSTR mulps, sse, 1, 0, 1
1288 AVX_INSTR mulsd, sse2, 1, 0, 1
1289 AVX_INSTR mulss, sse, 1, 0, 1
1290 AVX_INSTR orpd, sse2, 1, 0, 1
1291 AVX_INSTR orps, sse, 1, 0, 1
1292 AVX_INSTR pabsb, ssse3
1293 AVX_INSTR pabsd, ssse3
1294 AVX_INSTR pabsw, ssse3
1295 AVX_INSTR packsswb, mmx, 0, 0, 0
1296 AVX_INSTR packssdw, mmx, 0, 0, 0
1297 AVX_INSTR packuswb, mmx, 0, 0, 0
1298 AVX_INSTR packusdw, sse4, 0, 0, 0
1299 AVX_INSTR paddb, mmx, 0, 0, 1
1300 AVX_INSTR paddw, mmx, 0, 0, 1
1301 AVX_INSTR paddd, mmx, 0, 0, 1
1302 AVX_INSTR paddq, sse2, 0, 0, 1
1303 AVX_INSTR paddsb, mmx, 0, 0, 1
1304 AVX_INSTR paddsw, mmx, 0, 0, 1
1305 AVX_INSTR paddusb, mmx, 0, 0, 1
1306 AVX_INSTR paddusw, mmx, 0, 0, 1
1307 AVX_INSTR palignr, ssse3
1308 AVX_INSTR pand, mmx, 0, 0, 1
1309 AVX_INSTR pandn, mmx, 0, 0, 0
1310 AVX_INSTR pavgb, mmx2, 0, 0, 1
1311 AVX_INSTR pavgw, mmx2, 0, 0, 1
1312 AVX_INSTR pblendvb, sse4, 0, 0, 0
1313 AVX_INSTR pblendw, sse4
1315 AVX_INSTR pcmpestri, sse42
1316 AVX_INSTR pcmpestrm, sse42
1317 AVX_INSTR pcmpistri, sse42
1318 AVX_INSTR pcmpistrm, sse42
1319 AVX_INSTR pcmpeqb, mmx, 0, 0, 1
1320 AVX_INSTR pcmpeqw, mmx, 0, 0, 1
1321 AVX_INSTR pcmpeqd, mmx, 0, 0, 1
1322 AVX_INSTR pcmpeqq, sse4, 0, 0, 1
1323 AVX_INSTR pcmpgtb, mmx, 0, 0, 0
1324 AVX_INSTR pcmpgtw, mmx, 0, 0, 0
1325 AVX_INSTR pcmpgtd, mmx, 0, 0, 0
1326 AVX_INSTR pcmpgtq, sse42, 0, 0, 0
1327 AVX_INSTR pextrb, sse4
1328 AVX_INSTR pextrd, sse4
1329 AVX_INSTR pextrq, sse4
1330 AVX_INSTR pextrw, mmx2
1331 AVX_INSTR phaddw, ssse3, 0, 0, 0
1332 AVX_INSTR phaddd, ssse3, 0, 0, 0
1333 AVX_INSTR phaddsw, ssse3, 0, 0, 0
1334 AVX_INSTR phminposuw, sse4
1335 AVX_INSTR phsubw, ssse3, 0, 0, 0
1336 AVX_INSTR phsubd, ssse3, 0, 0, 0
1337 AVX_INSTR phsubsw, ssse3, 0, 0, 0
1338 AVX_INSTR pinsrb, sse4
1339 AVX_INSTR pinsrd, sse4
1340 AVX_INSTR pinsrq, sse4
1341 AVX_INSTR pinsrw, mmx2
1342 AVX_INSTR pmaddwd, mmx, 0, 0, 1
1343 AVX_INSTR pmaddubsw, ssse3, 0, 0, 0
1344 AVX_INSTR pmaxsb, sse4, 0, 0, 1
1345 AVX_INSTR pmaxsw, mmx2, 0, 0, 1
1346 AVX_INSTR pmaxsd, sse4, 0, 0, 1
1347 AVX_INSTR pmaxub, mmx2, 0, 0, 1
1348 AVX_INSTR pmaxuw, sse4, 0, 0, 1
1349 AVX_INSTR pmaxud, sse4, 0, 0, 1
1350 AVX_INSTR pminsb, sse4, 0, 0, 1
1351 AVX_INSTR pminsw, mmx2, 0, 0, 1
1352 AVX_INSTR pminsd, sse4, 0, 0, 1
1353 AVX_INSTR pminub, mmx2, 0, 0, 1
1354 AVX_INSTR pminuw, sse4, 0, 0, 1
1355 AVX_INSTR pminud, sse4, 0, 0, 1
1356 AVX_INSTR pmovmskb, mmx2
1357 AVX_INSTR pmovsxbw, sse4
1358 AVX_INSTR pmovsxbd, sse4
1359 AVX_INSTR pmovsxbq, sse4
1360 AVX_INSTR pmovsxwd, sse4
1361 AVX_INSTR pmovsxwq, sse4
1362 AVX_INSTR pmovsxdq, sse4
1363 AVX_INSTR pmovzxbw, sse4
1364 AVX_INSTR pmovzxbd, sse4
1365 AVX_INSTR pmovzxbq, sse4
1366 AVX_INSTR pmovzxwd, sse4
1367 AVX_INSTR pmovzxwq, sse4
1368 AVX_INSTR pmovzxdq, sse4
1369 AVX_INSTR pmuldq, sse4, 0, 0, 1
1370 AVX_INSTR pmulhrsw, ssse3, 0, 0, 1
1371 AVX_INSTR pmulhuw, mmx2, 0, 0, 1
1372 AVX_INSTR pmulhw, mmx, 0, 0, 1
1373 AVX_INSTR pmullw, mmx, 0, 0, 1
1374 AVX_INSTR pmulld, sse4, 0, 0, 1
1375 AVX_INSTR pmuludq, sse2, 0, 0, 1
1376 AVX_INSTR por, mmx, 0, 0, 1
1377 AVX_INSTR psadbw, mmx2, 0, 0, 1
1378 AVX_INSTR pshufb, ssse3, 0, 0, 0
1379 AVX_INSTR pshufd, sse2
1380 AVX_INSTR pshufhw, sse2
1381 AVX_INSTR pshuflw, sse2
1382 AVX_INSTR psignb, ssse3, 0, 0, 0
1383 AVX_INSTR psignw, ssse3, 0, 0, 0
1384 AVX_INSTR psignd, ssse3, 0, 0, 0
1385 AVX_INSTR psllw, mmx, 0, 0, 0
1386 AVX_INSTR pslld, mmx, 0, 0, 0
1387 AVX_INSTR psllq, mmx, 0, 0, 0
1388 AVX_INSTR pslldq, sse2, 0, 0, 0
1389 AVX_INSTR psraw, mmx, 0, 0, 0
1390 AVX_INSTR psrad, mmx, 0, 0, 0
1391 AVX_INSTR psrlw, mmx, 0, 0, 0
1392 AVX_INSTR psrld, mmx, 0, 0, 0
1393 AVX_INSTR psrlq, mmx, 0, 0, 0
1394 AVX_INSTR psrldq, sse2, 0, 0, 0
1395 AVX_INSTR psubb, mmx, 0, 0, 0
1396 AVX_INSTR psubw, mmx, 0, 0, 0
1397 AVX_INSTR psubd, mmx, 0, 0, 0
1398 AVX_INSTR psubq, sse2, 0, 0, 0
1399 AVX_INSTR psubsb, mmx, 0, 0, 0
1400 AVX_INSTR psubsw, mmx, 0, 0, 0
1401 AVX_INSTR psubusb, mmx, 0, 0, 0
1402 AVX_INSTR psubusw, mmx, 0, 0, 0
1403 AVX_INSTR ptest, sse4
1404 AVX_INSTR punpckhbw, mmx, 0, 0, 0
1405 AVX_INSTR punpckhwd, mmx, 0, 0, 0
1406 AVX_INSTR punpckhdq, mmx, 0, 0, 0
1407 AVX_INSTR punpckhqdq, sse2, 0, 0, 0
1408 AVX_INSTR punpcklbw, mmx, 0, 0, 0
1409 AVX_INSTR punpcklwd, mmx, 0, 0, 0
1410 AVX_INSTR punpckldq, mmx, 0, 0, 0
1411 AVX_INSTR punpcklqdq, sse2, 0, 0, 0
1412 AVX_INSTR pxor, mmx, 0, 0, 1
1413 AVX_INSTR rcpps, sse, 1, 0, 0
1414 AVX_INSTR rcpss, sse, 1, 0, 0
1415 AVX_INSTR roundpd, sse4
1416 AVX_INSTR roundps, sse4
1417 AVX_INSTR roundsd, sse4
1418 AVX_INSTR roundss, sse4
1419 AVX_INSTR rsqrtps, sse, 1, 0, 0
1420 AVX_INSTR rsqrtss, sse, 1, 0, 0
1421 AVX_INSTR shufpd, sse2, 1, 1, 0
1422 AVX_INSTR shufps, sse, 1, 1, 0
1423 AVX_INSTR sqrtpd, sse2, 1, 0, 0
1424 AVX_INSTR sqrtps, sse, 1, 0, 0
1425 AVX_INSTR sqrtsd, sse2, 1, 0, 0
1426 AVX_INSTR sqrtss, sse, 1, 0, 0
1427 AVX_INSTR stmxcsr, sse
1428 AVX_INSTR subpd, sse2, 1, 0, 0
1429 AVX_INSTR subps, sse, 1, 0, 0
1430 AVX_INSTR subsd, sse2, 1, 0, 0
1431 AVX_INSTR subss, sse, 1, 0, 0
1432 AVX_INSTR ucomisd, sse2
1433 AVX_INSTR ucomiss, sse
1434 AVX_INSTR unpckhpd, sse2, 1, 0, 0
1435 AVX_INSTR unpckhps, sse, 1, 0, 0
1436 AVX_INSTR unpcklpd, sse2, 1, 0, 0
1437 AVX_INSTR unpcklps, sse, 1, 0, 0
1438 AVX_INSTR xorpd, sse2, 1, 0, 1
1439 AVX_INSTR xorps, sse, 1, 0, 1
1441 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1442 AVX_INSTR pfadd, 3dnow, 1, 0, 1
1443 AVX_INSTR pfsub, 3dnow, 1, 0, 0
1444 AVX_INSTR pfmul, 3dnow, 1, 0, 1
1446 ; base-4 constants for shuffles
1449 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1451 CAT_XDEFINE q000, j, i
1453 CAT_XDEFINE q00, j, i
1455 CAT_XDEFINE q0, j, i
1465 %macro %1 4-7 %1, %2, %3
1472 %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported
1477 FMA_INSTR pmacsww, pmullw, paddw
1478 FMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation
1479 FMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation
1480 FMA_INSTR pmadcswd, pmaddwd, paddd
1482 ; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1483 ; This lets us use tzcnt without bumping the yasm version requirement yet.
1484 %define tzcnt rep bsf
1486 ; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.
1487 ; FMA3 is only possible if dst is the same as one of the src registers.
1488 ; Either src2 or src3 can be a memory operand.
1489 %macro FMA4_INSTR 2-*
1491 %xdefine %$prefix %1
1493 %macro %$prefix%2 4-6 %$prefix, %2
1494 %if notcpuflag(fma3) && notcpuflag(fma4)
1495 %error use of ``%5%6'' fma instruction in cpuname function: current_function
1497 v%5%6 %1, %2, %3, %4
1499 ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.
1501 v%{5}213%6 %2, %3, %4
1503 v%{5}132%6 %2, %4, %3
1506 v%{5}213%6 %3, %2, %4
1508 v%{5}231%6 %4, %2, %3
1510 %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported
1518 FMA4_INSTR fmadd, pd, ps, sd, ss
1519 FMA4_INSTR fmaddsub, pd, ps
1520 FMA4_INSTR fmsub, pd, ps, sd, ss
1521 FMA4_INSTR fmsubadd, pd, ps
1522 FMA4_INSTR fnmadd, pd, ps, sd, ss
1523 FMA4_INSTR fnmsub, pd, ps, sd, ss
1525 ; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug (fixed in 1.3.0)
1527 %if __YASM_VERSION_ID__ < 0x01030000 && ARCH_X86_64 == 0
1528 %macro vpbroadcastq 2